1 # Cell Broadband Engine possible unit masks 2 # 3 # Copyright OProfile authors 4 # 5 #(C) COPYRIGHT International Business Machines Corp. 2006 6 # Contributed by Maynard Johnson <maynardj (a] us.ibm.com> 7 # 8 # 9 name:zero type:mandatory default:0x0 10 0x000 Count cycles [mandatory] 11 name:PPU_0_cycles type:bitmask default:0x013 12 0x001 Count cycles [mandatory] 13 0x000 Negative polarity [optional ] 14 0x002 Positive polarity [default ] 15 0x010 PPU Bus Word 0 [mandatory] 16 name:PPU_0_edges type:bitmask default:0x012 17 0x000 Count edges [mandatory] 18 0x000 Negative polarity [optional ] 19 0x002 Positive polarity [default ] 20 0x010 PPU Bus Word 0 [mandatory] 21 name:PPU_2_cycles type:bitmask default:0x043 22 0x001 Count cycles [mandatory] 23 0x000 Negative polarity [optional ] 24 0x002 Positive polarity [default ] 25 0x040 PPU Bus Word 2 [mandatory] 26 name:PPU_2_edges type:bitmask default:0x042 27 0x000 Count edges [mandatory] 28 0x000 Negative polarity [optional ] 29 0x002 Positive polarity [default ] 30 0x040 PPU Bus Word 2 [mandatory] 31 name:PPU_01_cycles type:bitmask default:0x023 32 0x001 Count cycles [mandatory] 33 0x000 Negative polarity [optional ] 34 0x002 Positive polarity [default ] 35 0x010 PPU Bus Word 0 [optional ] 36 0x020 PPU Bus Word 1 [default ] 37 name:PPU_01_edges type:bitmask default:0x022 38 0x000 Count edges [mandatory] 39 0x000 Negative polarity [optional ] 40 0x002 Positive polarity [default ] 41 0x010 PPU Bus Word 0 [optional ] 42 0x020 PPU Bus Word 1 [default ] 43 name:PPU_01_cycles_or_edges type:bitmask default:0x023 44 0x000 Count edges [optional ] 45 0x001 Count cycles [default ] 46 0x000 Negative polarity [optional ] 47 0x002 Positive polarity [default ] 48 0x010 PPU Bus Word 0 [optional ] 49 0x020 PPU Bus Word 1 [default ] 50 name:PPU_02_cycles type:bitmask default:0x013 51 0x001 Count cycles [mandatory] 52 0x000 Negative polarity [optional ] 53 0x002 Positive polarity [default ] 54 0x010 PPU Bus Word 0 [default ] 55 0x040 PPU Bus Word 2 [optional ] 56 name:PPU_02_edges type:bitmask default:0x012 57 0x000 Count edges [mandatory] 58 0x000 Negative polarity [optional ] 59 0x002 Positive polarity [default ] 60 0x010 PPU Bus Word 0 [default ] 61 0x040 PPU Bus Word 2 [optional ] 62 name:PPU_02_cycles_or_edges type:bitmask default:0x013 63 0x000 Count edges [optional ] 64 0x001 Count cycles [default ] 65 0x000 Negative polarity [optional ] 66 0x002 Positive polarity [default ] 67 0x010 PPU Bus Word 0 [default ] 68 0x040 PPU Bus Word 2 [optional ] 69 name:PPU_0123_cycles type:bitmask default:0x033 70 0x001 Count cycles [mandatory] 71 0x000 Negative polarity [optional ] 72 0x002 Positive polarity [default ] 73 0x030 PPU Bus Word 0/1 [default ] 74 0x0c0 PPU Bus Word 2/3 [optional ] 75 name:SPU_02_cycles type:bitmask default:0x0113 76 0x0001 Count cycles [mandatory] 77 0x0000 Negative polarity [optional ] 78 0x0002 Positive polarity [default ] 79 0x0110 SPU Bus Word 0 [default ] 80 0x0140 SPU Bus Word 2 [optional ] 81 0x0000 SPU 0 [default ] 82 0x1000 SPU 1 [optional ] 83 0x2000 SPU 2 [optional ] 84 0x3000 SPU 3 [optional ] 85 0x4000 SPU 4 [optional ] 86 0x5000 SPU 5 [optional ] 87 0x6000 SPU 6 [optional ] 88 0x7000 SPU 7 [optional ] 89 name:SPU_02_cycles_or_edges type:bitmask default:0x0113 90 0x0000 Count edges [optional ] 91 0x0001 Count cycles [default ] 92 0x0000 Negative polarity [optional ] 93 0x0002 Positive polarity [default ] 94 0x0110 SPU Bus Word 0 [default ] 95 0x0140 SPU Bus Word 2 [optional ] 96 0x0000 SPU 0 [default ] 97 0x1000 SPU 1 [optional ] 98 0x2000 SPU 2 [optional ] 99 0x3000 SPU 3 [optional ] 100 0x4000 SPU 4 [optional ] 101 0x5000 SPU 5 [optional ] 102 0x6000 SPU 6 [optional ] 103 0x7000 SPU 7 [optional ] 104 name:SPU_Trigger_cycles_or_edges type:bitmask default:0x0107 105 0x0000 Count edges [optional ] 106 0x0001 Count cycles [default ] 107 0x0000 Negative polarity [optional ] 108 0x0002 Positive polarity [default ] 109 0x0104 SPU Trigger 0 [default ] 110 0x0114 SPU Trigger 1 [optional ] 111 0x0124 SPU Trigger 2 [optional ] 112 0x0134 SPU Trigger 3 [optional ] 113 0x0000 SPU 0 [default ] 114 0x1000 SPU 1 [optional ] 115 0x2000 SPU 2 [optional ] 116 0x3000 SPU 3 [optional ] 117 0x4000 SPU 4 [optional ] 118 0x5000 SPU 5 [optional ] 119 0x6000 SPU 6 [optional ] 120 0x7000 SPU 7 [optional ] 121 name:SPU_Event_cycles_or_edges type:bitmask default:0x0147 122 0x0000 Count edges [optional ] 123 0x0001 Count cycles [default ] 124 0x0000 Negative polarity [optional ] 125 0x0002 Positive polarity [default ] 126 0x0144 SPU Event 0 [default ] 127 0x0154 SPU Event 1 [optional ] 128 0x0164 SPU Event 2 [optional ] 129 0x0174 SPU Event 3 [optional ] 130 0x0000 SPU 0 [default ] 131 0x1000 SPU 1 [optional ] 132 0x2000 SPU 2 [optional ] 133 0x3000 SPU 3 [optional ] 134 0x4000 SPU 4 [optional ] 135 0x5000 SPU 5 [optional ] 136 0x6000 SPU 6 [optional ] 137 0x7000 SPU 7 [optional ] 138
