1 This is as.info, produced by makeinfo version 4.13 from 2 /Volumes/androidtc/androidtoolchain/./src/build/../binutils/binutils-2.21/gas/doc/as.texinfo. 3 4 INFO-DIR-SECTION Software development 5 START-INFO-DIR-ENTRY 6 * As: (as). The GNU assembler. 7 * Gas: (as). The GNU assembler. 8 END-INFO-DIR-ENTRY 9 10 This file documents the GNU Assembler "as". 11 12 Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 13 2000, 2001, 2002, 2006, 2007, 2008, 2009, 2010 Free Software 14 Foundation, Inc. 15 16 Permission is granted to copy, distribute and/or modify this document 17 under the terms of the GNU Free Documentation License, Version 1.3 or 18 any later version published by the Free Software Foundation; with no 19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 20 Texts. A copy of the license is included in the section entitled "GNU 21 Free Documentation License". 22 23 24 File: as.info, Node: Top, Next: Overview, Up: (dir) 25 26 Using as 27 ******** 28 29 This file is a user guide to the GNU assembler `as' (GNU Binutils) 30 version 2.21. 31 32 This document is distributed under the terms of the GNU Free 33 Documentation License. A copy of the license is included in the 34 section entitled "GNU Free Documentation License". 35 36 * Menu: 37 38 * Overview:: Overview 39 * Invoking:: Command-Line Options 40 * Syntax:: Syntax 41 * Sections:: Sections and Relocation 42 * Symbols:: Symbols 43 * Expressions:: Expressions 44 * Pseudo Ops:: Assembler Directives 45 46 * Object Attributes:: Object Attributes 47 * Machine Dependencies:: Machine Dependent Features 48 * Reporting Bugs:: Reporting Bugs 49 * Acknowledgements:: Who Did What 50 * GNU Free Documentation License:: GNU Free Documentation License 51 * AS Index:: AS Index 52 53 54 File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 55 56 1 Overview 57 ********** 58 59 Here is a brief summary of how to invoke `as'. For details, see *note 60 Command-Line Options: Invoking. 61 62 as [-a[cdghlns][=FILE]] [-alternate] [-D] 63 [-compress-debug-sections] [-nocompress-debug-sections] 64 [-debug-prefix-map OLD=NEW] 65 [-defsym SYM=VAL] [-f] [-g] [-gstabs] 66 [-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J] 67 [-K] [-L] [-listing-lhs-width=NUM] 68 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] 69 [-listing-cont-lines=NUM] [-keep-locals] [-o 70 OBJFILE] [-R] [-reduce-memory-overheads] [-statistics] 71 [-v] [-version] [-version] [-W] [-warn] 72 [-fatal-warnings] [-w] [-x] [-Z] [@FILE] 73 [-target-help] [TARGET-OPTIONS] 74 [-|FILES ...] 75 76 _Target Alpha options:_ 77 [-mCPU] 78 [-mdebug | -no-mdebug] 79 [-replace | -noreplace] 80 [-relax] [-g] [-GSIZE] 81 [-F] [-32addr] 82 83 _Target ARC options:_ 84 [-marc[5|6|7|8]] 85 [-EB|-EL] 86 87 _Target ARM options:_ 88 [-mcpu=PROCESSOR[+EXTENSION...]] 89 [-march=ARCHITECTURE[+EXTENSION...]] 90 [-mfpu=FLOATING-POINT-FORMAT] 91 [-mfloat-abi=ABI] 92 [-meabi=VER] 93 [-mthumb] 94 [-EB|-EL] 95 [-mapcs-32|-mapcs-26|-mapcs-float| 96 -mapcs-reentrant] 97 [-mthumb-interwork] [-k] 98 99 _Target Blackfin options:_ 100 [-mcpu=PROCESSOR[-SIREVISION]] 101 [-mfdpic] 102 [-mno-fdpic] 103 [-mnopic] 104 105 _Target CRIS options:_ 106 [-underscore | -no-underscore] 107 [-pic] [-N] 108 [-emulation=criself | -emulation=crisaout] 109 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] 110 111 _Target D10V options:_ 112 [-O] 113 114 _Target D30V options:_ 115 [-O|-n|-N] 116 117 _Target H8/300 options:_ 118 [-h-tick-hex] 119 120 _Target i386 options:_ 121 [-32|-64] [-n] 122 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 123 124 _Target i960 options:_ 125 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB| 126 -AKC|-AMC] 127 [-b] [-no-relax] 128 129 _Target IA-64 options:_ 130 [-mconstant-gp|-mauto-pic] 131 [-milp32|-milp64|-mlp64|-mp64] 132 [-mle|mbe] 133 [-mtune=itanium1|-mtune=itanium2] 134 [-munwind-check=warning|-munwind-check=error] 135 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 136 [-x|-xexplicit] [-xauto] [-xdebug] 137 138 _Target IP2K options:_ 139 [-mip2022|-mip2022ext] 140 141 _Target M32C options:_ 142 [-m32c|-m16c] [-relax] [-h-tick-hex] 143 144 _Target M32R options:_ 145 [-m32rx|-[no-]warn-explicit-parallel-conflicts| 146 -W[n]p] 147 148 _Target M680X0 options:_ 149 [-l] [-m68000|-m68010|-m68020|...] 150 151 _Target M68HC11 options:_ 152 [-m68hc11|-m68hc12|-m68hcs12] 153 [-mshort|-mlong] 154 [-mshort-double|-mlong-double] 155 [-force-long-branches] [-short-branches] 156 [-strict-direct-mode] [-print-insn-syntax] 157 [-print-opcodes] [-generate-example] 158 159 _Target MCORE options:_ 160 [-jsri2bsr] [-sifilter] [-relax] 161 [-mcpu=[210|340]] 162 _Target MICROBLAZE options:_ 163 164 _Target MIPS options:_ 165 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 166 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 167 [-non_shared] [-xgot [-mvxworks-pic] 168 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 169 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 170 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 171 [-mips64] [-mips64r2] 172 [-construct-floats] [-no-construct-floats] 173 [-trap] [-no-break] [-break] [-no-trap] 174 [-mips16] [-no-mips16] 175 [-msmartmips] [-mno-smartmips] 176 [-mips3d] [-no-mips3d] 177 [-mdmx] [-no-mdmx] 178 [-mdsp] [-mno-dsp] 179 [-mdspr2] [-mno-dspr2] 180 [-mmt] [-mno-mt] 181 [-mfix7000] [-mno-fix7000] 182 [-mfix-vr4120] [-mno-fix-vr4120] 183 [-mfix-vr4130] [-mno-fix-vr4130] 184 [-mdebug] [-no-mdebug] 185 [-mpdr] [-mno-pdr] 186 187 _Target MMIX options:_ 188 [-fixed-special-register-names] [-globalize-symbols] 189 [-gnu-syntax] [-relax] [-no-predefined-symbols] 190 [-no-expand] [-no-merge-gregs] [-x] 191 [-linker-allocated-gregs] 192 193 _Target PDP11 options:_ 194 [-mpic|-mno-pic] [-mall] [-mno-extensions] 195 [-mEXTENSION|-mno-EXTENSION] 196 [-mCPU] [-mMACHINE] 197 198 _Target picoJava options:_ 199 [-mb|-me] 200 201 _Target PowerPC options:_ 202 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604| 203 -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke] 204 [-mcom|-many|-maltivec|-mvsx] [-memb] 205 [-mregnames|-mno-regnames] 206 [-mrelocatable|-mrelocatable-lib] 207 [-mlittle|-mlittle-endian|-mbig|-mbig-endian] 208 [-msolaris|-mno-solaris] 209 210 _Target RX options:_ 211 [-mlittle-endian|-mbig-endian] 212 [-m32bit-ints|-m16bit-ints] 213 [-m32bit-doubles|-m64bit-doubles] 214 215 _Target s390 options:_ 216 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 217 [-mregnames|-mno-regnames] 218 [-mwarn-areg-zero] 219 220 _Target SCORE options:_ 221 [-EB][-EL][-FIXDD][-NWARN] 222 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 223 [-march=score7][-march=score3] 224 [-USE_R1][-KPIC][-O0][-G NUM][-V] 225 226 _Target SPARC options:_ 227 [-Av6|-Av7|-Av8|-Asparclet|-Asparclite 228 -Av8plus|-Av8plusa|-Av9|-Av9a] 229 [-xarch=v8plus|-xarch=v8plusa] [-bump] 230 [-32|-64] 231 232 _Target TIC54X options:_ 233 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 234 [-merrors-to-file <FILENAME>|-me <FILENAME>] 235 236 237 _Target TIC6X options:_ 238 [-march=ARCH] [-matomic|-mno-atomic] 239 [-mbig-endian|-mlittle-endian] [-mdsbt|-mno-dsbt] 240 [-mpid=no|-mpid=near|-mpid=far] [-mpic|-mno-pic] 241 242 243 _Target Z80 options:_ 244 [-z80] [-r800] 245 [ -ignore-undocumented-instructions] [-Wnud] 246 [ -ignore-unportable-instructions] [-Wnup] 247 [ -warn-undocumented-instructions] [-Wud] 248 [ -warn-unportable-instructions] [-Wup] 249 [ -forbid-undocumented-instructions] [-Fud] 250 [ -forbid-unportable-instructions] [-Fup] 251 252 253 _Target Xtensa options:_ 254 [-[no-]text-section-literals] [-[no-]absolute-literals] 255 [-[no-]target-align] [-[no-]longcalls] 256 [-[no-]transform] 257 [-rename-section OLDNAME=NEWNAME] 258 259 `@FILE' 260 Read command-line options from FILE. The options read are 261 inserted in place of the original @FILE option. If FILE does not 262 exist, or cannot be read, then the option will be treated 263 literally, and not removed. 264 265 Options in FILE are separated by whitespace. A whitespace 266 character may be included in an option by surrounding the entire 267 option in either single or double quotes. Any character 268 (including a backslash) may be included by prefixing the character 269 to be included with a backslash. The FILE may itself contain 270 additional @FILE options; any such options will be processed 271 recursively. 272 273 `-a[cdghlmns]' 274 Turn on listings, in any of a variety of ways: 275 276 `-ac' 277 omit false conditionals 278 279 `-ad' 280 omit debugging directives 281 282 `-ag' 283 include general information, like as version and options 284 passed 285 286 `-ah' 287 include high-level source 288 289 `-al' 290 include assembly 291 292 `-am' 293 include macro expansions 294 295 `-an' 296 omit forms processing 297 298 `-as' 299 include symbols 300 301 `=file' 302 set the name of the listing file 303 304 You may combine these options; for example, use `-aln' for assembly 305 listing without forms processing. The `=file' option, if used, 306 must be the last one. By itself, `-a' defaults to `-ahls'. 307 308 `--alternate' 309 Begin in alternate macro mode. *Note `.altmacro': Altmacro. 310 311 `--compress-debug-sections' 312 Compress DWARF debug sections using zlib. The debug sections are 313 renamed to begin with `.zdebug', and the resulting object file may 314 not be compatible with older linkers and object file utilities. 315 316 `--nocompress-debug-sections' 317 Do not compress DWARF debug sections. This is the default. 318 319 `-D' 320 Ignored. This option is accepted for script compatibility with 321 calls to other assemblers. 322 323 `--debug-prefix-map OLD=NEW' 324 When assembling files in directory `OLD', record debugging 325 information describing them as in `NEW' instead. 326 327 `--defsym SYM=VALUE' 328 Define the symbol SYM to be VALUE before assembling the input file. 329 VALUE must be an integer constant. As in C, a leading `0x' 330 indicates a hexadecimal value, and a leading `0' indicates an octal 331 value. The value of the symbol can be overridden inside a source 332 file via the use of a `.set' pseudo-op. 333 334 `-f' 335 "fast"--skip whitespace and comment preprocessing (assume source is 336 compiler output). 337 338 `-g' 339 `--gen-debug' 340 Generate debugging information for each assembler source line 341 using whichever debug format is preferred by the target. This 342 currently means either STABS, ECOFF or DWARF2. 343 344 `--gstabs' 345 Generate stabs debugging information for each assembler line. This 346 may help debugging assembler code, if the debugger can handle it. 347 348 `--gstabs+' 349 Generate stabs debugging information for each assembler line, with 350 GNU extensions that probably only gdb can handle, and that could 351 make other debuggers crash or refuse to read your program. This 352 may help debugging assembler code. Currently the only GNU 353 extension is the location of the current working directory at 354 assembling time. 355 356 `--gdwarf-2' 357 Generate DWARF2 debugging information for each assembler line. 358 This may help debugging assembler code, if the debugger can handle 359 it. Note--this option is only supported by some targets, not all 360 of them. 361 362 `--help' 363 Print a summary of the command line options and exit. 364 365 `--target-help' 366 Print a summary of all target specific options and exit. 367 368 `-I DIR' 369 Add directory DIR to the search list for `.include' directives. 370 371 `-J' 372 Don't warn about signed overflow. 373 374 `-K' 375 Issue warnings when difference tables altered for long 376 displacements. 377 378 `-L' 379 `--keep-locals' 380 Keep (in the symbol table) local symbols. These symbols start with 381 system-specific local label prefixes, typically `.L' for ELF 382 systems or `L' for traditional a.out systems. *Note Symbol 383 Names::. 384 385 `--listing-lhs-width=NUMBER' 386 Set the maximum width, in words, of the output data column for an 387 assembler listing to NUMBER. 388 389 `--listing-lhs-width2=NUMBER' 390 Set the maximum width, in words, of the output data column for 391 continuation lines in an assembler listing to NUMBER. 392 393 `--listing-rhs-width=NUMBER' 394 Set the maximum width of an input source line, as displayed in a 395 listing, to NUMBER bytes. 396 397 `--listing-cont-lines=NUMBER' 398 Set the maximum number of lines printed in a listing for a single 399 line of input to NUMBER + 1. 400 401 `-o OBJFILE' 402 Name the object-file output from `as' OBJFILE. 403 404 `-R' 405 Fold the data section into the text section. 406 407 Set the default size of GAS's hash tables to a prime number close 408 to NUMBER. Increasing this value can reduce the length of time it 409 takes the assembler to perform its tasks, at the expense of 410 increasing the assembler's memory requirements. Similarly 411 reducing this value can reduce the memory requirements at the 412 expense of speed. 413 414 `--reduce-memory-overheads' 415 This option reduces GAS's memory requirements, at the expense of 416 making the assembly processes slower. Currently this switch is a 417 synonym for `--hash-size=4051', but in the future it may have 418 other effects as well. 419 420 `--statistics' 421 Print the maximum space (in bytes) and total time (in seconds) 422 used by assembly. 423 424 `--strip-local-absolute' 425 Remove local absolute symbols from the outgoing symbol table. 426 427 `-v' 428 `-version' 429 Print the `as' version. 430 431 `--version' 432 Print the `as' version and exit. 433 434 `-W' 435 `--no-warn' 436 Suppress warning messages. 437 438 `--fatal-warnings' 439 Treat warnings as errors. 440 441 `--warn' 442 Don't suppress warning messages or treat them as errors. 443 444 `-w' 445 Ignored. 446 447 `-x' 448 Ignored. 449 450 `-Z' 451 Generate an object file even after errors. 452 453 `-- | FILES ...' 454 Standard input, or source files to assemble. 455 456 457 The following options are available when as is configured for an ARC 458 processor. 459 460 `-marc[5|6|7|8]' 461 This option selects the core processor variant. 462 463 `-EB | -EL' 464 Select either big-endian (-EB) or little-endian (-EL) output. 465 466 The following options are available when as is configured for the ARM 467 processor family. 468 469 `-mcpu=PROCESSOR[+EXTENSION...]' 470 Specify which ARM processor variant is the target. 471 472 `-march=ARCHITECTURE[+EXTENSION...]' 473 Specify which ARM architecture variant is used by the target. 474 475 `-mfpu=FLOATING-POINT-FORMAT' 476 Select which Floating Point architecture is the target. 477 478 `-mfloat-abi=ABI' 479 Select which floating point ABI is in use. 480 481 `-mthumb' 482 Enable Thumb only instruction decoding. 483 484 `-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' 485 Select which procedure calling convention is in use. 486 487 `-EB | -EL' 488 Select either big-endian (-EB) or little-endian (-EL) output. 489 490 `-mthumb-interwork' 491 Specify that the code has been generated with interworking between 492 Thumb and ARM code in mind. 493 494 `-k' 495 Specify that PIC code has been generated. 496 497 The following options are available when as is configured for the 498 Blackfin processor family. 499 500 `-mcpu=PROCESSOR[-SIREVISION]' 501 This option specifies the target processor. The optional 502 SIREVISION is not used in assembler. 503 504 `-mfdpic' 505 Assemble for the FDPIC ABI. 506 507 `-mno-fdpic' 508 `-mnopic' 509 Disable -mfdpic. 510 511 See the info pages for documentation of the CRIS-specific options. 512 513 The following options are available when as is configured for a D10V 514 processor. 515 `-O' 516 Optimize output by parallelizing instructions. 517 518 The following options are available when as is configured for a D30V 519 processor. 520 `-O' 521 Optimize output by parallelizing instructions. 522 523 `-n' 524 Warn when nops are generated. 525 526 `-N' 527 Warn when a nop after a 32-bit multiply instruction is generated. 528 529 The following options are available when as is configured for the 530 Intel 80960 processor. 531 532 `-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 533 Specify which variant of the 960 architecture is the target. 534 535 `-b' 536 Add code to collect statistics about branches taken. 537 538 `-no-relax' 539 Do not alter compare-and-branch instructions for long 540 displacements; error if necessary. 541 542 543 The following options are available when as is configured for the 544 Ubicom IP2K series. 545 546 `-mip2022ext' 547 Specifies that the extended IP2022 instructions are allowed. 548 549 `-mip2022' 550 Restores the default behaviour, which restricts the permitted 551 instructions to just the basic IP2022 ones. 552 553 554 The following options are available when as is configured for the 555 Renesas M32C and M16C processors. 556 557 `-m32c' 558 Assemble M32C instructions. 559 560 `-m16c' 561 Assemble M16C instructions (the default). 562 563 `-relax' 564 Enable support for link-time relaxations. 565 566 `-h-tick-hex' 567 Support H'00 style hex constants in addition to 0x00 style. 568 569 570 The following options are available when as is configured for the 571 Renesas M32R (formerly Mitsubishi M32R) series. 572 573 `--m32rx' 574 Specify which processor in the M32R family is the target. The 575 default is normally the M32R, but this option changes it to the 576 M32RX. 577 578 `--warn-explicit-parallel-conflicts or --Wp' 579 Produce warning messages when questionable parallel constructs are 580 encountered. 581 582 `--no-warn-explicit-parallel-conflicts or --Wnp' 583 Do not produce warning messages when questionable parallel 584 constructs are encountered. 585 586 587 The following options are available when as is configured for the 588 Motorola 68000 series. 589 590 `-l' 591 Shorten references to undefined symbols, to one word instead of 592 two. 593 594 `-m68000 | -m68008 | -m68010 | -m68020 | -m68030' 595 `| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' 596 `| -m68333 | -m68340 | -mcpu32 | -m5200' 597 Specify what processor in the 68000 family is the target. The 598 default is normally the 68020, but this can be changed at 599 configuration time. 600 601 `-m68881 | -m68882 | -mno-68881 | -mno-68882' 602 The target machine does (or does not) have a floating-point 603 coprocessor. The default is to assume a coprocessor for 68020, 604 68030, and cpu32. Although the basic 68000 is not compatible with 605 the 68881, a combination of the two can be specified, since it's 606 possible to do emulation of the coprocessor instructions with the 607 main processor. 608 609 `-m68851 | -mno-68851' 610 The target machine does (or does not) have a memory-management 611 unit coprocessor. The default is to assume an MMU for 68020 and 612 up. 613 614 615 For details about the PDP-11 machine dependent features options, see 616 *note PDP-11-Options::. 617 618 `-mpic | -mno-pic' 619 Generate position-independent (or position-dependent) code. The 620 default is `-mpic'. 621 622 `-mall' 623 `-mall-extensions' 624 Enable all instruction set extensions. This is the default. 625 626 `-mno-extensions' 627 Disable all instruction set extensions. 628 629 `-mEXTENSION | -mno-EXTENSION' 630 Enable (or disable) a particular instruction set extension. 631 632 `-mCPU' 633 Enable the instruction set extensions supported by a particular 634 CPU, and disable all other extensions. 635 636 `-mMACHINE' 637 Enable the instruction set extensions supported by a particular 638 machine model, and disable all other extensions. 639 640 The following options are available when as is configured for a 641 picoJava processor. 642 643 `-mb' 644 Generate "big endian" format output. 645 646 `-ml' 647 Generate "little endian" format output. 648 649 650 The following options are available when as is configured for the 651 Motorola 68HC11 or 68HC12 series. 652 653 `-m68hc11 | -m68hc12 | -m68hcs12' 654 Specify what processor is the target. The default is defined by 655 the configuration option when building the assembler. 656 657 `-mshort' 658 Specify to use the 16-bit integer ABI. 659 660 `-mlong' 661 Specify to use the 32-bit integer ABI. 662 663 `-mshort-double' 664 Specify to use the 32-bit double ABI. 665 666 `-mlong-double' 667 Specify to use the 64-bit double ABI. 668 669 `--force-long-branches' 670 Relative branches are turned into absolute ones. This concerns 671 conditional branches, unconditional branches and branches to a sub 672 routine. 673 674 `-S | --short-branches' 675 Do not turn relative branches into absolute ones when the offset 676 is out of range. 677 678 `--strict-direct-mode' 679 Do not turn the direct addressing mode into extended addressing 680 mode when the instruction does not support direct addressing mode. 681 682 `--print-insn-syntax' 683 Print the syntax of instruction in case of error. 684 685 `--print-opcodes' 686 print the list of instructions with syntax and then exit. 687 688 `--generate-example' 689 print an example of instruction for each possible instruction and 690 then exit. This option is only useful for testing `as'. 691 692 693 The following options are available when `as' is configured for the 694 SPARC architecture: 695 696 `-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 697 `-Av8plus | -Av8plusa | -Av9 | -Av9a' 698 Explicitly select a variant of the SPARC architecture. 699 700 `-Av8plus' and `-Av8plusa' select a 32 bit environment. `-Av9' 701 and `-Av9a' select a 64 bit environment. 702 703 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 704 UltraSPARC extensions. 705 706 `-xarch=v8plus | -xarch=v8plusa' 707 For compatibility with the Solaris v9 assembler. These options are 708 equivalent to -Av8plus and -Av8plusa, respectively. 709 710 `-bump' 711 Warn when the assembler switches to another architecture. 712 713 The following options are available when as is configured for the 714 'c54x architecture. 715 716 `-mfar-mode' 717 Enable extended addressing mode. All addresses and relocations 718 will assume extended addressing (usually 23 bits). 719 720 `-mcpu=CPU_VERSION' 721 Sets the CPU version being compiled for. 722 723 `-merrors-to-file FILENAME' 724 Redirect error output to a file, for broken systems which don't 725 support such behaviour in the shell. 726 727 The following options are available when as is configured for a MIPS 728 processor. 729 730 `-G NUM' 731 This option sets the largest size of an object that can be 732 referenced implicitly with the `gp' register. It is only accepted 733 for targets that use ECOFF format, such as a DECstation running 734 Ultrix. The default value is 8. 735 736 `-EB' 737 Generate "big endian" format output. 738 739 `-EL' 740 Generate "little endian" format output. 741 742 `-mips1' 743 `-mips2' 744 `-mips3' 745 `-mips4' 746 `-mips5' 747 `-mips32' 748 `-mips32r2' 749 `-mips64' 750 `-mips64r2' 751 Generate code for a particular MIPS Instruction Set Architecture 752 level. `-mips1' is an alias for `-march=r3000', `-mips2' is an 753 alias for `-march=r6000', `-mips3' is an alias for `-march=r4000' 754 and `-mips4' is an alias for `-march=r8000'. `-mips5', `-mips32', 755 `-mips32r2', `-mips64', and `-mips64r2' correspond to generic 756 `MIPS V', `MIPS32', `MIPS32 Release 2', `MIPS64', and `MIPS64 757 Release 2' ISA processors, respectively. 758 759 `-march=CPU' 760 Generate code for a particular MIPS cpu. 761 762 `-mtune=CPU' 763 Schedule and tune for a particular MIPS cpu. 764 765 `-mfix7000' 766 `-mno-fix7000' 767 Cause nops to be inserted if the read of the destination register 768 of an mfhi or mflo instruction occurs in the following two 769 instructions. 770 771 `-mdebug' 772 `-no-mdebug' 773 Cause stabs-style debugging output to go into an ECOFF-style 774 .mdebug section instead of the standard ELF .stabs sections. 775 776 `-mpdr' 777 `-mno-pdr' 778 Control generation of `.pdr' sections. 779 780 `-mgp32' 781 `-mfp32' 782 The register sizes are normally inferred from the ISA and ABI, but 783 these flags force a certain group of registers to be treated as 32 784 bits wide at all times. `-mgp32' controls the size of 785 general-purpose registers and `-mfp32' controls the size of 786 floating-point registers. 787 788 `-mips16' 789 `-no-mips16' 790 Generate code for the MIPS 16 processor. This is equivalent to 791 putting `.set mips16' at the start of the assembly file. 792 `-no-mips16' turns off this option. 793 794 `-msmartmips' 795 `-mno-smartmips' 796 Enables the SmartMIPS extension to the MIPS32 instruction set. 797 This is equivalent to putting `.set smartmips' at the start of the 798 assembly file. `-mno-smartmips' turns off this option. 799 800 `-mips3d' 801 `-no-mips3d' 802 Generate code for the MIPS-3D Application Specific Extension. 803 This tells the assembler to accept MIPS-3D instructions. 804 `-no-mips3d' turns off this option. 805 806 `-mdmx' 807 `-no-mdmx' 808 Generate code for the MDMX Application Specific Extension. This 809 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 810 off this option. 811 812 `-mdsp' 813 `-mno-dsp' 814 Generate code for the DSP Release 1 Application Specific Extension. 815 This tells the assembler to accept DSP Release 1 instructions. 816 `-mno-dsp' turns off this option. 817 818 `-mdspr2' 819 `-mno-dspr2' 820 Generate code for the DSP Release 2 Application Specific Extension. 821 This option implies -mdsp. This tells the assembler to accept DSP 822 Release 2 instructions. `-mno-dspr2' turns off this option. 823 824 `-mmt' 825 `-mno-mt' 826 Generate code for the MT Application Specific Extension. This 827 tells the assembler to accept MT instructions. `-mno-mt' turns 828 off this option. 829 830 `--construct-floats' 831 `--no-construct-floats' 832 The `--no-construct-floats' option disables the construction of 833 double width floating point constants by loading the two halves of 834 the value into the two single width floating point registers that 835 make up the double width register. By default 836 `--construct-floats' is selected, allowing construction of these 837 floating point constants. 838 839 `--emulation=NAME' 840 This option causes `as' to emulate `as' configured for some other 841 target, in all respects, including output format (choosing between 842 ELF and ECOFF only), handling of pseudo-opcodes which may generate 843 debugging information or store symbol table information, and 844 default endianness. The available configuration names are: 845 `mipsecoff', `mipself', `mipslecoff', `mipsbecoff', `mipslelf', 846 `mipsbelf'. The first two do not alter the default endianness 847 from that of the primary target for which the assembler was 848 configured; the others change the default to little- or big-endian 849 as indicated by the `b' or `l' in the name. Using `-EB' or `-EL' 850 will override the endianness selection in any case. 851 852 This option is currently supported only when the primary target 853 `as' is configured for is a MIPS ELF or ECOFF target. 854 Furthermore, the primary target or others specified with 855 `--enable-targets=...' at configuration time must include support 856 for the other format, if both are to be available. For example, 857 the Irix 5 configuration includes support for both. 858 859 Eventually, this option will support more configurations, with more 860 fine-grained control over the assembler's behavior, and will be 861 supported for more processors. 862 863 `-nocpp' 864 `as' ignores this option. It is accepted for compatibility with 865 the native tools. 866 867 `--trap' 868 `--no-trap' 869 `--break' 870 `--no-break' 871 Control how to deal with multiplication overflow and division by 872 zero. `--trap' or `--no-break' (which are synonyms) take a trap 873 exception (and only work for Instruction Set Architecture level 2 874 and higher); `--break' or `--no-trap' (also synonyms, and the 875 default) take a break exception. 876 877 `-n' 878 When this option is used, `as' will issue a warning every time it 879 generates a nop instruction from a macro. 880 881 The following options are available when as is configured for an 882 MCore processor. 883 884 `-jsri2bsr' 885 `-nojsri2bsr' 886 Enable or disable the JSRI to BSR transformation. By default this 887 is enabled. The command line option `-nojsri2bsr' can be used to 888 disable it. 889 890 `-sifilter' 891 `-nosifilter' 892 Enable or disable the silicon filter behaviour. By default this 893 is disabled. The default can be overridden by the `-sifilter' 894 command line option. 895 896 `-relax' 897 Alter jump instructions for long displacements. 898 899 `-mcpu=[210|340]' 900 Select the cpu type on the target hardware. This controls which 901 instructions can be assembled. 902 903 `-EB' 904 Assemble for a big endian target. 905 906 `-EL' 907 Assemble for a little endian target. 908 909 910 See the info pages for documentation of the MMIX-specific options. 911 912 See the info pages for documentation of the RX-specific options. 913 914 The following options are available when as is configured for the 915 s390 processor family. 916 917 `-m31' 918 `-m64' 919 Select the word size, either 31/32 bits or 64 bits. 920 921 `-mesa' 922 923 `-mzarch' 924 Select the architecture mode, either the Enterprise System 925 Architecture (esa) or the z/Architecture mode (zarch). 926 927 `-march=PROCESSOR' 928 Specify which s390 processor variant is the target, `g6', `g6', 929 `z900', `z990', `z9-109', `z9-ec', or `z10'. 930 931 `-mregnames' 932 `-mno-regnames' 933 Allow or disallow symbolic names for registers. 934 935 `-mwarn-areg-zero' 936 Warn whenever the operand for a base or index register has been 937 specified but evaluates to zero. 938 939 The following options are available when as is configured for a 940 TMS320C6000 processor. 941 942 `-march=ARCH' 943 Enable (only) instructions from architecture ARCH. By default, 944 all instructions are permitted. 945 946 The following values of ARCH are accepted: `c62x', `c64x', 947 `c64x+', `c67x', `c67x+', `c674x'. 948 949 `-matomic' 950 `-mno-atomic' 951 Enable or disable the optional C64x+ atomic operation instructions. 952 By default, they are enabled if no `-march' option is given, or if 953 an architecture is specified with `-march' that implies these 954 instructions are present (currently, there are no such 955 architectures); they are disabled if an architecture is specified 956 with `-march' on which the instructions are optional or not 957 present. This option overrides such a default from the 958 architecture, independent of the order in which the `-march' or 959 `-matomic' or `-mno-atomic' options are passed. 960 961 `-mdsbt' 962 `-mno-dsbt' 963 The `-mdsbt' option causes the assembler to generate the 964 `Tag_ABI_DSBT' attribute with a value of 1, indicating that the 965 code is using DSBT addressing. The `-mno-dsbt' option, the 966 default, causes the tag to have a value of 0, indicating that the 967 code does not use DSBT addressing. The linker will emit a warning 968 if objects of different type (DSBT and non-DSBT) are linked 969 together. 970 971 `-mpid=no' 972 `-mpid=near' 973 `-mpid=far' 974 The `-mpid=' option causes the assembler to generate the 975 `Tag_ABI_PID' attribute with a value indicating the form of data 976 addressing used by the code. `-mpid=no', the default, indicates 977 position-dependent data addressing, `-mpid=near' indicates 978 position-independent addressing with GOT accesses using near DP 979 addressing, and `-mpid=far' indicates position-independent 980 addressing with GOT accesses using far DP addressing. The linker 981 will emit a warning if objects built with different settings of 982 this option are linked together. 983 984 `-mpic' 985 `-mno-pic' 986 The `-mpic' option causes the assembler to generate the 987 `Tag_ABI_PIC' attribute with a value of 1, indicating that the 988 code is using position-independent code addressing, The 989 `-mno-pic' option, the default, causes the tag to have a value of 990 0, indicating position-dependent code addressing. The linker will 991 emit a warning if objects of different type (position-dependent and 992 position-independent) are linked together. 993 994 `-mbig-endian' 995 `-mlittle-endian' 996 Generate code for the specified endianness. The default is 997 little-endian. 998 999 The following options are available when as is configured for an 1000 Xtensa processor. 1001 1002 `--text-section-literals | --no-text-section-literals' 1003 With `--text-section-literals', literal pools are interspersed in 1004 the text section. The default is `--no-text-section-literals', 1005 which places literals in a separate section in the output file. 1006 These options only affect literals referenced via PC-relative 1007 `L32R' instructions; literals for absolute mode `L32R' 1008 instructions are handled separately. 1009 1010 `--absolute-literals | --no-absolute-literals' 1011 Indicate to the assembler whether `L32R' instructions use absolute 1012 or PC-relative addressing. The default is to assume absolute 1013 addressing if the Xtensa processor includes the absolute `L32R' 1014 addressing option. Otherwise, only the PC-relative `L32R' mode 1015 can be used. 1016 1017 `--target-align | --no-target-align' 1018 Enable or disable automatic alignment to reduce branch penalties 1019 at the expense of some code density. The default is 1020 `--target-align'. 1021 1022 `--longcalls | --no-longcalls' 1023 Enable or disable transformation of call instructions to allow 1024 calls across a greater range of addresses. The default is 1025 `--no-longcalls'. 1026 1027 `--transform | --no-transform' 1028 Enable or disable all assembler transformations of Xtensa 1029 instructions. The default is `--transform'; `--no-transform' 1030 should be used only in the rare cases when the instructions must 1031 be exactly as specified in the assembly source. 1032 1033 `--rename-section OLDNAME=NEWNAME' 1034 When generating output sections, rename the OLDNAME section to 1035 NEWNAME. 1036 1037 The following options are available when as is configured for a Z80 1038 family processor. 1039 `-z80' 1040 Assemble for Z80 processor. 1041 1042 `-r800' 1043 Assemble for R800 processor. 1044 1045 `-ignore-undocumented-instructions' 1046 `-Wnud' 1047 Assemble undocumented Z80 instructions that also work on R800 1048 without warning. 1049 1050 `-ignore-unportable-instructions' 1051 `-Wnup' 1052 Assemble all undocumented Z80 instructions without warning. 1053 1054 `-warn-undocumented-instructions' 1055 `-Wud' 1056 Issue a warning for undocumented Z80 instructions that also work 1057 on R800. 1058 1059 `-warn-unportable-instructions' 1060 `-Wup' 1061 Issue a warning for undocumented Z80 instructions that do not work 1062 on R800. 1063 1064 `-forbid-undocumented-instructions' 1065 `-Fud' 1066 Treat all undocumented instructions as errors. 1067 1068 `-forbid-unportable-instructions' 1069 `-Fup' 1070 Treat undocumented Z80 instructions that do not work on R800 as 1071 errors. 1072 1073 * Menu: 1074 1075 * Manual:: Structure of this Manual 1076 * GNU Assembler:: The GNU Assembler 1077 * Object Formats:: Object File Formats 1078 * Command Line:: Command Line 1079 * Input Files:: Input Files 1080 * Object:: Output (Object) File 1081 * Errors:: Error and Warning Messages 1082 1083 1084 File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1085 1086 1.1 Structure of this Manual 1087 ============================ 1088 1089 This manual is intended to describe what you need to know to use GNU 1090 `as'. We cover the syntax expected in source files, including notation 1091 for symbols, constants, and expressions; the directives that `as' 1092 understands; and of course how to invoke `as'. 1093 1094 This manual also describes some of the machine-dependent features of 1095 various flavors of the assembler. 1096 1097 On the other hand, this manual is _not_ intended as an introduction 1098 to programming in assembly language--let alone programming in general! 1099 In a similar vein, we make no attempt to introduce the machine 1100 architecture; we do _not_ describe the instruction set, standard 1101 mnemonics, registers or addressing modes that are standard to a 1102 particular architecture. You may want to consult the manufacturer's 1103 machine architecture manual for this information. 1104 1105 1106 File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1107 1108 1.2 The GNU Assembler 1109 ===================== 1110 1111 GNU `as' is really a family of assemblers. If you use (or have used) 1112 the GNU assembler on one architecture, you should find a fairly similar 1113 environment when you use it on another architecture. Each version has 1114 much in common with the others, including object file formats, most 1115 assembler directives (often called "pseudo-ops") and assembler syntax. 1116 1117 `as' is primarily intended to assemble the output of the GNU C 1118 compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried 1119 to make `as' assemble correctly everything that other assemblers for 1120 the same machine would assemble. Any exceptions are documented 1121 explicitly (*note Machine Dependencies::). This doesn't mean `as' 1122 always uses the same syntax as another assembler for the same 1123 architecture; for example, we know of several incompatible versions of 1124 680x0 assembly language syntax. 1125 1126 Unlike older assemblers, `as' is designed to assemble a source 1127 program in one pass of the source file. This has a subtle impact on the 1128 `.org' directive (*note `.org': Org.). 1129 1130 1131 File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1132 1133 1.3 Object File Formats 1134 ======================= 1135 1136 The GNU assembler can be configured to produce several alternative 1137 object file formats. For the most part, this does not affect how you 1138 write assembly language programs; but directives for debugging symbols 1139 are typically different in different file formats. *Note Symbol 1140 Attributes: Symbol Attributes. 1141 1142 1143 File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1144 1145 1.4 Command Line 1146 ================ 1147 1148 After the program name `as', the command line may contain options and 1149 file names. Options may appear in any order, and may be before, after, 1150 or between file names. The order of file names is significant. 1151 1152 `--' (two hyphens) by itself names the standard input file 1153 explicitly, as one of the files for `as' to assemble. 1154 1155 Except for `--' any command line argument that begins with a hyphen 1156 (`-') is an option. Each option changes the behavior of `as'. No 1157 option changes the way another option works. An option is a `-' 1158 followed by one or more letters; the case of the letter is important. 1159 All options are optional. 1160 1161 Some options expect exactly one file name to follow them. The file 1162 name may either immediately follow the option's letter (compatible with 1163 older assemblers) or it may be the next command argument (GNU 1164 standard). These two command lines are equivalent: 1165 1166 as -o my-object-file.o mumble.s 1167 as -omy-object-file.o mumble.s 1168 1169 1170 File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1171 1172 1.5 Input Files 1173 =============== 1174 1175 We use the phrase "source program", abbreviated "source", to describe 1176 the program input to one run of `as'. The program may be in one or 1177 more files; how the source is partitioned into files doesn't change the 1178 meaning of the source. 1179 1180 The source program is a concatenation of the text in all the files, 1181 in the order specified. 1182 1183 Each time you run `as' it assembles exactly one source program. The 1184 source program is made up of one or more files. (The standard input is 1185 also a file.) 1186 1187 You give `as' a command line that has zero or more input file names. 1188 The input files are read (from left file name to right). A command 1189 line argument (in any position) that has no special meaning is taken to 1190 be an input file name. 1191 1192 If you give `as' no file names it attempts to read one input file 1193 from the `as' standard input, which is normally your terminal. You may 1194 have to type <ctl-D> to tell `as' there is no more program to assemble. 1195 1196 Use `--' if you need to explicitly name the standard input file in 1197 your command line. 1198 1199 If the source is empty, `as' produces a small, empty object file. 1200 1201 Filenames and Line-numbers 1202 -------------------------- 1203 1204 There are two ways of locating a line in the input file (or files) and 1205 either may be used in reporting error messages. One way refers to a 1206 line number in a physical file; the other refers to a line number in a 1207 "logical" file. *Note Error and Warning Messages: Errors. 1208 1209 "Physical files" are those files named in the command line given to 1210 `as'. 1211 1212 "Logical files" are simply names declared explicitly by assembler 1213 directives; they bear no relation to physical files. Logical file 1214 names help error messages reflect the original source file, when `as' 1215 source is itself synthesized from other files. `as' understands the 1216 `#' directives emitted by the `gcc' preprocessor. See also *note 1217 `.file': File. 1218 1219 1220 File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1221 1222 1.6 Output (Object) File 1223 ======================== 1224 1225 Every time you run `as' it produces an output file, which is your 1226 assembly language program translated into numbers. This file is the 1227 object file. Its default name is `a.out'. You can give it another 1228 name by using the `-o' option. Conventionally, object file names end 1229 with `.o'. The default name is used for historical reasons: older 1230 assemblers were capable of assembling self-contained programs directly 1231 into a runnable program. (For some formats, this isn't currently 1232 possible, but it can be done for the `a.out' format.) 1233 1234 The object file is meant for input to the linker `ld'. It contains 1235 assembled program code, information to help `ld' integrate the 1236 assembled program into a runnable file, and (optionally) symbolic 1237 information for the debugger. 1238 1239 1240 File: as.info, Node: Errors, Prev: Object, Up: Overview 1241 1242 1.7 Error and Warning Messages 1243 ============================== 1244 1245 `as' may write warnings and error messages to the standard error file 1246 (usually your terminal). This should not happen when a compiler runs 1247 `as' automatically. Warnings report an assumption made so that `as' 1248 could keep assembling a flawed program; errors report a grave problem 1249 that stops the assembly. 1250 1251 Warning messages have the format 1252 1253 file_name:NNN:Warning Message Text 1254 1255 (where NNN is a line number). If a logical file name has been given 1256 (*note `.file': File.) it is used for the filename, otherwise the name 1257 of the current input file is used. If a logical line number was given 1258 (*note `.line': Line.) then it is used to calculate the number printed, 1259 otherwise the actual line in the current source file is printed. The 1260 message text is intended to be self explanatory (in the grand Unix 1261 tradition). 1262 1263 Error messages have the format 1264 file_name:NNN:FATAL:Error Message Text 1265 The file name and line number are derived as for warning messages. 1266 The actual message text may be rather less explanatory because many of 1267 them aren't supposed to happen. 1268 1269 1270 File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1271 1272 2 Command-Line Options 1273 ********************** 1274 1275 This chapter describes command-line options available in _all_ versions 1276 of the GNU assembler; see *note Machine Dependencies::, for options 1277 specific to particular machine architectures. 1278 1279 If you are invoking `as' via the GNU C compiler, you can use the 1280 `-Wa' option to pass arguments through to the assembler. The assembler 1281 arguments must be separated from each other (and the `-Wa') by commas. 1282 For example: 1283 1284 gcc -c -g -O -Wa,-alh,-L file.c 1285 1286 This passes two options to the assembler: `-alh' (emit a listing to 1287 standard output with high-level and assembly source) and `-L' (retain 1288 local symbols in the symbol table). 1289 1290 Usually you do not need to use this `-Wa' mechanism, since many 1291 compiler command-line options are automatically passed to the assembler 1292 by the compiler. (You can call the GNU compiler driver with the `-v' 1293 option to see precisely what options it passes to each compilation 1294 pass, including the assembler.) 1295 1296 * Menu: 1297 1298 * a:: -a[cdghlns] enable listings 1299 * alternate:: --alternate enable alternate macro syntax 1300 * D:: -D for compatibility 1301 * f:: -f to work faster 1302 * I:: -I for .include search path 1303 1304 * K:: -K for difference tables 1305 1306 * L:: -L to retain local symbols 1307 * listing:: --listing-XXX to configure listing output 1308 * M:: -M or --mri to assemble in MRI compatibility mode 1309 * MD:: --MD for dependency tracking 1310 * o:: -o to name the object file 1311 * R:: -R to join data and text sections 1312 * statistics:: --statistics to see statistics about assembly 1313 * traditional-format:: --traditional-format for compatible output 1314 * v:: -v to announce version 1315 * W:: -W, --no-warn, --warn, --fatal-warnings to control warnings 1316 * Z:: -Z to make object file even after errors 1317 1318 1319 File: as.info, Node: a, Next: alternate, Up: Invoking 1320 1321 2.1 Enable Listings: `-a[cdghlns]' 1322 ================================== 1323 1324 These options enable listing output from the assembler. By itself, 1325 `-a' requests high-level, assembly, and symbols listing. You can use 1326 other letters to select specific options for the list: `-ah' requests a 1327 high-level language listing, `-al' requests an output-program assembly 1328 listing, and `-as' requests a symbol table listing. High-level 1329 listings require that a compiler debugging option like `-g' be used, 1330 and that assembly listings (`-al') be requested also. 1331 1332 Use the `-ag' option to print a first section with general assembly 1333 information, like as version, switches passed, or time stamp. 1334 1335 Use the `-ac' option to omit false conditionals from a listing. Any 1336 lines which are not assembled because of a false `.if' (or `.ifdef', or 1337 any other conditional), or a true `.if' followed by an `.else', will be 1338 omitted from the listing. 1339 1340 Use the `-ad' option to omit debugging directives from the listing. 1341 1342 Once you have specified one of these options, you can further control 1343 listing output and its appearance using the directives `.list', 1344 `.nolist', `.psize', `.eject', `.title', and `.sbttl'. The `-an' 1345 option turns off all forms processing. If you do not request listing 1346 output with one of the `-a' options, the listing-control directives 1347 have no effect. 1348 1349 The letters after `-a' may be combined into one option, _e.g._, 1350 `-aln'. 1351 1352 Note if the assembler source is coming from the standard input (e.g., 1353 because it is being created by `gcc' and the `-pipe' command line switch 1354 is being used) then the listing will not contain any comments or 1355 preprocessor directives. This is because the listing code buffers 1356 input source lines from stdin only after they have been preprocessed by 1357 the assembler. This reduces memory usage and makes the code more 1358 efficient. 1359 1360 1361 File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1362 1363 2.2 `--alternate' 1364 ================= 1365 1366 Begin in alternate macro mode, see *note `.altmacro': Altmacro. 1367 1368 1369 File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1370 1371 2.3 `-D' 1372 ======== 1373 1374 This option has no effect whatsoever, but it is accepted to make it more 1375 likely that scripts written for other assemblers also work with `as'. 1376 1377 1378 File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1379 1380 2.4 Work Faster: `-f' 1381 ===================== 1382 1383 `-f' should only be used when assembling programs written by a 1384 (trusted) compiler. `-f' stops the assembler from doing whitespace and 1385 comment preprocessing on the input file(s) before assembling them. 1386 *Note Preprocessing: Preprocessing. 1387 1388 _Warning:_ if you use `-f' when the files actually need to be 1389 preprocessed (if they contain comments, for example), `as' does 1390 not work correctly. 1391 1392 1393 File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1394 1395 2.5 `.include' Search Path: `-I' PATH 1396 ===================================== 1397 1398 Use this option to add a PATH to the list of directories `as' searches 1399 for files specified in `.include' directives (*note `.include': 1400 Include.). You may use `-I' as many times as necessary to include a 1401 variety of paths. The current working directory is always searched 1402 first; after that, `as' searches any `-I' directories in the same order 1403 as they were specified (left to right) on the command line. 1404 1405 1406 File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1407 1408 2.6 Difference Tables: `-K' 1409 =========================== 1410 1411 `as' sometimes alters the code emitted for directives of the form 1412 `.word SYM1-SYM2'. *Note `.word': Word. You can use the `-K' option 1413 if you want a warning issued when this is done. 1414 1415 1416 File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1417 1418 2.7 Include Local Symbols: `-L' 1419 =============================== 1420 1421 Symbols beginning with system-specific local label prefixes, typically 1422 `.L' for ELF systems or `L' for traditional a.out systems, are called 1423 "local symbols". *Note Symbol Names::. Normally you do not see such 1424 symbols when debugging, because they are intended for the use of 1425 programs (like compilers) that compose assembler programs, not for your 1426 notice. Normally both `as' and `ld' discard such symbols, so you do 1427 not normally debug with them. 1428 1429 This option tells `as' to retain those local symbols in the object 1430 file. Usually if you do this you also tell the linker `ld' to preserve 1431 those symbols. 1432 1433 1434 File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1435 1436 2.8 Configuring listing output: `--listing' 1437 =========================================== 1438 1439 The listing feature of the assembler can be enabled via the command 1440 line switch `-a' (*note a::). This feature combines the input source 1441 file(s) with a hex dump of the corresponding locations in the output 1442 object file, and displays them as a listing file. The format of this 1443 listing can be controlled by directives inside the assembler source 1444 (i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl' 1445 (*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::) 1446 and also by the following switches: 1447 1448 `--listing-lhs-width=`number'' 1449 Sets the maximum width, in words, of the first line of the hex 1450 byte dump. This dump appears on the left hand side of the listing 1451 output. 1452 1453 `--listing-lhs-width2=`number'' 1454 Sets the maximum width, in words, of any further lines of the hex 1455 byte dump for a given input source line. If this value is not 1456 specified, it defaults to being the same as the value specified 1457 for `--listing-lhs-width'. If neither switch is used the default 1458 is to one. 1459 1460 `--listing-rhs-width=`number'' 1461 Sets the maximum width, in characters, of the source line that is 1462 displayed alongside the hex dump. The default value for this 1463 parameter is 100. The source line is displayed on the right hand 1464 side of the listing output. 1465 1466 `--listing-cont-lines=`number'' 1467 Sets the maximum number of continuation lines of hex dump that 1468 will be displayed for a given single line of source input. The 1469 default value is 4. 1470 1471 1472 File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1473 1474 2.9 Assemble in MRI Compatibility Mode: `-M' 1475 ============================================ 1476 1477 The `-M' or `--mri' option selects MRI compatibility mode. This 1478 changes the syntax and pseudo-op handling of `as' to make it compatible 1479 with the `ASM68K' or the `ASM960' (depending upon the configured 1480 target) assembler from Microtec Research. The exact nature of the MRI 1481 syntax will not be documented here; see the MRI manuals for more 1482 information. Note in particular that the handling of macros and macro 1483 arguments is somewhat different. The purpose of this option is to 1484 permit assembling existing MRI assembler code using `as'. 1485 1486 The MRI compatibility is not complete. Certain operations of the 1487 MRI assembler depend upon its object file format, and can not be 1488 supported using other object file formats. Supporting these would 1489 require enhancing each object file format individually. These are: 1490 1491 * global symbols in common section 1492 1493 The m68k MRI assembler supports common sections which are merged 1494 by the linker. Other object file formats do not support this. 1495 `as' handles common sections by treating them as a single common 1496 symbol. It permits local symbols to be defined within a common 1497 section, but it can not support global symbols, since it has no 1498 way to describe them. 1499 1500 * complex relocations 1501 1502 The MRI assemblers support relocations against a negated section 1503 address, and relocations which combine the start addresses of two 1504 or more sections. These are not support by other object file 1505 formats. 1506 1507 * `END' pseudo-op specifying start address 1508 1509 The MRI `END' pseudo-op permits the specification of a start 1510 address. This is not supported by other object file formats. The 1511 start address may instead be specified using the `-e' option to 1512 the linker, or in a linker script. 1513 1514 * `IDNT', `.ident' and `NAME' pseudo-ops 1515 1516 The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module 1517 name to the output file. This is not supported by other object 1518 file formats. 1519 1520 * `ORG' pseudo-op 1521 1522 The m68k MRI `ORG' pseudo-op begins an absolute section at a given 1523 address. This differs from the usual `as' `.org' pseudo-op, which 1524 changes the location within the current section. Absolute 1525 sections are not supported by other object file formats. The 1526 address of a section may be assigned within a linker script. 1527 1528 There are some other features of the MRI assembler which are not 1529 supported by `as', typically either because they are difficult or 1530 because they seem of little consequence. Some of these may be 1531 supported in future releases. 1532 1533 * EBCDIC strings 1534 1535 EBCDIC strings are not supported. 1536 1537 * packed binary coded decimal 1538 1539 Packed binary coded decimal is not supported. This means that the 1540 `DC.P' and `DCB.P' pseudo-ops are not supported. 1541 1542 * `FEQU' pseudo-op 1543 1544 The m68k `FEQU' pseudo-op is not supported. 1545 1546 * `NOOBJ' pseudo-op 1547 1548 The m68k `NOOBJ' pseudo-op is not supported. 1549 1550 * `OPT' branch control options 1551 1552 The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL', 1553 and `BRW'--are ignored. `as' automatically relaxes all branches, 1554 whether forward or backward, to an appropriate size, so these 1555 options serve no purpose. 1556 1557 * `OPT' list control options 1558 1559 The following m68k `OPT' list control options are ignored: `C', 1560 `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'. 1561 1562 * other `OPT' options 1563 1564 The following m68k `OPT' options are ignored: `NEST', `O', `OLD', 1565 `OP', `P', `PCO', `PCR', `PCS', `R'. 1566 1567 * `OPT' `D' option is default 1568 1569 The m68k `OPT' `D' option is the default, unlike the MRI assembler. 1570 `OPT NOD' may be used to turn it off. 1571 1572 * `XREF' pseudo-op. 1573 1574 The m68k `XREF' pseudo-op is ignored. 1575 1576 * `.debug' pseudo-op 1577 1578 The i960 `.debug' pseudo-op is not supported. 1579 1580 * `.extended' pseudo-op 1581 1582 The i960 `.extended' pseudo-op is not supported. 1583 1584 * `.list' pseudo-op. 1585 1586 The various options of the i960 `.list' pseudo-op are not 1587 supported. 1588 1589 * `.optimize' pseudo-op 1590 1591 The i960 `.optimize' pseudo-op is not supported. 1592 1593 * `.output' pseudo-op 1594 1595 The i960 `.output' pseudo-op is not supported. 1596 1597 * `.setreal' pseudo-op 1598 1599 The i960 `.setreal' pseudo-op is not supported. 1600 1601 1602 1603 File: as.info, Node: MD, Next: o, Prev: M, Up: Invoking 1604 1605 2.10 Dependency Tracking: `--MD' 1606 ================================ 1607 1608 `as' can generate a dependency file for the file it creates. This file 1609 consists of a single rule suitable for `make' describing the 1610 dependencies of the main source file. 1611 1612 The rule is written to the file named in its argument. 1613 1614 This feature is used in the automatic updating of makefiles. 1615 1616 1617 File: as.info, Node: o, Next: R, Prev: MD, Up: Invoking 1618 1619 2.11 Name the Object File: `-o' 1620 =============================== 1621 1622 There is always one object file output when you run `as'. By default 1623 it has the name `a.out' (or `b.out', for Intel 960 targets only). You 1624 use this option (which takes exactly one filename) to give the object 1625 file a different name. 1626 1627 Whatever the object file is called, `as' overwrites any existing 1628 file of the same name. 1629 1630 1631 File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1632 1633 2.12 Join Data and Text Sections: `-R' 1634 ====================================== 1635 1636 `-R' tells `as' to write the object file as if all data-section data 1637 lives in the text section. This is only done at the very last moment: 1638 your binary data are the same, but data section parts are relocated 1639 differently. The data section part of your object file is zero bytes 1640 long because all its bytes are appended to the text section. (*Note 1641 Sections and Relocation: Sections.) 1642 1643 When you specify `-R' it would be possible to generate shorter 1644 address displacements (because we do not have to cross between text and 1645 data section). We refrain from doing this simply for compatibility with 1646 older versions of `as'. In future, `-R' may work this way. 1647 1648 When `as' is configured for COFF or ELF output, this option is only 1649 useful if you use sections named `.text' and `.data'. 1650 1651 `-R' is not supported for any of the HPPA targets. Using `-R' 1652 generates a warning from `as'. 1653 1654 1655 File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1656 1657 2.13 Display Assembly Statistics: `--statistics' 1658 ================================================ 1659 1660 Use `--statistics' to display two statistics about the resources used by 1661 `as': the maximum amount of space allocated during the assembly (in 1662 bytes), and the total execution time taken for the assembly (in CPU 1663 seconds). 1664 1665 1666 File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1667 1668 2.14 Compatible Output: `--traditional-format' 1669 ============================================== 1670 1671 For some targets, the output of `as' is different in some ways from the 1672 output of some existing assembler. This switch requests `as' to use 1673 the traditional format instead. 1674 1675 For example, it disables the exception frame optimizations which 1676 `as' normally does by default on `gcc' output. 1677 1678 1679 File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1680 1681 2.15 Announce Version: `-v' 1682 =========================== 1683 1684 You can find out what version of as is running by including the option 1685 `-v' (which you can also spell as `-version') on the command line. 1686 1687 1688 File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1689 1690 2.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings' 1691 ====================================================================== 1692 1693 `as' should never give a warning or error message when assembling 1694 compiler output. But programs written by people often cause `as' to 1695 give a warning that a particular assumption was made. All such 1696 warnings are directed to the standard error file. 1697 1698 If you use the `-W' and `--no-warn' options, no warnings are issued. 1699 This only affects the warning messages: it does not change any 1700 particular of how `as' assembles your file. Errors, which stop the 1701 assembly, are still reported. 1702 1703 If you use the `--fatal-warnings' option, `as' considers files that 1704 generate warnings to be in error. 1705 1706 You can switch these options off again by specifying `--warn', which 1707 causes warnings to be output as usual. 1708 1709 1710 File: as.info, Node: Z, Prev: W, Up: Invoking 1711 1712 2.17 Generate Object File in Spite of Errors: `-Z' 1713 ================================================== 1714 1715 After an error message, `as' normally produces no output. If for some 1716 reason you are interested in object file output even after `as' gives 1717 an error message on your program, use the `-Z' option. If there are 1718 any errors, `as' continues anyways, and writes an object file after a 1719 final warning message of the form `N errors, M warnings, generating bad 1720 object file.' 1721 1722 1723 File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1724 1725 3 Syntax 1726 ******** 1727 1728 This chapter describes the machine-independent syntax allowed in a 1729 source file. `as' syntax is similar to what many other assemblers use; 1730 it is inspired by the BSD 4.2 assembler, except that `as' does not 1731 assemble Vax bit-fields. 1732 1733 * Menu: 1734 1735 * Preprocessing:: Preprocessing 1736 * Whitespace:: Whitespace 1737 * Comments:: Comments 1738 * Symbol Intro:: Symbols 1739 * Statements:: Statements 1740 * Constants:: Constants 1741 1742 1743 File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 1744 1745 3.1 Preprocessing 1746 ================= 1747 1748 The `as' internal preprocessor: 1749 * adjusts and removes extra whitespace. It leaves one space or tab 1750 before the keywords on a line, and turns any other whitespace on 1751 the line into a single space. 1752 1753 * removes all comments, replacing them with a single space, or an 1754 appropriate number of newlines. 1755 1756 * converts character constants into the appropriate numeric values. 1757 1758 It does not do macro processing, include file handling, or anything 1759 else you may get from your C compiler's preprocessor. You can do 1760 include file processing with the `.include' directive (*note 1761 `.include': Include.). You can use the GNU C compiler driver to get 1762 other "CPP" style preprocessing by giving the input file a `.S' suffix. 1763 *Note Options Controlling the Kind of Output: (gcc.info)Overall Options. 1764 1765 Excess whitespace, comments, and character constants cannot be used 1766 in the portions of the input text that are not preprocessed. 1767 1768 If the first line of an input file is `#NO_APP' or if you use the 1769 `-f' option, whitespace and comments are not removed from the input 1770 file. Within an input file, you can ask for whitespace and comment 1771 removal in specific portions of the by putting a line that says `#APP' 1772 before the text that may contain whitespace or comments, and putting a 1773 line that says `#NO_APP' after this text. This feature is mainly 1774 intend to support `asm' statements in compilers whose output is 1775 otherwise free of comments and whitespace. 1776 1777 1778 File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 1779 1780 3.2 Whitespace 1781 ============== 1782 1783 "Whitespace" is one or more blanks or tabs, in any order. Whitespace 1784 is used to separate symbols, and to make programs neater for people to 1785 read. Unless within character constants (*note Character Constants: 1786 Characters.), any whitespace means the same as exactly one space. 1787 1788 1789 File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 1790 1791 3.3 Comments 1792 ============ 1793 1794 There are two ways of rendering comments to `as'. In both cases the 1795 comment is equivalent to one space. 1796 1797 Anything from `/*' through the next `*/' is a comment. This means 1798 you may not nest these comments. 1799 1800 /* 1801 The only way to include a newline ('\n') in a comment 1802 is to use this sort of comment. 1803 */ 1804 1805 /* This sort of comment does not nest. */ 1806 1807 Anything from the "line comment" character to the next newline is 1808 considered a comment and is ignored. The line comment character is `;' 1809 on the ARC; `@' on the ARM; `;' for the H8/300 family; `;' for the HPPA; 1810 `#' on the i386 and x86-64; `#' on the i960; `;' for the PDP-11; `;' 1811 for picoJava; `#' for Motorola PowerPC; `#' for IBM S/390; `#' for the 1812 Sunplus SCORE; `!' for the Renesas / SuperH SH; `!' on the SPARC; `#' 1813 on the ip2k; `#' on the m32c; `#' on the m32r; `|' on the 680x0; `#' on 1814 the 68HC11 and 68HC12; `#' on the RX; `;' on the TMS320C6X; `#' on the 1815 Vax; `;' for the Z80; `!' for the Z8000; `#' on the V850; `#' for 1816 Xtensa systems; see *note Machine Dependencies::. 1817 1818 On some machines there are two different line comment characters. 1819 One character only begins a comment if it is the first non-whitespace 1820 character on a line, while the other always begins a comment. 1821 1822 The V850 assembler also supports a double dash as starting a comment 1823 that extends to the end of the line. 1824 1825 `--'; 1826 1827 To be compatible with past assemblers, lines that begin with `#' 1828 have a special interpretation. Following the `#' should be an absolute 1829 expression (*note Expressions::): the logical line number of the _next_ 1830 line. Then a string (*note Strings: Strings.) is allowed: if present 1831 it is a new logical file name. The rest of the line, if any, should be 1832 whitespace. 1833 1834 If the first non-whitespace characters on the line are not numeric, 1835 the line is ignored. (Just like a comment.) 1836 1837 # This is an ordinary comment. 1838 # 42-6 "new_file_name" # New logical file name 1839 # This is logical line # 36. 1840 This feature is deprecated, and may disappear from future versions 1841 of `as'. 1842 1843 1844 File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 1845 1846 3.4 Symbols 1847 =========== 1848 1849 A "symbol" is one or more characters chosen from the set of all letters 1850 (both upper and lower case), digits and the three characters `_.$'. On 1851 most machines, you can also use `$' in symbol names; exceptions are 1852 noted in *note Machine Dependencies::. No symbol may begin with a 1853 digit. Case is significant. There is no length limit: all characters 1854 are significant. Symbols are delimited by characters not in that set, 1855 or by the beginning of a file (since the source program must end with a 1856 newline, the end of a file is not a possible symbol delimiter). *Note 1857 Symbols::. 1858 1859 1860 File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 1861 1862 3.5 Statements 1863 ============== 1864 1865 A "statement" ends at a newline character (`\n') or line separator 1866 character. (The line separator is usually `;', unless this conflicts 1867 with the comment character; see *note Machine Dependencies::.) The 1868 newline or separator character is considered part of the preceding 1869 statement. Newlines and separators within character constants are an 1870 exception: they do not end statements. 1871 1872 It is an error to end any statement with end-of-file: the last 1873 character of any input file should be a newline. 1874 1875 An empty statement is allowed, and may include whitespace. It is 1876 ignored. 1877 1878 A statement begins with zero or more labels, optionally followed by a 1879 key symbol which determines what kind of statement it is. The key 1880 symbol determines the syntax of the rest of the statement. If the 1881 symbol begins with a dot `.' then the statement is an assembler 1882 directive: typically valid for any computer. If the symbol begins with 1883 a letter the statement is an assembly language "instruction": it 1884 assembles into a machine language instruction. Different versions of 1885 `as' for different computers recognize different instructions. In 1886 fact, the same symbol may represent a different instruction in a 1887 different computer's assembly language. 1888 1889 A label is a symbol immediately followed by a colon (`:'). 1890 Whitespace before a label or after a colon is permitted, but you may not 1891 have whitespace between a label's symbol and its colon. *Note Labels::. 1892 1893 For HPPA targets, labels need not be immediately followed by a 1894 colon, but the definition of a label must begin in column zero. This 1895 also implies that only one label may be defined on each line. 1896 1897 label: .directive followed by something 1898 another_label: # This is an empty statement. 1899 instruction operand_1, operand_2, ... 1900 1901 1902 File: as.info, Node: Constants, Prev: Statements, Up: Syntax 1903 1904 3.6 Constants 1905 ============= 1906 1907 A constant is a number, written so that its value is known by 1908 inspection, without knowing any context. Like this: 1909 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 1910 .ascii "Ring the bell\7" # A string constant. 1911 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 1912 .float 0f-314159265358979323846264338327\ 1913 95028841971.693993751E-40 # - pi, a flonum. 1914 1915 * Menu: 1916 1917 * Characters:: Character Constants 1918 * Numbers:: Number Constants 1919 1920 1921 File: as.info, Node: Characters, Next: Numbers, Up: Constants 1922 1923 3.6.1 Character Constants 1924 ------------------------- 1925 1926 There are two kinds of character constants. A "character" stands for 1927 one character in one byte and its value may be used in numeric 1928 expressions. String constants (properly called string _literals_) are 1929 potentially many bytes and their values may not be used in arithmetic 1930 expressions. 1931 1932 * Menu: 1933 1934 * Strings:: Strings 1935 * Chars:: Characters 1936 1937 1938 File: as.info, Node: Strings, Next: Chars, Up: Characters 1939 1940 3.6.1.1 Strings 1941 ............... 1942 1943 A "string" is written between double-quotes. It may contain 1944 double-quotes or null characters. The way to get special characters 1945 into a string is to "escape" these characters: precede them with a 1946 backslash `\' character. For example `\\' represents one backslash: 1947 the first `\' is an escape which tells `as' to interpret the second 1948 character literally as a backslash (which prevents `as' from 1949 recognizing the second `\' as an escape character). The complete list 1950 of escapes follows. 1951 1952 `\b' 1953 Mnemonic for backspace; for ASCII this is octal code 010. 1954 1955 `\f' 1956 Mnemonic for FormFeed; for ASCII this is octal code 014. 1957 1958 `\n' 1959 Mnemonic for newline; for ASCII this is octal code 012. 1960 1961 `\r' 1962 Mnemonic for carriage-Return; for ASCII this is octal code 015. 1963 1964 `\t' 1965 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 1966 1967 `\ DIGIT DIGIT DIGIT' 1968 An octal character code. The numeric code is 3 octal digits. For 1969 compatibility with other Unix systems, 8 and 9 are accepted as 1970 digits: for example, `\008' has the value 010, and `\009' the 1971 value 011. 1972 1973 `\`x' HEX-DIGITS...' 1974 A hex character code. All trailing hex digits are combined. 1975 Either upper or lower case `x' works. 1976 1977 `\\' 1978 Represents one `\' character. 1979 1980 `\"' 1981 Represents one `"' character. Needed in strings to represent this 1982 character, because an unescaped `"' would end the string. 1983 1984 `\ ANYTHING-ELSE' 1985 Any other character when escaped by `\' gives a warning, but 1986 assembles as if the `\' was not present. The idea is that if you 1987 used an escape sequence you clearly didn't want the literal 1988 interpretation of the following character. However `as' has no 1989 other interpretation, so `as' knows it is giving you the wrong 1990 code and warns you of the fact. 1991 1992 Which characters are escapable, and what those escapes represent, 1993 varies widely among assemblers. The current set is what we think the 1994 BSD 4.2 assembler recognizes, and is a subset of what most C compilers 1995 recognize. If you are in doubt, do not use an escape sequence. 1996 1997 1998 File: as.info, Node: Chars, Prev: Strings, Up: Characters 1999 2000 3.6.1.2 Characters 2001 .................. 2002 2003 A single character may be written as a single quote immediately 2004 followed by that character. The same escapes apply to characters as to 2005 strings. So if you want to write the character backslash, you must 2006 write `'\\' where the first `\' escapes the second `\'. As you can 2007 see, the quote is an acute accent, not a grave accent. A newline 2008 immediately following an acute accent is taken as a literal character 2009 and does not count as the end of a statement. The value of a character 2010 constant in a numeric expression is the machine's byte-wide code for 2011 that character. `as' assumes your character code is ASCII: `'A' means 2012 65, `'B' means 66, and so on. 2013 2014 2015 File: as.info, Node: Numbers, Prev: Characters, Up: Constants 2016 2017 3.6.2 Number Constants 2018 ---------------------- 2019 2020 `as' distinguishes three kinds of numbers according to how they are 2021 stored in the target machine. _Integers_ are numbers that would fit 2022 into an `int' in the C language. _Bignums_ are integers, but they are 2023 stored in more than 32 bits. _Flonums_ are floating point numbers, 2024 described below. 2025 2026 * Menu: 2027 2028 * Integers:: Integers 2029 * Bignums:: Bignums 2030 * Flonums:: Flonums 2031 2032 2033 File: as.info, Node: Integers, Next: Bignums, Up: Numbers 2034 2035 3.6.2.1 Integers 2036 ................ 2037 2038 A binary integer is `0b' or `0B' followed by zero or more of the binary 2039 digits `01'. 2040 2041 An octal integer is `0' followed by zero or more of the octal digits 2042 (`01234567'). 2043 2044 A decimal integer starts with a non-zero digit followed by zero or 2045 more digits (`0123456789'). 2046 2047 A hexadecimal integer is `0x' or `0X' followed by one or more 2048 hexadecimal digits chosen from `0123456789abcdefABCDEF'. 2049 2050 Integers have the usual values. To denote a negative integer, use 2051 the prefix operator `-' discussed under expressions (*note Prefix 2052 Operators: Prefix Ops.). 2053 2054 2055 File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 2056 2057 3.6.2.2 Bignums 2058 ............... 2059 2060 A "bignum" has the same syntax and semantics as an integer except that 2061 the number (or its negative) takes more than 32 bits to represent in 2062 binary. The distinction is made because in some places integers are 2063 permitted while bignums are not. 2064 2065 2066 File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2067 2068 3.6.2.3 Flonums 2069 ............... 2070 2071 A "flonum" represents a floating point number. The translation is 2072 indirect: a decimal floating point number from the text is converted by 2073 `as' to a generic binary floating point number of more than sufficient 2074 precision. This generic floating point number is converted to a 2075 particular computer's floating point format (or formats) by a portion 2076 of `as' specialized to that computer. 2077 2078 A flonum is written by writing (in order) 2079 * The digit `0'. (`0' is optional on the HPPA.) 2080 2081 * A letter, to tell `as' the rest of the number is a flonum. `e' is 2082 recommended. Case is not important. 2083 2084 On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the 2085 letter must be one of the letters `DFPRSX' (in upper or lower 2086 case). 2087 2088 On the ARC, the letter must be one of the letters `DFRS' (in upper 2089 or lower case). 2090 2091 On the Intel 960 architecture, the letter must be one of the 2092 letters `DFT' (in upper or lower case). 2093 2094 On the HPPA architecture, the letter must be `E' (upper case only). 2095 2096 * An optional sign: either `+' or `-'. 2097 2098 * An optional "integer part": zero or more decimal digits. 2099 2100 * An optional "fractional part": `.' followed by zero or more 2101 decimal digits. 2102 2103 * An optional exponent, consisting of: 2104 2105 * An `E' or `e'. 2106 2107 * Optional sign: either `+' or `-'. 2108 2109 * One or more decimal digits. 2110 2111 2112 At least one of the integer part or the fractional part must be 2113 present. The floating point number has the usual base-10 value. 2114 2115 `as' does all processing using integers. Flonums are computed 2116 independently of any floating point hardware in the computer running 2117 `as'. 2118 2119 2120 File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2121 2122 4 Sections and Relocation 2123 ************************* 2124 2125 * Menu: 2126 2127 * Secs Background:: Background 2128 * Ld Sections:: Linker Sections 2129 * As Sections:: Assembler Internal Sections 2130 * Sub-Sections:: Sub-Sections 2131 * bss:: bss Section 2132 2133 2134 File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2135 2136 4.1 Background 2137 ============== 2138 2139 Roughly, a section is a range of addresses, with no gaps; all data "in" 2140 those addresses is treated the same for some particular purpose. For 2141 example there may be a "read only" section. 2142 2143 The linker `ld' reads many object files (partial programs) and 2144 combines their contents to form a runnable program. When `as' emits an 2145 object file, the partial program is assumed to start at address 0. 2146 `ld' assigns the final addresses for the partial program, so that 2147 different partial programs do not overlap. This is actually an 2148 oversimplification, but it suffices to explain how `as' uses sections. 2149 2150 `ld' moves blocks of bytes of your program to their run-time 2151 addresses. These blocks slide to their run-time addresses as rigid 2152 units; their length does not change and neither does the order of bytes 2153 within them. Such a rigid unit is called a _section_. Assigning 2154 run-time addresses to sections is called "relocation". It includes the 2155 task of adjusting mentions of object-file addresses so they refer to 2156 the proper run-time addresses. For the H8/300, and for the Renesas / 2157 SuperH SH, `as' pads sections if needed to ensure they end on a word 2158 (sixteen bit) boundary. 2159 2160 An object file written by `as' has at least three sections, any of 2161 which may be empty. These are named "text", "data" and "bss" sections. 2162 2163 When it generates COFF or ELF output, `as' can also generate 2164 whatever other named sections you specify using the `.section' 2165 directive (*note `.section': Section.). If you do not use any 2166 directives that place output in the `.text' or `.data' sections, these 2167 sections still exist, but are empty. 2168 2169 When `as' generates SOM or ELF output for the HPPA, `as' can also 2170 generate whatever other named sections you specify using the `.space' 2171 and `.subspace' directives. See `HP9000 Series 800 Assembly Language 2172 Reference Manual' (HP 92432-90001) for details on the `.space' and 2173 `.subspace' assembler directives. 2174 2175 Additionally, `as' uses different names for the standard text, data, 2176 and bss sections when generating SOM output. Program text is placed 2177 into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'. 2178 2179 Within the object file, the text section starts at address `0', the 2180 data section follows, and the bss section follows the data section. 2181 2182 When generating either SOM or ELF output files on the HPPA, the text 2183 section starts at address `0', the data section at address `0x4000000', 2184 and the bss section follows the data section. 2185 2186 To let `ld' know which data changes when the sections are relocated, 2187 and how to change that data, `as' also writes to the object file 2188 details of the relocation needed. To perform relocation `ld' must 2189 know, each time an address in the object file is mentioned: 2190 * Where in the object file is the beginning of this reference to an 2191 address? 2192 2193 * How long (in bytes) is this reference? 2194 2195 * Which section does the address refer to? What is the numeric 2196 value of 2197 (ADDRESS) - (START-ADDRESS OF SECTION)? 2198 2199 * Is the reference to an address "Program-Counter relative"? 2200 2201 In fact, every address `as' ever uses is expressed as 2202 (SECTION) + (OFFSET INTO SECTION) 2203 Further, most expressions `as' computes have this section-relative 2204 nature. (For some object formats, such as SOM for the HPPA, some 2205 expressions are symbol-relative instead.) 2206 2207 In this manual we use the notation {SECNAME N} to mean "offset N 2208 into section SECNAME." 2209 2210 Apart from text, data and bss sections you need to know about the 2211 "absolute" section. When `ld' mixes partial programs, addresses in the 2212 absolute section remain unchanged. For example, address `{absolute 0}' 2213 is "relocated" to run-time address 0 by `ld'. Although the linker 2214 never arranges two partial programs' data sections with overlapping 2215 addresses after linking, _by definition_ their absolute sections must 2216 overlap. Address `{absolute 239}' in one part of a program is always 2217 the same address when the program is running as address `{absolute 2218 239}' in any other part of the program. 2219 2220 The idea of sections is extended to the "undefined" section. Any 2221 address whose section is unknown at assembly time is by definition 2222 rendered {undefined U}--where U is filled in later. Since numbers are 2223 always defined, the only way to generate an undefined address is to 2224 mention an undefined symbol. A reference to a named common block would 2225 be such a symbol: its value is unknown at assembly time so it has 2226 section _undefined_. 2227 2228 By analogy the word _section_ is used to describe groups of sections 2229 in the linked program. `ld' puts all partial programs' text sections 2230 in contiguous addresses in the linked program. It is customary to 2231 refer to the _text section_ of a program, meaning all the addresses of 2232 all partial programs' text sections. Likewise for data and bss 2233 sections. 2234 2235 Some sections are manipulated by `ld'; others are invented for use 2236 of `as' and have no meaning except during assembly. 2237 2238 2239 File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2240 2241 4.2 Linker Sections 2242 =================== 2243 2244 `ld' deals with just four kinds of sections, summarized below. 2245 2246 *named sections* 2247 *text section* 2248 *data section* 2249 These sections hold your program. `as' and `ld' treat them as 2250 separate but equal sections. Anything you can say of one section 2251 is true of another. When the program is running, however, it is 2252 customary for the text section to be unalterable. The text 2253 section is often shared among processes: it contains instructions, 2254 constants and the like. The data section of a running program is 2255 usually alterable: for example, C variables would be stored in the 2256 data section. 2257 2258 *bss section* 2259 This section contains zeroed bytes when your program begins 2260 running. It is used to hold uninitialized variables or common 2261 storage. The length of each partial program's bss section is 2262 important, but because it starts out containing zeroed bytes there 2263 is no need to store explicit zero bytes in the object file. The 2264 bss section was invented to eliminate those explicit zeros from 2265 object files. 2266 2267 *absolute section* 2268 Address 0 of this section is always "relocated" to runtime address 2269 0. This is useful if you want to refer to an address that `ld' 2270 must not change when relocating. In this sense we speak of 2271 absolute addresses being "unrelocatable": they do not change 2272 during relocation. 2273 2274 *undefined section* 2275 This "section" is a catch-all for address references to objects 2276 not in the preceding sections. 2277 2278 An idealized example of three relocatable sections follows. The 2279 example uses the traditional section names `.text' and `.data'. Memory 2280 addresses are on the horizontal axis. 2281 2282 +-----+----+--+ 2283 partial program # 1: |ttttt|dddd|00| 2284 +-----+----+--+ 2285 2286 text data bss 2287 seg. seg. seg. 2288 2289 +---+---+---+ 2290 partial program # 2: |TTT|DDD|000| 2291 +---+---+---+ 2292 2293 +--+---+-----+--+----+---+-----+~~ 2294 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2295 +--+---+-----+--+----+---+-----+~~ 2296 2297 addresses: 0 ... 2298 2299 2300 File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2301 2302 4.3 Assembler Internal Sections 2303 =============================== 2304 2305 These sections are meant only for the internal use of `as'. They have 2306 no meaning at run-time. You do not really need to know about these 2307 sections for most purposes; but they can be mentioned in `as' warning 2308 messages, so it might be helpful to have an idea of their meanings to 2309 `as'. These sections are used to permit the value of every expression 2310 in your assembly language program to be a section-relative address. 2311 2312 ASSEMBLER-INTERNAL-LOGIC-ERROR! 2313 An internal assembler logic error has been found. This means 2314 there is a bug in the assembler. 2315 2316 expr section 2317 The assembler stores complex expression internally as combinations 2318 of symbols. When it needs to represent an expression as a symbol, 2319 it puts it in the expr section. 2320 2321 2322 File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2323 2324 4.4 Sub-Sections 2325 ================ 2326 2327 Assembled bytes conventionally fall into two sections: text and data. 2328 You may have separate groups of data in named sections that you want to 2329 end up near to each other in the object file, even though they are not 2330 contiguous in the assembler source. `as' allows you to use 2331 "subsections" for this purpose. Within each section, there can be 2332 numbered subsections with values from 0 to 8192. Objects assembled 2333 into the same subsection go into the object file together with other 2334 objects in the same subsection. For example, a compiler might want to 2335 store constants in the text section, but might not want to have them 2336 interspersed with the program being assembled. In this case, the 2337 compiler could issue a `.text 0' before each section of code being 2338 output, and a `.text 1' before each group of constants being output. 2339 2340 Subsections are optional. If you do not use subsections, everything 2341 goes in subsection number zero. 2342 2343 Each subsection is zero-padded up to a multiple of four bytes. 2344 (Subsections may be padded a different amount on different flavors of 2345 `as'.) 2346 2347 Subsections appear in your object file in numeric order, lowest 2348 numbered to highest. (All this to be compatible with other people's 2349 assemblers.) The object file contains no representation of 2350 subsections; `ld' and other programs that manipulate object files see 2351 no trace of them. They just see all your text subsections as a text 2352 section, and all your data subsections as a data section. 2353 2354 To specify which subsection you want subsequent statements assembled 2355 into, use a numeric argument to specify it, in a `.text EXPRESSION' or 2356 a `.data EXPRESSION' statement. When generating COFF output, you can 2357 also use an extra subsection argument with arbitrary named sections: 2358 `.section NAME, EXPRESSION'. When generating ELF output, you can also 2359 use the `.subsection' directive (*note SubSection::) to specify a 2360 subsection: `.subsection EXPRESSION'. EXPRESSION should be an absolute 2361 expression (*note Expressions::). If you just say `.text' then `.text 2362 0' is assumed. Likewise `.data' means `.data 0'. Assembly begins in 2363 `text 0'. For instance: 2364 .text 0 # The default subsection is text 0 anyway. 2365 .ascii "This lives in the first text subsection. *" 2366 .text 1 2367 .ascii "But this lives in the second text subsection." 2368 .data 0 2369 .ascii "This lives in the data section," 2370 .ascii "in the first data subsection." 2371 .text 0 2372 .ascii "This lives in the first text section," 2373 .ascii "immediately following the asterisk (*)." 2374 2375 Each section has a "location counter" incremented by one for every 2376 byte assembled into that section. Because subsections are merely a 2377 convenience restricted to `as' there is no concept of a subsection 2378 location counter. There is no way to directly manipulate a location 2379 counter--but the `.align' directive changes it, and any label 2380 definition captures its current value. The location counter of the 2381 section where statements are being assembled is said to be the "active" 2382 location counter. 2383 2384 2385 File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2386 2387 4.5 bss Section 2388 =============== 2389 2390 The bss section is used for local common variable storage. You may 2391 allocate address space in the bss section, but you may not dictate data 2392 to load into it before your program executes. When your program starts 2393 running, all the contents of the bss section are zeroed bytes. 2394 2395 The `.lcomm' pseudo-op defines a symbol in the bss section; see 2396 *note `.lcomm': Lcomm. 2397 2398 The `.comm' pseudo-op may be used to declare a common symbol, which 2399 is another form of uninitialized symbol; see *note `.comm': Comm. 2400 2401 When assembling for a target which supports multiple sections, such 2402 as ELF or COFF, you may switch into the `.bss' section and define 2403 symbols as usual; see *note `.section': Section. You may only assemble 2404 zero values into the section. Typically the section will only contain 2405 symbol definitions and `.skip' directives (*note `.skip': Skip.). 2406 2407 2408 File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2409 2410 5 Symbols 2411 ********* 2412 2413 Symbols are a central concept: the programmer uses symbols to name 2414 things, the linker uses symbols to link, and the debugger uses symbols 2415 to debug. 2416 2417 _Warning:_ `as' does not place symbols in the object file in the 2418 same order they were declared. This may break some debuggers. 2419 2420 * Menu: 2421 2422 * Labels:: Labels 2423 * Setting Symbols:: Giving Symbols Other Values 2424 * Symbol Names:: Symbol Names 2425 * Dot:: The Special Dot Symbol 2426 * Symbol Attributes:: Symbol Attributes 2427 2428 2429 File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2430 2431 5.1 Labels 2432 ========== 2433 2434 A "label" is written as a symbol immediately followed by a colon `:'. 2435 The symbol then represents the current value of the active location 2436 counter, and is, for example, a suitable instruction operand. You are 2437 warned if you use the same symbol to represent two different locations: 2438 the first definition overrides any other definitions. 2439 2440 On the HPPA, the usual form for a label need not be immediately 2441 followed by a colon, but instead must start in column zero. Only one 2442 label may be defined on a single line. To work around this, the HPPA 2443 version of `as' also provides a special directive `.label' for defining 2444 labels more flexibly. 2445 2446 2447 File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2448 2449 5.2 Giving Symbols Other Values 2450 =============================== 2451 2452 A symbol can be given an arbitrary value by writing a symbol, followed 2453 by an equals sign `=', followed by an expression (*note Expressions::). 2454 This is equivalent to using the `.set' directive. *Note `.set': Set. 2455 In the same way, using a double equals sign `='`=' here represents an 2456 equivalent of the `.eqv' directive. *Note `.eqv': Eqv. 2457 2458 Blackfin does not support symbol assignment with `='. 2459 2460 2461 File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2462 2463 5.3 Symbol Names 2464 ================ 2465 2466 Symbol names begin with a letter or with one of `._'. On most 2467 machines, you can also use `$' in symbol names; exceptions are noted in 2468 *note Machine Dependencies::. That character may be followed by any 2469 string of digits, letters, dollar signs (unless otherwise noted for a 2470 particular target machine), and underscores. 2471 2472 Case of letters is significant: `foo' is a different symbol name than 2473 `Foo'. 2474 2475 Each symbol has exactly one name. Each name in an assembly language 2476 program refers to exactly one symbol. You may use that symbol name any 2477 number of times in a program. 2478 2479 Local Symbol Names 2480 ------------------ 2481 2482 A local symbol is any symbol beginning with certain local label 2483 prefixes. By default, the local label prefix is `.L' for ELF systems or 2484 `L' for traditional a.out systems, but each target may have its own set 2485 of local label prefixes. On the HPPA local symbols begin with `L$'. 2486 2487 Local symbols are defined and used within the assembler, but they are 2488 normally not saved in object files. Thus, they are not visible when 2489 debugging. You may use the `-L' option (*note Include Local Symbols: 2490 `-L': L.) to retain the local symbols in the object files. 2491 2492 Local Labels 2493 ------------ 2494 2495 Local labels help compilers and programmers use names temporarily. 2496 They create symbols which are guaranteed to be unique over the entire 2497 scope of the input source code and which can be referred to by a simple 2498 notation. To define a local label, write a label of the form `N:' 2499 (where N represents any positive integer). To refer to the most recent 2500 previous definition of that label write `Nb', using the same number as 2501 when you defined the label. To refer to the next definition of a local 2502 label, write `Nf'--the `b' stands for "backwards" and the `f' stands 2503 for "forwards". 2504 2505 There is no restriction on how you can use these labels, and you can 2506 reuse them too. So that it is possible to repeatedly define the same 2507 local label (using the same number `N'), although you can only refer to 2508 the most recently defined local label of that number (for a backwards 2509 reference) or the next definition of a specific local label for a 2510 forward reference. It is also worth noting that the first 10 local 2511 labels (`0:'...`9:') are implemented in a slightly more efficient 2512 manner than the others. 2513 2514 Here is an example: 2515 2516 1: branch 1f 2517 2: branch 1b 2518 1: branch 2f 2519 2: branch 1b 2520 2521 Which is the equivalent of: 2522 2523 label_1: branch label_3 2524 label_2: branch label_1 2525 label_3: branch label_4 2526 label_4: branch label_3 2527 2528 Local label names are only a notational device. They are immediately 2529 transformed into more conventional symbol names before the assembler 2530 uses them. The symbol names are stored in the symbol table, appear in 2531 error messages, and are optionally emitted to the object file. The 2532 names are constructed using these parts: 2533 2534 `_local label prefix_' 2535 All local symbols begin with the system-specific local label 2536 prefix. Normally both `as' and `ld' forget symbols that start 2537 with the local label prefix. These labels are used for symbols 2538 you are never intended to see. If you use the `-L' option then 2539 `as' retains these symbols in the object file. If you also 2540 instruct `ld' to retain these symbols, you may use them in 2541 debugging. 2542 2543 `NUMBER' 2544 This is the number that was used in the local label definition. 2545 So if the label is written `55:' then the number is `55'. 2546 2547 `C-B' 2548 This unusual character is included so you do not accidentally 2549 invent a symbol of the same name. The character has ASCII value 2550 of `\002' (control-B). 2551 2552 `_ordinal number_' 2553 This is a serial number to keep the labels distinct. The first 2554 definition of `0:' gets the number `1'. The 15th definition of 2555 `0:' gets the number `15', and so on. Likewise the first 2556 definition of `1:' gets the number `1' and its 15th definition 2557 gets `15' as well. 2558 2559 So for example, the first `1:' may be named `.L1C-B1', and the 44th 2560 `3:' may be named `.L3C-B44'. 2561 2562 Dollar Local Labels 2563 ------------------- 2564 2565 `as' also supports an even more local form of local labels called 2566 dollar labels. These labels go out of scope (i.e., they become 2567 undefined) as soon as a non-local label is defined. Thus they remain 2568 valid for only a small region of the input source code. Normal local 2569 labels, by contrast, remain in scope for the entire file, or until they 2570 are redefined by another occurrence of the same local label. 2571 2572 Dollar labels are defined in exactly the same way as ordinary local 2573 labels, except that they have a dollar sign suffix to their numeric 2574 value, e.g., `55$:'. 2575 2576 They can also be distinguished from ordinary local labels by their 2577 transformed names which use ASCII character `\001' (control-A) as the 2578 magic character to distinguish them from ordinary labels. For example, 2579 the fifth definition of `6$' may be named `.L6C-A5'. 2580 2581 2582 File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2583 2584 5.4 The Special Dot Symbol 2585 ========================== 2586 2587 The special symbol `.' refers to the current address that `as' is 2588 assembling into. Thus, the expression `melvin: .long .' defines 2589 `melvin' to contain its own address. Assigning a value to `.' is 2590 treated the same as a `.org' directive. Thus, the expression `.=.+4' 2591 is the same as saying `.space 4'. 2592 2593 2594 File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2595 2596 5.5 Symbol Attributes 2597 ===================== 2598 2599 Every symbol has, as well as its name, the attributes "Value" and 2600 "Type". Depending on output format, symbols can also have auxiliary 2601 attributes. 2602 2603 If you use a symbol without defining it, `as' assumes zero for all 2604 these attributes, and probably won't warn you. This makes the symbol 2605 an externally defined symbol, which is generally what you would want. 2606 2607 * Menu: 2608 2609 * Symbol Value:: Value 2610 * Symbol Type:: Type 2611 2612 2613 * a.out Symbols:: Symbol Attributes: `a.out' 2614 2615 * COFF Symbols:: Symbol Attributes for COFF 2616 2617 * SOM Symbols:: Symbol Attributes for SOM 2618 2619 2620 File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2621 2622 5.5.1 Value 2623 ----------- 2624 2625 The value of a symbol is (usually) 32 bits. For a symbol which labels a 2626 location in the text, data, bss or absolute sections the value is the 2627 number of addresses from the start of that section to the label. 2628 Naturally for text, data and bss sections the value of a symbol changes 2629 as `ld' changes section base addresses during linking. Absolute 2630 symbols' values do not change during linking: that is why they are 2631 called absolute. 2632 2633 The value of an undefined symbol is treated in a special way. If it 2634 is 0 then the symbol is not defined in this assembler source file, and 2635 `ld' tries to determine its value from other files linked into the same 2636 program. You make this kind of symbol simply by mentioning a symbol 2637 name without defining it. A non-zero value represents a `.comm' common 2638 declaration. The value is how much common storage to reserve, in bytes 2639 (addresses). The symbol refers to the first address of the allocated 2640 storage. 2641 2642 2643 File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2644 2645 5.5.2 Type 2646 ---------- 2647 2648 The type attribute of a symbol contains relocation (section) 2649 information, any flag settings indicating that a symbol is external, and 2650 (optionally), other information for linkers and debuggers. The exact 2651 format depends on the object-code output format in use. 2652 2653 2654 File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2655 2656 5.5.3 Symbol Attributes: `a.out' 2657 -------------------------------- 2658 2659 * Menu: 2660 2661 * Symbol Desc:: Descriptor 2662 * Symbol Other:: Other 2663 2664 2665 File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2666 2667 5.5.3.1 Descriptor 2668 .................. 2669 2670 This is an arbitrary 16-bit value. You may establish a symbol's 2671 descriptor value by using a `.desc' statement (*note `.desc': Desc.). 2672 A descriptor value means nothing to `as'. 2673 2674 2675 File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2676 2677 5.5.3.2 Other 2678 ............. 2679 2680 This is an arbitrary 8-bit value. It means nothing to `as'. 2681 2682 2683 File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2684 2685 5.5.4 Symbol Attributes for COFF 2686 -------------------------------- 2687 2688 The COFF format supports a multitude of auxiliary symbol attributes; 2689 like the primary symbol attributes, they are set between `.def' and 2690 `.endef' directives. 2691 2692 5.5.4.1 Primary Attributes 2693 .......................... 2694 2695 The symbol name is set with `.def'; the value and type, respectively, 2696 with `.val' and `.type'. 2697 2698 5.5.4.2 Auxiliary Attributes 2699 ............................ 2700 2701 The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and 2702 `.weak' can generate auxiliary symbol table information for COFF. 2703 2704 2705 File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2706 2707 5.5.5 Symbol Attributes for SOM 2708 ------------------------------- 2709 2710 The SOM format for the HPPA supports a multitude of symbol attributes 2711 set with the `.EXPORT' and `.IMPORT' directives. 2712 2713 The attributes are described in `HP9000 Series 800 Assembly Language 2714 Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT' 2715 assembler directive documentation. 2716 2717 2718 File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 2719 2720 6 Expressions 2721 ************* 2722 2723 An "expression" specifies an address or numeric value. Whitespace may 2724 precede and/or follow an expression. 2725 2726 The result of an expression must be an absolute number, or else an 2727 offset into a particular section. If an expression is not absolute, 2728 and there is not enough information when `as' sees the expression to 2729 know its section, a second pass over the source program might be 2730 necessary to interpret the expression--but the second pass is currently 2731 not implemented. `as' aborts with an error message in this situation. 2732 2733 * Menu: 2734 2735 * Empty Exprs:: Empty Expressions 2736 * Integer Exprs:: Integer Expressions 2737 2738 2739 File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 2740 2741 6.1 Empty Expressions 2742 ===================== 2743 2744 An empty expression has no value: it is just whitespace or null. 2745 Wherever an absolute expression is required, you may omit the 2746 expression, and `as' assumes a value of (absolute) 0. This is 2747 compatible with other assemblers. 2748 2749 2750 File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 2751 2752 6.2 Integer Expressions 2753 ======================= 2754 2755 An "integer expression" is one or more _arguments_ delimited by 2756 _operators_. 2757 2758 * Menu: 2759 2760 * Arguments:: Arguments 2761 * Operators:: Operators 2762 * Prefix Ops:: Prefix Operators 2763 * Infix Ops:: Infix Operators 2764 2765 2766 File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 2767 2768 6.2.1 Arguments 2769 --------------- 2770 2771 "Arguments" are symbols, numbers or subexpressions. In other contexts 2772 arguments are sometimes called "arithmetic operands". In this manual, 2773 to avoid confusing them with the "instruction operands" of the machine 2774 language, we use the term "argument" to refer to parts of expressions 2775 only, reserving the word "operand" to refer only to machine instruction 2776 operands. 2777 2778 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 2779 text, data, bss, absolute, or undefined. NNN is a signed, 2's 2780 complement 32 bit integer. 2781 2782 Numbers are usually integers. 2783 2784 A number can be a flonum or bignum. In this case, you are warned 2785 that only the low order 32 bits are used, and `as' pretends these 32 2786 bits are an integer. You may write integer-manipulating instructions 2787 that act on exotic constants, compatible with other assemblers. 2788 2789 Subexpressions are a left parenthesis `(' followed by an integer 2790 expression, followed by a right parenthesis `)'; or a prefix operator 2791 followed by an argument. 2792 2793 2794 File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 2795 2796 6.2.2 Operators 2797 --------------- 2798 2799 "Operators" are arithmetic functions, like `+' or `%'. Prefix 2800 operators are followed by an argument. Infix operators appear between 2801 their arguments. Operators may be preceded and/or followed by 2802 whitespace. 2803 2804 2805 File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 2806 2807 6.2.3 Prefix Operator 2808 --------------------- 2809 2810 `as' has the following "prefix operators". They each take one 2811 argument, which must be absolute. 2812 2813 `-' 2814 "Negation". Two's complement negation. 2815 2816 `~' 2817 "Complementation". Bitwise not. 2818 2819 2820 File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 2821 2822 6.2.4 Infix Operators 2823 --------------------- 2824 2825 "Infix operators" take two arguments, one on either side. Operators 2826 have precedence, but operations with equal precedence are performed left 2827 to right. Apart from `+' or `-', both arguments must be absolute, and 2828 the result is absolute. 2829 2830 1. Highest Precedence 2831 2832 `*' 2833 "Multiplication". 2834 2835 `/' 2836 "Division". Truncation is the same as the C operator `/' 2837 2838 `%' 2839 "Remainder". 2840 2841 `<<' 2842 "Shift Left". Same as the C operator `<<'. 2843 2844 `>>' 2845 "Shift Right". Same as the C operator `>>'. 2846 2847 2. Intermediate precedence 2848 2849 `|' 2850 "Bitwise Inclusive Or". 2851 2852 `&' 2853 "Bitwise And". 2854 2855 `^' 2856 "Bitwise Exclusive Or". 2857 2858 `!' 2859 "Bitwise Or Not". 2860 2861 3. Low Precedence 2862 2863 `+' 2864 "Addition". If either argument is absolute, the result has 2865 the section of the other argument. You may not add together 2866 arguments from different sections. 2867 2868 `-' 2869 "Subtraction". If the right argument is absolute, the result 2870 has the section of the left argument. If both arguments are 2871 in the same section, the result is absolute. You may not 2872 subtract arguments from different sections. 2873 2874 `==' 2875 "Is Equal To" 2876 2877 `<>' 2878 `!=' 2879 "Is Not Equal To" 2880 2881 `<' 2882 "Is Less Than" 2883 2884 `>' 2885 "Is Greater Than" 2886 2887 `>=' 2888 "Is Greater Than Or Equal To" 2889 2890 `<=' 2891 "Is Less Than Or Equal To" 2892 2893 The comparison operators can be used as infix operators. A 2894 true results has a value of -1 whereas a false result has a 2895 value of 0. Note, these operators perform signed 2896 comparisons. 2897 2898 4. Lowest Precedence 2899 2900 `&&' 2901 "Logical And". 2902 2903 `||' 2904 "Logical Or". 2905 2906 These two logical operations can be used to combine the 2907 results of sub expressions. Note, unlike the comparison 2908 operators a true result returns a value of 1 but a false 2909 results does still return 0. Also note that the logical or 2910 operator has a slightly lower precedence than logical and. 2911 2912 2913 In short, it's only meaningful to add or subtract the _offsets_ in an 2914 address; you can only have a defined section in one of the two 2915 arguments. 2916 2917 2918 File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 2919 2920 7 Assembler Directives 2921 ********************** 2922 2923 All assembler directives have names that begin with a period (`.'). 2924 The rest of the name is letters, usually in lower case. 2925 2926 This chapter discusses directives that are available regardless of 2927 the target machine configuration for the GNU assembler. Some machine 2928 configurations provide additional directives. *Note Machine 2929 Dependencies::. 2930 2931 * Menu: 2932 2933 * Abort:: `.abort' 2934 2935 * ABORT (COFF):: `.ABORT' 2936 2937 * Align:: `.align ABS-EXPR , ABS-EXPR' 2938 * Altmacro:: `.altmacro' 2939 * Ascii:: `.ascii "STRING"'... 2940 * Asciz:: `.asciz "STRING"'... 2941 * Balign:: `.balign ABS-EXPR , ABS-EXPR' 2942 * Byte:: `.byte EXPRESSIONS' 2943 * CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc. 2944 * Comm:: `.comm SYMBOL , LENGTH ' 2945 * Data:: `.data SUBSECTION' 2946 2947 * Def:: `.def NAME' 2948 2949 * Desc:: `.desc SYMBOL, ABS-EXPRESSION' 2950 2951 * Dim:: `.dim' 2952 2953 * Double:: `.double FLONUMS' 2954 * Eject:: `.eject' 2955 * Else:: `.else' 2956 * Elseif:: `.elseif' 2957 * End:: `.end' 2958 2959 * Endef:: `.endef' 2960 2961 * Endfunc:: `.endfunc' 2962 * Endif:: `.endif' 2963 * Equ:: `.equ SYMBOL, EXPRESSION' 2964 * Equiv:: `.equiv SYMBOL, EXPRESSION' 2965 * Eqv:: `.eqv SYMBOL, EXPRESSION' 2966 * Err:: `.err' 2967 * Error:: `.error STRING' 2968 * Exitm:: `.exitm' 2969 * Extern:: `.extern' 2970 * Fail:: `.fail' 2971 * File:: `.file' 2972 * Fill:: `.fill REPEAT , SIZE , VALUE' 2973 * Float:: `.float FLONUMS' 2974 * Func:: `.func' 2975 * Global:: `.global SYMBOL', `.globl SYMBOL' 2976 2977 * Gnu_attribute:: `.gnu_attribute TAG,VALUE' 2978 * Hidden:: `.hidden NAMES' 2979 2980 * hword:: `.hword EXPRESSIONS' 2981 * Ident:: `.ident' 2982 * If:: `.if ABSOLUTE EXPRESSION' 2983 * Incbin:: `.incbin "FILE"[,SKIP[,COUNT]]' 2984 * Include:: `.include "FILE"' 2985 * Int:: `.int EXPRESSIONS' 2986 2987 * Internal:: `.internal NAMES' 2988 2989 * Irp:: `.irp SYMBOL,VALUES'... 2990 * Irpc:: `.irpc SYMBOL,VALUES'... 2991 * Lcomm:: `.lcomm SYMBOL , LENGTH' 2992 * Lflags:: `.lflags' 2993 2994 * Line:: `.line LINE-NUMBER' 2995 2996 * Linkonce:: `.linkonce [TYPE]' 2997 * List:: `.list' 2998 * Ln:: `.ln LINE-NUMBER' 2999 * Loc:: `.loc FILENO LINENO' 3000 * Loc_mark_labels:: `.loc_mark_labels ENABLE' 3001 3002 * Local:: `.local NAMES' 3003 3004 * Long:: `.long EXPRESSIONS' 3005 3006 * Macro:: `.macro NAME ARGS'... 3007 * MRI:: `.mri VAL' 3008 * Noaltmacro:: `.noaltmacro' 3009 * Nolist:: `.nolist' 3010 * Octa:: `.octa BIGNUMS' 3011 * Org:: `.org NEW-LC, FILL' 3012 * P2align:: `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3013 3014 * PopSection:: `.popsection' 3015 * Previous:: `.previous' 3016 3017 * Print:: `.print STRING' 3018 3019 * Protected:: `.protected NAMES' 3020 3021 * Psize:: `.psize LINES, COLUMNS' 3022 * Purgem:: `.purgem NAME' 3023 3024 * PushSection:: `.pushsection NAME' 3025 3026 * Quad:: `.quad BIGNUMS' 3027 * Reloc:: `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 3028 * Rept:: `.rept COUNT' 3029 * Sbttl:: `.sbttl "SUBHEADING"' 3030 3031 * Scl:: `.scl CLASS' 3032 3033 * Section:: `.section NAME[, FLAGS]' 3034 3035 * Set:: `.set SYMBOL, EXPRESSION' 3036 * Short:: `.short EXPRESSIONS' 3037 * Single:: `.single FLONUMS' 3038 3039 * Size:: `.size [NAME , EXPRESSION]' 3040 3041 * Skip:: `.skip SIZE , FILL' 3042 3043 * Sleb128:: `.sleb128 EXPRESSIONS' 3044 3045 * Space:: `.space SIZE , FILL' 3046 3047 * Stab:: `.stabd, .stabn, .stabs' 3048 3049 * String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"' 3050 * Struct:: `.struct EXPRESSION' 3051 3052 * SubSection:: `.subsection' 3053 * Symver:: `.symver NAME,NAME2@NODENAME' 3054 3055 3056 * Tag:: `.tag STRUCTNAME' 3057 3058 * Text:: `.text SUBSECTION' 3059 * Title:: `.title "HEADING"' 3060 3061 * Type:: `.type <INT | NAME , TYPE DESCRIPTION>' 3062 3063 * Uleb128:: `.uleb128 EXPRESSIONS' 3064 3065 * Val:: `.val ADDR' 3066 3067 3068 * Version:: `.version "STRING"' 3069 * VTableEntry:: `.vtable_entry TABLE, OFFSET' 3070 * VTableInherit:: `.vtable_inherit CHILD, PARENT' 3071 3072 * Warning:: `.warning STRING' 3073 * Weak:: `.weak NAMES' 3074 * Weakref:: `.weakref ALIAS, SYMBOL' 3075 * Word:: `.word EXPRESSIONS' 3076 * Deprecated:: Deprecated Directives 3077 3078 3079 File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3080 3081 7.1 `.abort' 3082 ============ 3083 3084 This directive stops the assembly immediately. It is for compatibility 3085 with other assemblers. The original idea was that the assembly 3086 language source would be piped into the assembler. If the sender of 3087 the source quit, it could use this directive tells `as' to quit also. 3088 One day `.abort' will not be supported. 3089 3090 3091 File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3092 3093 7.2 `.ABORT' (COFF) 3094 =================== 3095 3096 When producing COFF output, `as' accepts this directive as a synonym 3097 for `.abort'. 3098 3099 3100 File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3101 3102 7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3103 ========================================= 3104 3105 Pad the location counter (in the current subsection) to a particular 3106 storage boundary. The first expression (which must be absolute) is the 3107 alignment required, as described below. 3108 3109 The second expression (also absolute) gives the fill value to be 3110 stored in the padding bytes. It (and the comma) may be omitted. If it 3111 is omitted, the padding bytes are normally zero. However, on some 3112 systems, if the section is marked as containing code and the fill value 3113 is omitted, the space is filled with no-op instructions. 3114 3115 The third expression is also absolute, and is also optional. If it 3116 is present, it is the maximum number of bytes that should be skipped by 3117 this alignment directive. If doing the alignment would require 3118 skipping more bytes than the specified maximum, then the alignment is 3119 not done at all. You can omit the fill value (the second argument) 3120 entirely by simply using two commas after the required alignment; this 3121 can be useful if you want the alignment to be filled with no-op 3122 instructions when appropriate. 3123 3124 The way the required alignment is specified varies from system to 3125 system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32, 3126 s390, sparc, tic4x, tic80 and xtensa, the first expression is the 3127 alignment request in bytes. For example `.align 8' advances the 3128 location counter until it is a multiple of 8. If the location counter 3129 is already a multiple of 8, no change is needed. For the tic54x, the 3130 first expression is the alignment request in words. 3131 3132 For other systems, including ppc, i386 using a.out format, arm and 3133 strongarm, it is the number of low-order zero bits the location counter 3134 must have after advancement. For example `.align 3' advances the 3135 location counter until it a multiple of 8. If the location counter is 3136 already a multiple of 8, no change is needed. 3137 3138 This inconsistency is due to the different behaviors of the various 3139 native assemblers for these systems which GAS must emulate. GAS also 3140 provides `.balign' and `.p2align' directives, described later, which 3141 have a consistent behavior across all architectures (but are specific 3142 to GAS). 3143 3144 3145 File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3146 3147 7.4 `.altmacro' 3148 =============== 3149 3150 Enable alternate macro mode, enabling: 3151 3152 `LOCAL NAME [ , ... ]' 3153 One additional directive, `LOCAL', is available. It is used to 3154 generate a string replacement for each of the NAME arguments, and 3155 replace any instances of NAME in each macro expansion. The 3156 replacement string is unique in the assembly, and different for 3157 each separate macro expansion. `LOCAL' allows you to write macros 3158 that define symbols, without fear of conflict between separate 3159 macro expansions. 3160 3161 `String delimiters' 3162 You can write strings delimited in these other ways besides 3163 `"STRING"': 3164 3165 `'STRING'' 3166 You can delimit strings with single-quote characters. 3167 3168 `<STRING>' 3169 You can delimit strings with matching angle brackets. 3170 3171 `single-character string escape' 3172 To include any single character literally in a string (even if the 3173 character would otherwise have some special meaning), you can 3174 prefix the character with `!' (an exclamation mark). For example, 3175 you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 > 3176 5.4!'. 3177 3178 `Expression results as strings' 3179 You can write `%EXPR' to evaluate the expression EXPR and use the 3180 result as a string. 3181 3182 3183 File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3184 3185 7.5 `.ascii "STRING"'... 3186 ======================== 3187 3188 `.ascii' expects zero or more string literals (*note Strings::) 3189 separated by commas. It assembles each string (with no automatic 3190 trailing zero byte) into consecutive addresses. 3191 3192 3193 File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops 3194 3195 7.6 `.asciz "STRING"'... 3196 ======================== 3197 3198 `.asciz' is just like `.ascii', but each string is followed by a zero 3199 byte. The "z" in `.asciz' stands for "zero". 3200 3201 3202 File: as.info, Node: Balign, Next: Byte, Prev: Asciz, Up: Pseudo Ops 3203 3204 7.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 3205 ============================================== 3206 3207 Pad the location counter (in the current subsection) to a particular 3208 storage boundary. The first expression (which must be absolute) is the 3209 alignment request in bytes. For example `.balign 8' advances the 3210 location counter until it is a multiple of 8. If the location counter 3211 is already a multiple of 8, no change is needed. 3212 3213 The second expression (also absolute) gives the fill value to be 3214 stored in the padding bytes. It (and the comma) may be omitted. If it 3215 is omitted, the padding bytes are normally zero. However, on some 3216 systems, if the section is marked as containing code and the fill value 3217 is omitted, the space is filled with no-op instructions. 3218 3219 The third expression is also absolute, and is also optional. If it 3220 is present, it is the maximum number of bytes that should be skipped by 3221 this alignment directive. If doing the alignment would require 3222 skipping more bytes than the specified maximum, then the alignment is 3223 not done at all. You can omit the fill value (the second argument) 3224 entirely by simply using two commas after the required alignment; this 3225 can be useful if you want the alignment to be filled with no-op 3226 instructions when appropriate. 3227 3228 The `.balignw' and `.balignl' directives are variants of the 3229 `.balign' directive. The `.balignw' directive treats the fill pattern 3230 as a two byte word value. The `.balignl' directives treats the fill 3231 pattern as a four byte longword value. For example, `.balignw 3232 4,0x368d' will align to a multiple of 4. If it skips two bytes, they 3233 will be filled in with the value 0x368d (the exact placement of the 3234 bytes depends upon the endianness of the processor). If it skips 1 or 3235 3 bytes, the fill value is undefined. 3236 3237 3238 File: as.info, Node: Byte, Next: CFI directives, Prev: Balign, Up: Pseudo Ops 3239 3240 7.8 `.byte EXPRESSIONS' 3241 ======================= 3242 3243 `.byte' expects zero or more expressions, separated by commas. Each 3244 expression is assembled into the next byte. 3245 3246 3247 File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3248 3249 7.9 `.cfi_sections SECTION_LIST' 3250 ================================ 3251 3252 `.cfi_sections' may be used to specify whether CFI directives should 3253 emit `.eh_frame' section and/or `.debug_frame' section. If 3254 SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is 3255 `.debug_frame', `.debug_frame' is emitted. To emit both use 3256 `.eh_frame, .debug_frame'. The default if this directive is not used 3257 is `.cfi_sections .eh_frame'. 3258 3259 7.10 `.cfi_startproc [simple]' 3260 ============================== 3261 3262 `.cfi_startproc' is used at the beginning of each function that should 3263 have an entry in `.eh_frame'. It initializes some internal data 3264 structures. Don't forget to close the function by `.cfi_endproc'. 3265 3266 Unless `.cfi_startproc' is used along with parameter `simple' it 3267 also emits some architecture dependent initial CFI instructions. 3268 3269 7.11 `.cfi_endproc' 3270 =================== 3271 3272 `.cfi_endproc' is used at the end of a function where it closes its 3273 unwind entry previously opened by `.cfi_startproc', and emits it to 3274 `.eh_frame'. 3275 3276 7.12 `.cfi_personality ENCODING [, EXP]' 3277 ======================================== 3278 3279 `.cfi_personality' defines personality routine and its encoding. 3280 ENCODING must be a constant determining how the personality should be 3281 encoded. If it is 255 (`DW_EH_PE_omit'), second argument is not 3282 present, otherwise second argument should be a constant or a symbol 3283 name. When using indirect encodings, the symbol provided should be the 3284 location where personality can be loaded from, not the personality 3285 routine itself. The default after `.cfi_startproc' is 3286 `.cfi_personality 0xff', no personality routine. 3287 3288 7.13 `.cfi_lsda ENCODING [, EXP]' 3289 ================================= 3290 3291 `.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant 3292 determining how the LSDA should be encoded. If it is 255 3293 (`DW_EH_PE_omit'), second argument is not present, otherwise second 3294 argument should be a constant or a symbol name. The default after 3295 `.cfi_startproc' is `.cfi_lsda 0xff', no LSDA. 3296 3297 7.14 `.cfi_def_cfa REGISTER, OFFSET' 3298 ==================================== 3299 3300 `.cfi_def_cfa' defines a rule for computing CFA as: take address from 3301 REGISTER and add OFFSET to it. 3302 3303 7.15 `.cfi_def_cfa_register REGISTER' 3304 ===================================== 3305 3306 `.cfi_def_cfa_register' modifies a rule for computing CFA. From now on 3307 REGISTER will be used instead of the old one. Offset remains the same. 3308 3309 7.16 `.cfi_def_cfa_offset OFFSET' 3310 ================================= 3311 3312 `.cfi_def_cfa_offset' modifies a rule for computing CFA. Register 3313 remains the same, but OFFSET is new. Note that it is the absolute 3314 offset that will be added to a defined register to compute CFA address. 3315 3316 7.17 `.cfi_adjust_cfa_offset OFFSET' 3317 ==================================== 3318 3319 Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is 3320 added/substracted from the previous offset. 3321 3322 7.18 `.cfi_offset REGISTER, OFFSET' 3323 =================================== 3324 3325 Previous value of REGISTER is saved at offset OFFSET from CFA. 3326 3327 7.19 `.cfi_rel_offset REGISTER, OFFSET' 3328 ======================================= 3329 3330 Previous value of REGISTER is saved at offset OFFSET from the current 3331 CFA register. This is transformed to `.cfi_offset' using the known 3332 displacement of the CFA register from the CFA. This is often easier to 3333 use, because the number will match the code it's annotating. 3334 3335 7.20 `.cfi_register REGISTER1, REGISTER2' 3336 ========================================= 3337 3338 Previous value of REGISTER1 is saved in register REGISTER2. 3339 3340 7.21 `.cfi_restore REGISTER' 3341 ============================ 3342 3343 `.cfi_restore' says that the rule for REGISTER is now the same as it 3344 was at the beginning of the function, after all initial instruction 3345 added by `.cfi_startproc' were executed. 3346 3347 7.22 `.cfi_undefined REGISTER' 3348 ============================== 3349 3350 From now on the previous value of REGISTER can't be restored anymore. 3351 3352 7.23 `.cfi_same_value REGISTER' 3353 =============================== 3354 3355 Current value of REGISTER is the same like in the previous frame, i.e. 3356 no restoration needed. 3357 3358 7.24 `.cfi_remember_state', 3359 =========================== 3360 3361 First save all current rules for all registers by `.cfi_remember_state', 3362 then totally screw them up by subsequent `.cfi_*' directives and when 3363 everything is hopelessly bad, use `.cfi_restore_state' to restore the 3364 previous saved state. 3365 3366 7.25 `.cfi_return_column REGISTER' 3367 ================================== 3368 3369 Change return column REGISTER, i.e. the return address is either 3370 directly in REGISTER or can be accessed by rules for REGISTER. 3371 3372 7.26 `.cfi_signal_frame' 3373 ======================== 3374 3375 Mark current function as signal trampoline. 3376 3377 7.27 `.cfi_window_save' 3378 ======================= 3379 3380 SPARC register window has been saved. 3381 3382 7.28 `.cfi_escape' EXPRESSION[, ...] 3383 ==================================== 3384 3385 Allows the user to add arbitrary bytes to the unwind info. One might 3386 use this to add OS-specific CFI opcodes, or generic CFI opcodes that 3387 GAS does not yet support. 3388 3389 7.29 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' 3390 ====================================================== 3391 3392 The current value of REGISTER is LABEL. The value of LABEL will be 3393 encoded in the output file according to ENCODING; see the description 3394 of `.cfi_personality' for details on this encoding. 3395 3396 The usefulness of equating a register to a fixed label is probably 3397 limited to the return address register. Here, it can be useful to mark 3398 a code segment that has only one return address which is reached by a 3399 direct branch and no copy of the return address exists in memory or 3400 another register. 3401 3402 3403 File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3404 3405 7.30 `.comm SYMBOL , LENGTH ' 3406 ============================= 3407 3408 `.comm' declares a common symbol named SYMBOL. When linking, a common 3409 symbol in one object file may be merged with a defined or common symbol 3410 of the same name in another object file. If `ld' does not see a 3411 definition for the symbol-just one or more common symbols-then it will 3412 allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3413 absolute expression. If `ld' sees multiple common symbols with the 3414 same name, and they do not all have the same size, it will allocate 3415 space using the largest size. 3416 3417 When using ELF or (as a GNU extension) PE, the `.comm' directive 3418 takes an optional third argument. This is the desired alignment of the 3419 symbol, specified for ELF as a byte boundary (for example, an alignment 3420 of 16 means that the least significant 4 bits of the address should be 3421 zero), and for PE as a power of two (for example, an alignment of 5 3422 means aligned to a 32-byte boundary). The alignment must be an 3423 absolute expression, and it must be a power of two. If `ld' allocates 3424 uninitialized memory for the common symbol, it will use the alignment 3425 when placing the symbol. If no alignment is specified, `as' will set 3426 the alignment to the largest power of two less than or equal to the 3427 size of the symbol, up to a maximum of 16 on ELF, or the default 3428 section alignment of 4 on PE(1). 3429 3430 The syntax for `.comm' differs slightly on the HPPA. The syntax is 3431 `SYMBOL .comm, LENGTH'; SYMBOL is optional. 3432 3433 ---------- Footnotes ---------- 3434 3435 (1) This is not the same as the executable image file alignment 3436 controlled by `ld''s `--section-alignment' option; image file sections 3437 in PE are aligned to multiples of 4096, which is far too large an 3438 alignment for ordinary variables. It is rather the default alignment 3439 for (non-debug) sections within object (`*.o') files, which are less 3440 strictly aligned. 3441 3442 3443 File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops 3444 3445 7.31 `.data SUBSECTION' 3446 ======================= 3447 3448 `.data' tells `as' to assemble the following statements onto the end of 3449 the data subsection numbered SUBSECTION (which is an absolute 3450 expression). If SUBSECTION is omitted, it defaults to zero. 3451 3452 3453 File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops 3454 3455 7.32 `.def NAME' 3456 ================ 3457 3458 Begin defining debugging information for a symbol NAME; the definition 3459 extends until the `.endef' directive is encountered. 3460 3461 3462 File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 3463 3464 7.33 `.desc SYMBOL, ABS-EXPRESSION' 3465 =================================== 3466 3467 This directive sets the descriptor of the symbol (*note Symbol 3468 Attributes::) to the low 16 bits of an absolute expression. 3469 3470 The `.desc' directive is not available when `as' is configured for 3471 COFF output; it is only for `a.out' or `b.out' object format. For the 3472 sake of compatibility, `as' accepts it, but produces no output, when 3473 configured for COFF. 3474 3475 3476 File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 3477 3478 7.34 `.dim' 3479 =========== 3480 3481 This directive is generated by compilers to include auxiliary debugging 3482 information in the symbol table. It is only permitted inside 3483 `.def'/`.endef' pairs. 3484 3485 3486 File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 3487 3488 7.35 `.double FLONUMS' 3489 ====================== 3490 3491 `.double' expects zero or more flonums, separated by commas. It 3492 assembles floating point numbers. The exact kind of floating point 3493 numbers emitted depends on how `as' is configured. *Note Machine 3494 Dependencies::. 3495 3496 3497 File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 3498 3499 7.36 `.eject' 3500 ============= 3501 3502 Force a page break at this point, when generating assembly listings. 3503 3504 3505 File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 3506 3507 7.37 `.else' 3508 ============ 3509 3510 `.else' is part of the `as' support for conditional assembly; see *note 3511 `.if': If. It marks the beginning of a section of code to be assembled 3512 if the condition for the preceding `.if' was false. 3513 3514 3515 File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 3516 3517 7.38 `.elseif' 3518 ============== 3519 3520 `.elseif' is part of the `as' support for conditional assembly; see 3521 *note `.if': If. It is shorthand for beginning a new `.if' block that 3522 would otherwise fill the entire `.else' section. 3523 3524 3525 File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 3526 3527 7.39 `.end' 3528 =========== 3529 3530 `.end' marks the end of the assembly file. `as' does not process 3531 anything in the file past the `.end' directive. 3532 3533 3534 File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 3535 3536 7.40 `.endef' 3537 ============= 3538 3539 This directive flags the end of a symbol definition begun with `.def'. 3540 3541 3542 File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 3543 3544 7.41 `.endfunc' 3545 =============== 3546 3547 `.endfunc' marks the end of a function specified with `.func'. 3548 3549 3550 File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 3551 3552 7.42 `.endif' 3553 ============= 3554 3555 `.endif' is part of the `as' support for conditional assembly; it marks 3556 the end of a block of code that is only assembled conditionally. *Note 3557 `.if': If. 3558 3559 3560 File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 3561 3562 7.43 `.equ SYMBOL, EXPRESSION' 3563 ============================== 3564 3565 This directive sets the value of SYMBOL to EXPRESSION. It is 3566 synonymous with `.set'; see *note `.set': Set. 3567 3568 The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'. 3569 3570 The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'. On the 3571 Z80 it is an eror if SYMBOL is already defined, but the symbol is not 3572 protected from later redefinition. Compare *note Equiv::. 3573 3574 3575 File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 3576 3577 7.44 `.equiv SYMBOL, EXPRESSION' 3578 ================================ 3579 3580 The `.equiv' directive is like `.equ' and `.set', except that the 3581 assembler will signal an error if SYMBOL is already defined. Note a 3582 symbol which has been referenced but not actually defined is considered 3583 to be undefined. 3584 3585 Except for the contents of the error message, this is roughly 3586 equivalent to 3587 .ifdef SYM 3588 .err 3589 .endif 3590 .equ SYM,VAL 3591 plus it protects the symbol from later redefinition. 3592 3593 3594 File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 3595 3596 7.45 `.eqv SYMBOL, EXPRESSION' 3597 ============================== 3598 3599 The `.eqv' directive is like `.equiv', but no attempt is made to 3600 evaluate the expression or any part of it immediately. Instead each 3601 time the resulting symbol is used in an expression, a snapshot of its 3602 current value is taken. 3603 3604 3605 File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 3606 3607 7.46 `.err' 3608 =========== 3609 3610 If `as' assembles a `.err' directive, it will print an error message 3611 and, unless the `-Z' option was used, it will not generate an object 3612 file. This can be used to signal an error in conditionally compiled 3613 code. 3614 3615 3616 File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 3617 3618 7.47 `.error "STRING"' 3619 ====================== 3620 3621 Similarly to `.err', this directive emits an error, but you can specify 3622 a string that will be emitted as the error message. If you don't 3623 specify the message, it defaults to `".error directive invoked in 3624 source file"'. *Note Error and Warning Messages: Errors. 3625 3626 .error "This code has not been assembled and tested." 3627 3628 3629 File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 3630 3631 7.48 `.exitm' 3632 ============= 3633 3634 Exit early from the current macro definition. *Note Macro::. 3635 3636 3637 File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 3638 3639 7.49 `.extern' 3640 ============== 3641 3642 `.extern' is accepted in the source program--for compatibility with 3643 other assemblers--but it is ignored. `as' treats all undefined symbols 3644 as external. 3645 3646 3647 File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 3648 3649 7.50 `.fail EXPRESSION' 3650 ======================= 3651 3652 Generates an error or a warning. If the value of the EXPRESSION is 500 3653 or more, `as' will print a warning message. If the value is less than 3654 500, `as' will print an error message. The message will include the 3655 value of EXPRESSION. This can occasionally be useful inside complex 3656 nested macros or conditional assembly. 3657 3658 3659 File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 3660 3661 7.51 `.file' 3662 ============ 3663 3664 There are two different versions of the `.file' directive. Targets 3665 that support DWARF2 line number information use the DWARF2 version of 3666 `.file'. Other targets use the default version. 3667 3668 Default Version 3669 --------------- 3670 3671 This version of the `.file' directive tells `as' that we are about to 3672 start a new logical file. The syntax is: 3673 3674 .file STRING 3675 3676 STRING is the new file name. In general, the filename is recognized 3677 whether or not it is surrounded by quotes `"'; but if you wish to 3678 specify an empty file name, you must give the quotes-`""'. This 3679 statement may go away in future: it is only recognized to be compatible 3680 with old `as' programs. 3681 3682 DWARF2 Version 3683 -------------- 3684 3685 When emitting DWARF2 line number information, `.file' assigns filenames 3686 to the `.debug_line' file name table. The syntax is: 3687 3688 .file FILENO FILENAME 3689 3690 The FILENO operand should be a unique positive integer to use as the 3691 index of the entry in the table. The FILENAME operand is a C string 3692 literal. 3693 3694 The detail of filename indices is exposed to the user because the 3695 filename table is shared with the `.debug_info' section of the DWARF2 3696 debugging information, and thus the user must know the exact indices 3697 that table entries will have. 3698 3699 3700 File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 3701 3702 7.52 `.fill REPEAT , SIZE , VALUE' 3703 ================================== 3704 3705 REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 3706 copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 3707 more, but if it is more than 8, then it is deemed to have the value 8, 3708 compatible with other people's assemblers. The contents of each REPEAT 3709 bytes is taken from an 8-byte number. The highest order 4 bytes are 3710 zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 3711 an integer on the computer `as' is assembling for. Each SIZE bytes in 3712 a repetition is taken from the lowest order SIZE bytes of this number. 3713 Again, this bizarre behavior is compatible with other people's 3714 assemblers. 3715 3716 SIZE and VALUE are optional. If the second comma and VALUE are 3717 absent, VALUE is assumed zero. If the first comma and following tokens 3718 are absent, SIZE is assumed to be 1. 3719 3720 3721 File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 3722 3723 7.53 `.float FLONUMS' 3724 ===================== 3725 3726 This directive assembles zero or more flonums, separated by commas. It 3727 has the same effect as `.single'. The exact kind of floating point 3728 numbers emitted depends on how `as' is configured. *Note Machine 3729 Dependencies::. 3730 3731 3732 File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 3733 3734 7.54 `.func NAME[,LABEL]' 3735 ========================= 3736 3737 `.func' emits debugging information to denote function NAME, and is 3738 ignored unless the file is assembled with debugging enabled. Only 3739 `--gstabs[+]' is currently supported. LABEL is the entry point of the 3740 function and if omitted NAME prepended with the `leading char' is used. 3741 `leading char' is usually `_' or nothing, depending on the target. All 3742 functions are currently defined to have `void' return type. The 3743 function must be terminated with `.endfunc'. 3744 3745 3746 File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 3747 3748 7.55 `.global SYMBOL', `.globl SYMBOL' 3749 ====================================== 3750 3751 `.global' makes the symbol visible to `ld'. If you define SYMBOL in 3752 your partial program, its value is made available to other partial 3753 programs that are linked with it. Otherwise, SYMBOL takes its 3754 attributes from a symbol of the same name from another file linked into 3755 the same program. 3756 3757 Both spellings (`.globl' and `.global') are accepted, for 3758 compatibility with other assemblers. 3759 3760 On the HPPA, `.global' is not always enough to make it accessible to 3761 other partial programs. You may need the HPPA-only `.EXPORT' directive 3762 as well. *Note HPPA Assembler Directives: HPPA Directives. 3763 3764 3765 File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 3766 3767 7.56 `.gnu_attribute TAG,VALUE' 3768 =============================== 3769 3770 Record a GNU object attribute for this file. *Note Object Attributes::. 3771 3772 3773 File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 3774 3775 7.57 `.hidden NAMES' 3776 ==================== 3777 3778 This is one of the ELF visibility directives. The other two are 3779 `.internal' (*note `.internal': Internal.) and `.protected' (*note 3780 `.protected': Protected.). 3781 3782 This directive overrides the named symbols default visibility (which 3783 is set by their binding: local, global or weak). The directive sets 3784 the visibility to `hidden' which means that the symbols are not visible 3785 to other components. Such symbols are always considered to be 3786 `protected' as well. 3787 3788 3789 File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 3790 3791 7.58 `.hword EXPRESSIONS' 3792 ========================= 3793 3794 This expects zero or more EXPRESSIONS, and emits a 16 bit number for 3795 each. 3796 3797 This directive is a synonym for `.short'; depending on the target 3798 architecture, it may also be a synonym for `.word'. 3799 3800 3801 File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 3802 3803 7.59 `.ident' 3804 ============= 3805 3806 This directive is used by some assemblers to place tags in object 3807 files. The behavior of this directive varies depending on the target. 3808 When using the a.out object file format, `as' simply accepts the 3809 directive for source-file compatibility with existing assemblers, but 3810 does not emit anything for it. When using COFF, comments are emitted 3811 to the `.comment' or `.rdata' section, depending on the target. When 3812 using ELF, comments are emitted to the `.comment' section. 3813 3814 3815 File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 3816 3817 7.60 `.if ABSOLUTE EXPRESSION' 3818 ============================== 3819 3820 `.if' marks the beginning of a section of code which is only considered 3821 part of the source program being assembled if the argument (which must 3822 be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 3823 section of code must be marked by `.endif' (*note `.endif': Endif.); 3824 optionally, you may include code for the alternative condition, flagged 3825 by `.else' (*note `.else': Else.). If you have several conditions to 3826 check, `.elseif' may be used to avoid nesting blocks if/else within 3827 each subsequent `.else' block. 3828 3829 The following variants of `.if' are also supported: 3830 `.ifdef SYMBOL' 3831 Assembles the following section of code if the specified SYMBOL 3832 has been defined. Note a symbol which has been referenced but not 3833 yet defined is considered to be undefined. 3834 3835 `.ifb TEXT' 3836 Assembles the following section of code if the operand is blank 3837 (empty). 3838 3839 `.ifc STRING1,STRING2' 3840 Assembles the following section of code if the two strings are the 3841 same. The strings may be optionally quoted with single quotes. 3842 If they are not quoted, the first string stops at the first comma, 3843 and the second string stops at the end of the line. Strings which 3844 contain whitespace should be quoted. The string comparison is 3845 case sensitive. 3846 3847 `.ifeq ABSOLUTE EXPRESSION' 3848 Assembles the following section of code if the argument is zero. 3849 3850 `.ifeqs STRING1,STRING2' 3851 Another form of `.ifc'. The strings must be quoted using double 3852 quotes. 3853 3854 `.ifge ABSOLUTE EXPRESSION' 3855 Assembles the following section of code if the argument is greater 3856 than or equal to zero. 3857 3858 `.ifgt ABSOLUTE EXPRESSION' 3859 Assembles the following section of code if the argument is greater 3860 than zero. 3861 3862 `.ifle ABSOLUTE EXPRESSION' 3863 Assembles the following section of code if the argument is less 3864 than or equal to zero. 3865 3866 `.iflt ABSOLUTE EXPRESSION' 3867 Assembles the following section of code if the argument is less 3868 than zero. 3869 3870 `.ifnb TEXT' 3871 Like `.ifb', but the sense of the test is reversed: this assembles 3872 the following section of code if the operand is non-blank 3873 (non-empty). 3874 3875 `.ifnc STRING1,STRING2.' 3876 Like `.ifc', but the sense of the test is reversed: this assembles 3877 the following section of code if the two strings are not the same. 3878 3879 `.ifndef SYMBOL' 3880 `.ifnotdef SYMBOL' 3881 Assembles the following section of code if the specified SYMBOL 3882 has not been defined. Both spelling variants are equivalent. 3883 Note a symbol which has been referenced but not yet defined is 3884 considered to be undefined. 3885 3886 `.ifne ABSOLUTE EXPRESSION' 3887 Assembles the following section of code if the argument is not 3888 equal to zero (in other words, this is equivalent to `.if'). 3889 3890 `.ifnes STRING1,STRING2' 3891 Like `.ifeqs', but the sense of the test is reversed: this 3892 assembles the following section of code if the two strings are not 3893 the same. 3894 3895 3896 File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 3897 3898 7.61 `.incbin "FILE"[,SKIP[,COUNT]]' 3899 ==================================== 3900 3901 The `incbin' directive can be used with `--allow-incbin'. 3902 3903 The `incbin' directive includes FILE verbatim at the current 3904 location. You can control the search paths used with the `-I' 3905 command-line option (*note Command-Line Options: Invoking.). Quotation 3906 marks are required around FILE. 3907 3908 The SKIP argument skips a number of bytes from the start of the 3909 FILE. The COUNT argument indicates the maximum number of bytes to 3910 read. Note that the data is not aligned in any way, so it is the user's 3911 responsibility to make sure that proper alignment is provided both 3912 before and after the `incbin' directive. 3913 3914 3915 File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 3916 3917 7.62 `.include "FILE"' 3918 ====================== 3919 3920 This directive provides a way to include supporting files at specified 3921 points in your source program. The code from FILE is assembled as if 3922 it followed the point of the `.include'; when the end of the included 3923 file is reached, assembly of the original file continues. You can 3924 control the search paths used with the `-I' command-line option (*note 3925 Command-Line Options: Invoking.). Quotation marks are required around 3926 FILE. 3927 3928 3929 File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 3930 3931 7.63 `.int EXPRESSIONS' 3932 ======================= 3933 3934 Expect zero or more EXPRESSIONS, of any section, separated by commas. 3935 For each expression, emit a number that, at run time, is the value of 3936 that expression. The byte order and bit size of the number depends on 3937 what kind of target the assembly is for. 3938 3939 3940 File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 3941 3942 7.64 `.internal NAMES' 3943 ====================== 3944 3945 This is one of the ELF visibility directives. The other two are 3946 `.hidden' (*note `.hidden': Hidden.) and `.protected' (*note 3947 `.protected': Protected.). 3948 3949 This directive overrides the named symbols default visibility (which 3950 is set by their binding: local, global or weak). The directive sets 3951 the visibility to `internal' which means that the symbols are 3952 considered to be `hidden' (i.e., not visible to other components), and 3953 that some extra, processor specific processing must also be performed 3954 upon the symbols as well. 3955 3956 3957 File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 3958 3959 7.65 `.irp SYMBOL,VALUES'... 3960 ============================ 3961 3962 Evaluate a sequence of statements assigning different values to SYMBOL. 3963 The sequence of statements starts at the `.irp' directive, and is 3964 terminated by an `.endr' directive. For each VALUE, SYMBOL is set to 3965 VALUE, and the sequence of statements is assembled. If no VALUE is 3966 listed, the sequence of statements is assembled once, with SYMBOL set 3967 to the null string. To refer to SYMBOL within the sequence of 3968 statements, use \SYMBOL. 3969 3970 For example, assembling 3971 3972 .irp param,1,2,3 3973 move d\param,sp@- 3974 .endr 3975 3976 is equivalent to assembling 3977 3978 move d1,sp@- 3979 move d2,sp@- 3980 move d3,sp@- 3981 3982 For some caveats with the spelling of SYMBOL, see also *note Macro::. 3983 3984 3985 File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 3986 3987 7.66 `.irpc SYMBOL,VALUES'... 3988 ============================= 3989 3990 Evaluate a sequence of statements assigning different values to SYMBOL. 3991 The sequence of statements starts at the `.irpc' directive, and is 3992 terminated by an `.endr' directive. For each character in VALUE, 3993 SYMBOL is set to the character, and the sequence of statements is 3994 assembled. If no VALUE is listed, the sequence of statements is 3995 assembled once, with SYMBOL set to the null string. To refer to SYMBOL 3996 within the sequence of statements, use \SYMBOL. 3997 3998 For example, assembling 3999 4000 .irpc param,123 4001 move d\param,sp@- 4002 .endr 4003 4004 is equivalent to assembling 4005 4006 move d1,sp@- 4007 move d2,sp@- 4008 move d3,sp@- 4009 4010 For some caveats with the spelling of SYMBOL, see also the discussion 4011 at *Note Macro::. 4012 4013 4014 File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 4015 4016 7.67 `.lcomm SYMBOL , LENGTH' 4017 ============================= 4018 4019 Reserve LENGTH (an absolute expression) bytes for a local common 4020 denoted by SYMBOL. The section and value of SYMBOL are those of the 4021 new local common. The addresses are allocated in the bss section, so 4022 that at run-time the bytes start off zeroed. SYMBOL is not declared 4023 global (*note `.global': Global.), so is normally not visible to `ld'. 4024 4025 Some targets permit a third argument to be used with `.lcomm'. This 4026 argument specifies the desired alignment of the symbol in the bss 4027 section. 4028 4029 The syntax for `.lcomm' differs slightly on the HPPA. The syntax is 4030 `SYMBOL .lcomm, LENGTH'; SYMBOL is optional. 4031 4032 4033 File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 4034 4035 7.68 `.lflags' 4036 ============== 4037 4038 `as' accepts this directive, for compatibility with other assemblers, 4039 but ignores it. 4040 4041 4042 File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 4043 4044 7.69 `.line LINE-NUMBER' 4045 ======================== 4046 4047 Change the logical line number. LINE-NUMBER must be an absolute 4048 expression. The next line has that logical line number. Therefore any 4049 other statements on the current line (after a statement separator 4050 character) are reported as on logical line number LINE-NUMBER - 1. One 4051 day `as' will no longer support this directive: it is recognized only 4052 for compatibility with existing assembler programs. 4053 4054 Even though this is a directive associated with the `a.out' or `b.out' 4055 object-code formats, `as' still recognizes it when producing COFF 4056 output, and treats `.line' as though it were the COFF `.ln' _if_ it is 4057 found outside a `.def'/`.endef' pair. 4058 4059 Inside a `.def', `.line' is, instead, one of the directives used by 4060 compilers to generate auxiliary symbol information for debugging. 4061 4062 4063 File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4064 4065 7.70 `.linkonce [TYPE]' 4066 ======================= 4067 4068 Mark the current section so that the linker only includes a single copy 4069 of it. This may be used to include the same section in several 4070 different object files, but ensure that the linker will only include it 4071 once in the final output file. The `.linkonce' pseudo-op must be used 4072 for each instance of the section. Duplicate sections are detected 4073 based on the section name, so it should be unique. 4074 4075 This directive is only supported by a few object file formats; as of 4076 this writing, the only object file format which supports it is the 4077 Portable Executable format used on Windows NT. 4078 4079 The TYPE argument is optional. If specified, it must be one of the 4080 following strings. For example: 4081 .linkonce same_size 4082 Not all types may be supported on all object file formats. 4083 4084 `discard' 4085 Silently discard duplicate sections. This is the default. 4086 4087 `one_only' 4088 Warn if there are duplicate sections, but still keep only one copy. 4089 4090 `same_size' 4091 Warn if any of the duplicates have different sizes. 4092 4093 `same_contents' 4094 Warn if any of the duplicates do not have exactly the same 4095 contents. 4096 4097 4098 File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4099 4100 7.71 `.list' 4101 ============ 4102 4103 Control (in conjunction with the `.nolist' directive) whether or not 4104 assembly listings are generated. These two directives maintain an 4105 internal counter (which is zero initially). `.list' increments the 4106 counter, and `.nolist' decrements it. Assembly listings are generated 4107 whenever the counter is greater than zero. 4108 4109 By default, listings are disabled. When you enable them (with the 4110 `-a' command line option; *note Command-Line Options: Invoking.), the 4111 initial value of the listing counter is one. 4112 4113 4114 File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4115 4116 7.72 `.ln LINE-NUMBER' 4117 ====================== 4118 4119 `.ln' is a synonym for `.line'. 4120 4121 4122 File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4123 4124 7.73 `.loc FILENO LINENO [COLUMN] [OPTIONS]' 4125 ============================================ 4126 4127 When emitting DWARF2 line number information, the `.loc' directive will 4128 add a row to the `.debug_line' line number matrix corresponding to the 4129 immediately following assembly instruction. The FILENO, LINENO, and 4130 optional COLUMN arguments will be applied to the `.debug_line' state 4131 machine before the row is added. 4132 4133 The OPTIONS are a sequence of the following tokens in any order: 4134 4135 `basic_block' 4136 This option will set the `basic_block' register in the 4137 `.debug_line' state machine to `true'. 4138 4139 `prologue_end' 4140 This option will set the `prologue_end' register in the 4141 `.debug_line' state machine to `true'. 4142 4143 `epilogue_begin' 4144 This option will set the `epilogue_begin' register in the 4145 `.debug_line' state machine to `true'. 4146 4147 `is_stmt VALUE' 4148 This option will set the `is_stmt' register in the `.debug_line' 4149 state machine to `value', which must be either 0 or 1. 4150 4151 `isa VALUE' 4152 This directive will set the `isa' register in the `.debug_line' 4153 state machine to VALUE, which must be an unsigned integer. 4154 4155 `discriminator VALUE' 4156 This directive will set the `discriminator' register in the 4157 `.debug_line' state machine to VALUE, which must be an unsigned 4158 integer. 4159 4160 4161 4162 File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4163 4164 7.74 `.loc_mark_labels ENABLE' 4165 ============================== 4166 4167 When emitting DWARF2 line number information, the `.loc_mark_labels' 4168 directive makes the assembler emit an entry to the `.debug_line' line 4169 number matrix with the `basic_block' register in the state machine set 4170 whenever a code label is seen. The ENABLE argument should be either 1 4171 or 0, to enable or disable this function respectively. 4172 4173 4174 File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4175 4176 7.75 `.local NAMES' 4177 =================== 4178 4179 This directive, which is available for ELF targets, marks each symbol in 4180 the comma-separated list of `names' as a local symbol so that it will 4181 not be externally visible. If the symbols do not already exist, they 4182 will be created. 4183 4184 For targets where the `.lcomm' directive (*note Lcomm::) does not 4185 accept an alignment argument, which is the case for most ELF targets, 4186 the `.local' directive can be used in combination with `.comm' (*note 4187 Comm::) to define aligned local common data. 4188 4189 4190 File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4191 4192 7.76 `.long EXPRESSIONS' 4193 ======================== 4194 4195 `.long' is the same as `.int'. *Note `.int': Int. 4196 4197 4198 File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4199 4200 7.77 `.macro' 4201 ============= 4202 4203 The commands `.macro' and `.endm' allow you to define macros that 4204 generate assembly output. For example, this definition specifies a 4205 macro `sum' that puts a sequence of numbers into memory: 4206 4207 .macro sum from=0, to=5 4208 .long \from 4209 .if \to-\from 4210 sum "(\from+1)",\to 4211 .endif 4212 .endm 4213 4214 With that definition, `SUM 0,5' is equivalent to this assembly input: 4215 4216 .long 0 4217 .long 1 4218 .long 2 4219 .long 3 4220 .long 4 4221 .long 5 4222 4223 `.macro MACNAME' 4224 `.macro MACNAME MACARGS ...' 4225 Begin the definition of a macro called MACNAME. If your macro 4226 definition requires arguments, specify their names after the macro 4227 name, separated by commas or spaces. You can qualify the macro 4228 argument to indicate whether all invocations must specify a 4229 non-blank value (through `:`req''), or whether it takes all of the 4230 remaining arguments (through `:`vararg''). You can supply a 4231 default value for any macro argument by following the name with 4232 `=DEFLT'. You cannot define two macros with the same MACNAME 4233 unless it has been subject to the `.purgem' directive (*note 4234 Purgem::) between the two definitions. For example, these are all 4235 valid `.macro' statements: 4236 4237 `.macro comm' 4238 Begin the definition of a macro called `comm', which takes no 4239 arguments. 4240 4241 `.macro plus1 p, p1' 4242 `.macro plus1 p p1' 4243 Either statement begins the definition of a macro called 4244 `plus1', which takes two arguments; within the macro 4245 definition, write `\p' or `\p1' to evaluate the arguments. 4246 4247 `.macro reserve_str p1=0 p2' 4248 Begin the definition of a macro called `reserve_str', with two 4249 arguments. The first argument has a default value, but not 4250 the second. After the definition is complete, you can call 4251 the macro either as `reserve_str A,B' (with `\p1' evaluating 4252 to A and `\p2' evaluating to B), or as `reserve_str ,B' (with 4253 `\p1' evaluating as the default, in this case `0', and `\p2' 4254 evaluating to B). 4255 4256 `.macro m p1:req, p2=0, p3:vararg' 4257 Begin the definition of a macro called `m', with at least 4258 three arguments. The first argument must always have a value 4259 specified, but not the second, which instead has a default 4260 value. The third formal will get assigned all remaining 4261 arguments specified at invocation time. 4262 4263 When you call a macro, you can specify the argument values 4264 either by position, or by keyword. For example, `sum 9,17' 4265 is equivalent to `sum to=17, from=9'. 4266 4267 4268 Note that since each of the MACARGS can be an identifier exactly 4269 as any other one permitted by the target architecture, there may be 4270 occasional problems if the target hand-crafts special meanings to 4271 certain characters when they occur in a special position. For 4272 example, if the colon (`:') is generally permitted to be part of a 4273 symbol name, but the architecture specific code special-cases it 4274 when occurring as the final character of a symbol (to denote a 4275 label), then the macro parameter replacement code will have no way 4276 of knowing that and consider the whole construct (including the 4277 colon) an identifier, and check only this identifier for being the 4278 subject to parameter substitution. So for example this macro 4279 definition: 4280 4281 .macro label l 4282 \l: 4283 .endm 4284 4285 might not work as expected. Invoking `label foo' might not create 4286 a label called `foo' but instead just insert the text `\l:' into 4287 the assembler source, probably generating an error about an 4288 unrecognised identifier. 4289 4290 Similarly problems might occur with the period character (`.') 4291 which is often allowed inside opcode names (and hence identifier 4292 names). So for example constructing a macro to build an opcode 4293 from a base name and a length specifier like this: 4294 4295 .macro opcode base length 4296 \base.\length 4297 .endm 4298 4299 and invoking it as `opcode store l' will not create a `store.l' 4300 instruction but instead generate some kind of error as the 4301 assembler tries to interpret the text `\base.\length'. 4302 4303 There are several possible ways around this problem: 4304 4305 `Insert white space' 4306 If it is possible to use white space characters then this is 4307 the simplest solution. eg: 4308 4309 .macro label l 4310 \l : 4311 .endm 4312 4313 `Use `\()'' 4314 The string `\()' can be used to separate the end of a macro 4315 argument from the following text. eg: 4316 4317 .macro opcode base length 4318 \base\().\length 4319 .endm 4320 4321 `Use the alternate macro syntax mode' 4322 In the alternative macro syntax mode the ampersand character 4323 (`&') can be used as a separator. eg: 4324 4325 .altmacro 4326 .macro label l 4327 l&: 4328 .endm 4329 4330 Note: this problem of correctly identifying string parameters to 4331 pseudo ops also applies to the identifiers used in `.irp' (*note 4332 Irp::) and `.irpc' (*note Irpc::) as well. 4333 4334 `.endm' 4335 Mark the end of a macro definition. 4336 4337 `.exitm' 4338 Exit early from the current macro definition. 4339 4340 `\@' 4341 `as' maintains a counter of how many macros it has executed in 4342 this pseudo-variable; you can copy that number to your output with 4343 `\@', but _only within a macro definition_. 4344 4345 `LOCAL NAME [ , ... ]' 4346 _Warning: `LOCAL' is only available if you select "alternate macro 4347 syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro': 4348 Altmacro. 4349 4350 4351 File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4352 4353 7.78 `.mri VAL' 4354 =============== 4355 4356 If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero, 4357 this tells `as' to exit MRI mode. This change affects code assembled 4358 until the next `.mri' directive, or until the end of the file. *Note 4359 MRI mode: M. 4360 4361 4362 File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4363 4364 7.79 `.noaltmacro' 4365 ================== 4366 4367 Disable alternate macro mode. *Note Altmacro::. 4368 4369 4370 File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops 4371 4372 7.80 `.nolist' 4373 ============== 4374 4375 Control (in conjunction with the `.list' directive) whether or not 4376 assembly listings are generated. These two directives maintain an 4377 internal counter (which is zero initially). `.list' increments the 4378 counter, and `.nolist' decrements it. Assembly listings are generated 4379 whenever the counter is greater than zero. 4380 4381 4382 File: as.info, Node: Octa, Next: Org, Prev: Nolist, Up: Pseudo Ops 4383 4384 7.81 `.octa BIGNUMS' 4385 ==================== 4386 4387 This directive expects zero or more bignums, separated by commas. For 4388 each bignum, it emits a 16-byte integer. 4389 4390 The term "octa" comes from contexts in which a "word" is two bytes; 4391 hence _octa_-word for 16 bytes. 4392 4393 4394 File: as.info, Node: Org, Next: P2align, Prev: Octa, Up: Pseudo Ops 4395 4396 7.82 `.org NEW-LC , FILL' 4397 ========================= 4398 4399 Advance the location counter of the current section to NEW-LC. NEW-LC 4400 is either an absolute expression or an expression with the same section 4401 as the current subsection. That is, you can't use `.org' to cross 4402 sections: if NEW-LC has the wrong section, the `.org' directive is 4403 ignored. To be compatible with former assemblers, if the section of 4404 NEW-LC is absolute, `as' issues a warning, then pretends the section of 4405 NEW-LC is the same as the current subsection. 4406 4407 `.org' may only increase the location counter, or leave it 4408 unchanged; you cannot use `.org' to move the location counter backwards. 4409 4410 Because `as' tries to assemble programs in one pass, NEW-LC may not 4411 be undefined. If you really detest this restriction we eagerly await a 4412 chance to share your improved assembler. 4413 4414 Beware that the origin is relative to the start of the section, not 4415 to the start of the subsection. This is compatible with other people's 4416 assemblers. 4417 4418 When the location counter (of the current subsection) is advanced, 4419 the intervening bytes are filled with FILL which should be an absolute 4420 expression. If the comma and FILL are omitted, FILL defaults to zero. 4421 4422 4423 File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 4424 4425 7.83 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 4426 ================================================ 4427 4428 Pad the location counter (in the current subsection) to a particular 4429 storage boundary. The first expression (which must be absolute) is the 4430 number of low-order zero bits the location counter must have after 4431 advancement. For example `.p2align 3' advances the location counter 4432 until it a multiple of 8. If the location counter is already a 4433 multiple of 8, no change is needed. 4434 4435 The second expression (also absolute) gives the fill value to be 4436 stored in the padding bytes. It (and the comma) may be omitted. If it 4437 is omitted, the padding bytes are normally zero. However, on some 4438 systems, if the section is marked as containing code and the fill value 4439 is omitted, the space is filled with no-op instructions. 4440 4441 The third expression is also absolute, and is also optional. If it 4442 is present, it is the maximum number of bytes that should be skipped by 4443 this alignment directive. If doing the alignment would require 4444 skipping more bytes than the specified maximum, then the alignment is 4445 not done at all. You can omit the fill value (the second argument) 4446 entirely by simply using two commas after the required alignment; this 4447 can be useful if you want the alignment to be filled with no-op 4448 instructions when appropriate. 4449 4450 The `.p2alignw' and `.p2alignl' directives are variants of the 4451 `.p2align' directive. The `.p2alignw' directive treats the fill 4452 pattern as a two byte word value. The `.p2alignl' directives treats the 4453 fill pattern as a four byte longword value. For example, `.p2alignw 4454 2,0x368d' will align to a multiple of 4. If it skips two bytes, they 4455 will be filled in with the value 0x368d (the exact placement of the 4456 bytes depends upon the endianness of the processor). If it skips 1 or 4457 3 bytes, the fill value is undefined. 4458 4459 4460 File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 4461 4462 7.84 `.popsection' 4463 ================== 4464 4465 This is one of the ELF section stack manipulation directives. The 4466 others are `.section' (*note Section::), `.subsection' (*note 4467 SubSection::), `.pushsection' (*note PushSection::), and `.previous' 4468 (*note Previous::). 4469 4470 This directive replaces the current section (and subsection) with 4471 the top section (and subsection) on the section stack. This section is 4472 popped off the stack. 4473 4474 4475 File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 4476 4477 7.85 `.previous' 4478 ================ 4479 4480 This is one of the ELF section stack manipulation directives. The 4481 others are `.section' (*note Section::), `.subsection' (*note 4482 SubSection::), `.pushsection' (*note PushSection::), and `.popsection' 4483 (*note PopSection::). 4484 4485 This directive swaps the current section (and subsection) with most 4486 recently referenced section/subsection pair prior to this one. Multiple 4487 `.previous' directives in a row will flip between two sections (and 4488 their subsections). For example: 4489 4490 .section A 4491 .subsection 1 4492 .word 0x1234 4493 .subsection 2 4494 .word 0x5678 4495 .previous 4496 .word 0x9abc 4497 4498 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 4499 subsection 2 of section A. Whilst: 4500 4501 .section A 4502 .subsection 1 4503 # Now in section A subsection 1 4504 .word 0x1234 4505 .section B 4506 .subsection 0 4507 # Now in section B subsection 0 4508 .word 0x5678 4509 .subsection 1 4510 # Now in section B subsection 1 4511 .word 0x9abc 4512 .previous 4513 # Now in section B subsection 0 4514 .word 0xdef0 4515 4516 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 4517 0 of section B and 0x9abc into subsection 1 of section B. 4518 4519 In terms of the section stack, this directive swaps the current 4520 section with the top section on the section stack. 4521 4522 4523 File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 4524 4525 7.86 `.print STRING' 4526 ==================== 4527 4528 `as' will print STRING on the standard output during assembly. You 4529 must put STRING in double quotes. 4530 4531 4532 File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 4533 4534 7.87 `.protected NAMES' 4535 ======================= 4536 4537 This is one of the ELF visibility directives. The other two are 4538 `.hidden' (*note Hidden::) and `.internal' (*note Internal::). 4539 4540 This directive overrides the named symbols default visibility (which 4541 is set by their binding: local, global or weak). The directive sets 4542 the visibility to `protected' which means that any references to the 4543 symbols from within the components that defines them must be resolved 4544 to the definition in that component, even if a definition in another 4545 component would normally preempt this. 4546 4547 4548 File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 4549 4550 7.88 `.psize LINES , COLUMNS' 4551 ============================= 4552 4553 Use this directive to declare the number of lines--and, optionally, the 4554 number of columns--to use for each page, when generating listings. 4555 4556 If you do not use `.psize', listings use a default line-count of 60. 4557 You may omit the comma and COLUMNS specification; the default width is 4558 200 columns. 4559 4560 `as' generates formfeeds whenever the specified number of lines is 4561 exceeded (or whenever you explicitly request one, using `.eject'). 4562 4563 If you specify LINES as `0', no formfeeds are generated save those 4564 explicitly specified with `.eject'. 4565 4566 4567 File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 4568 4569 7.89 `.purgem NAME' 4570 =================== 4571 4572 Undefine the macro NAME, so that later uses of the string will not be 4573 expanded. *Note Macro::. 4574 4575 4576 File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 4577 4578 7.90 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' 4579 ======================================================================== 4580 4581 This is one of the ELF section stack manipulation directives. The 4582 others are `.section' (*note Section::), `.subsection' (*note 4583 SubSection::), `.popsection' (*note PopSection::), and `.previous' 4584 (*note Previous::). 4585 4586 This directive pushes the current section (and subsection) onto the 4587 top of the section stack, and then replaces the current section and 4588 subsection with `name' and `subsection'. The optional `flags', `type' 4589 and `arguments' are treated the same as in the `.section' (*note 4590 Section::) directive. 4591 4592 4593 File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 4594 4595 7.91 `.quad BIGNUMS' 4596 ==================== 4597 4598 `.quad' expects zero or more bignums, separated by commas. For each 4599 bignum, it emits an 8-byte integer. If the bignum won't fit in 8 4600 bytes, it prints a warning message; and just takes the lowest order 8 4601 bytes of the bignum. 4602 4603 The term "quad" comes from contexts in which a "word" is two bytes; 4604 hence _quad_-word for 8 bytes. 4605 4606 4607 File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 4608 4609 7.92 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 4610 ============================================== 4611 4612 Generate a relocation at OFFSET of type RELOC_NAME with value 4613 EXPRESSION. If OFFSET is a number, the relocation is generated in the 4614 current section. If OFFSET is an expression that resolves to a symbol 4615 plus offset, the relocation is generated in the given symbol's section. 4616 EXPRESSION, if present, must resolve to a symbol plus addend or to an 4617 absolute value, but note that not all targets support an addend. e.g. 4618 ELF REL targets such as i386 store an addend in the section contents 4619 rather than in the relocation. This low level interface does not 4620 support addends stored in the section. 4621 4622 4623 File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 4624 4625 7.93 `.rept COUNT' 4626 ================== 4627 4628 Repeat the sequence of lines between the `.rept' directive and the next 4629 `.endr' directive COUNT times. 4630 4631 For example, assembling 4632 4633 .rept 3 4634 .long 0 4635 .endr 4636 4637 is equivalent to assembling 4638 4639 .long 0 4640 .long 0 4641 .long 0 4642 4643 4644 File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 4645 4646 7.94 `.sbttl "SUBHEADING"' 4647 ========================== 4648 4649 Use SUBHEADING as the title (third line, immediately after the title 4650 line) when generating assembly listings. 4651 4652 This directive affects subsequent pages, as well as the current page 4653 if it appears within ten lines of the top of a page. 4654 4655 4656 File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 4657 4658 7.95 `.scl CLASS' 4659 ================= 4660 4661 Set the storage-class value for a symbol. This directive may only be 4662 used inside a `.def'/`.endef' pair. Storage class may flag whether a 4663 symbol is static or external, or it may record further symbolic 4664 debugging information. 4665 4666 4667 File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 4668 4669 7.96 `.section NAME' 4670 ==================== 4671 4672 Use the `.section' directive to assemble the following code into a 4673 section named NAME. 4674 4675 This directive is only supported for targets that actually support 4676 arbitrarily named sections; on `a.out' targets, for example, it is not 4677 accepted, even with a standard `a.out' section name. 4678 4679 COFF Version 4680 ------------ 4681 4682 For COFF targets, the `.section' directive is used in one of the 4683 following ways: 4684 4685 .section NAME[, "FLAGS"] 4686 .section NAME[, SUBSECTION] 4687 4688 If the optional argument is quoted, it is taken as flags to use for 4689 the section. Each flag is a single character. The following flags are 4690 recognized: 4691 `b' 4692 bss section (uninitialized data) 4693 4694 `n' 4695 section is not loaded 4696 4697 `w' 4698 writable section 4699 4700 `d' 4701 data section 4702 4703 `r' 4704 read-only section 4705 4706 `x' 4707 executable section 4708 4709 `s' 4710 shared section (meaningful for PE targets) 4711 4712 `a' 4713 ignored. (For compatibility with the ELF version) 4714 4715 `y' 4716 section is not readable (meaningful for PE targets) 4717 4718 `0-9' 4719 single-digit power-of-two section alignment (GNU extension) 4720 4721 If no flags are specified, the default flags depend upon the section 4722 name. If the section name is not recognized, the default will be for 4723 the section to be loaded and writable. Note the `n' and `w' flags 4724 remove attributes from the section, rather than adding them, so if they 4725 are used on their own it will be as if no flags had been specified at 4726 all. 4727 4728 If the optional argument to the `.section' directive is not quoted, 4729 it is taken as a subsection number (*note Sub-Sections::). 4730 4731 ELF Version 4732 ----------- 4733 4734 This is one of the ELF section stack manipulation directives. The 4735 others are `.subsection' (*note SubSection::), `.pushsection' (*note 4736 PushSection::), `.popsection' (*note PopSection::), and `.previous' 4737 (*note Previous::). 4738 4739 For ELF targets, the `.section' directive is used like this: 4740 4741 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 4742 4743 The optional FLAGS argument is a quoted string which may contain any 4744 combination of the following characters: 4745 `a' 4746 section is allocatable 4747 4748 `e' 4749 section is excluded from executable and shared library. 4750 4751 `w' 4752 section is writable 4753 4754 `x' 4755 section is executable 4756 4757 `M' 4758 section is mergeable 4759 4760 `S' 4761 section contains zero terminated strings 4762 4763 `G' 4764 section is a member of a section group 4765 4766 `T' 4767 section is used for thread-local-storage 4768 4769 `?' 4770 section is a member of the previously-current section's group, if 4771 any 4772 4773 The optional TYPE argument may contain one of the following 4774 constants: 4775 `@progbits' 4776 section contains data 4777 4778 `@nobits' 4779 section does not contain data (i.e., section only occupies space) 4780 4781 `@note' 4782 section contains data which is used by things other than the 4783 program 4784 4785 `@init_array' 4786 section contains an array of pointers to init functions 4787 4788 `@fini_array' 4789 section contains an array of pointers to finish functions 4790 4791 `@preinit_array' 4792 section contains an array of pointers to pre-init functions 4793 4794 Many targets only support the first three section types. 4795 4796 Note on targets where the `@' character is the start of a comment (eg 4797 ARM) then another character is used instead. For example the ARM port 4798 uses the `%' character. 4799 4800 If FLAGS contains the `M' symbol then the TYPE argument must be 4801 specified as well as an extra argument--ENTSIZE--like this: 4802 4803 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 4804 4805 Sections with the `M' flag but not `S' flag must contain fixed size 4806 constants, each ENTSIZE octets long. Sections with both `M' and `S' 4807 must contain zero terminated strings where each character is ENTSIZE 4808 bytes long. The linker may remove duplicates within sections with the 4809 same name, same entity size and same flags. ENTSIZE must be an 4810 absolute expression. For sections with both `M' and `S', a string 4811 which is a suffix of a larger string is considered a duplicate. Thus 4812 `"def"' will be merged with `"abcdef"'; A reference to the first 4813 `"def"' will be changed to a reference to `"abcdef"+3'. 4814 4815 If FLAGS contains the `G' symbol then the TYPE argument must be 4816 present along with an additional field like this: 4817 4818 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 4819 4820 The GROUPNAME field specifies the name of the section group to which 4821 this particular section belongs. The optional linkage field can 4822 contain: 4823 `comdat' 4824 indicates that only one copy of this section should be retained 4825 4826 `.gnu.linkonce' 4827 an alias for comdat 4828 4829 Note: if both the M and G flags are present then the fields for the 4830 Merge flag should come first, like this: 4831 4832 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 4833 4834 If FLAGS contains the `?' symbol then it may not also contain the 4835 `G' symbol and the GROUPNAME or LINKAGE fields should not be present. 4836 Instead, `?' says to consider the section that's current before this 4837 directive. If that section used `G', then the new section will use `G' 4838 with those same GROUPNAME and LINKAGE fields implicitly. If not, then 4839 the `?' symbol has no effect. 4840 4841 If no flags are specified, the default flags depend upon the section 4842 name. If the section name is not recognized, the default will be for 4843 the section to have none of the above flags: it will not be allocated 4844 in memory, nor writable, nor executable. The section will contain data. 4845 4846 For ELF targets, the assembler supports another type of `.section' 4847 directive for compatibility with the Solaris assembler: 4848 4849 .section "NAME"[, FLAGS...] 4850 4851 Note that the section name is quoted. There may be a sequence of 4852 comma separated flags: 4853 `#alloc' 4854 section is allocatable 4855 4856 `#write' 4857 section is writable 4858 4859 `#execinstr' 4860 section is executable 4861 4862 `#exclude' 4863 section is excluded from executable and shared library. 4864 4865 `#tls' 4866 section is used for thread local storage 4867 4868 This directive replaces the current section and subsection. See the 4869 contents of the gas testsuite directory `gas/testsuite/gas/elf' for 4870 some examples of how this directive and the other section stack 4871 directives work. 4872 4873 4874 File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 4875 4876 7.97 `.set SYMBOL, EXPRESSION' 4877 ============================== 4878 4879 Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and 4880 type to conform to EXPRESSION. If SYMBOL was flagged as external, it 4881 remains flagged (*note Symbol Attributes::). 4882 4883 You may `.set' a symbol many times in the same assembly. 4884 4885 If you `.set' a global symbol, the value stored in the object file 4886 is the last value stored into it. 4887 4888 On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION' 4889 instead. 4890 4891 4892 File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 4893 4894 7.98 `.short EXPRESSIONS' 4895 ========================= 4896 4897 `.short' is normally the same as `.word'. *Note `.word': Word. 4898 4899 In some configurations, however, `.short' and `.word' generate 4900 numbers of different lengths. *Note Machine Dependencies::. 4901 4902 4903 File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 4904 4905 7.99 `.single FLONUMS' 4906 ====================== 4907 4908 This directive assembles zero or more flonums, separated by commas. It 4909 has the same effect as `.float'. The exact kind of floating point 4910 numbers emitted depends on how `as' is configured. *Note Machine 4911 Dependencies::. 4912 4913 4914 File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 4915 4916 7.100 `.size' 4917 ============= 4918 4919 This directive is used to set the size associated with a symbol. 4920 4921 COFF Version 4922 ------------ 4923 4924 For COFF targets, the `.size' directive is only permitted inside 4925 `.def'/`.endef' pairs. It is used like this: 4926 4927 .size EXPRESSION 4928 4929 ELF Version 4930 ----------- 4931 4932 For ELF targets, the `.size' directive is used like this: 4933 4934 .size NAME , EXPRESSION 4935 4936 This directive sets the size associated with a symbol NAME. The 4937 size in bytes is computed from EXPRESSION which can make use of label 4938 arithmetic. This directive is typically used to set the size of 4939 function symbols. 4940 4941 4942 File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 4943 4944 7.101 `.skip SIZE , FILL' 4945 ========================= 4946 4947 This directive emits SIZE bytes, each of value FILL. Both SIZE and 4948 FILL are absolute expressions. If the comma and FILL are omitted, FILL 4949 is assumed to be zero. This is the same as `.space'. 4950 4951 4952 File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 4953 4954 7.102 `.sleb128 EXPRESSIONS' 4955 ============================ 4956 4957 SLEB128 stands for "signed little endian base 128." This is a compact, 4958 variable length representation of numbers used by the DWARF symbolic 4959 debugging format. *Note `.uleb128': Uleb128. 4960 4961 4962 File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 4963 4964 7.103 `.space SIZE , FILL' 4965 ========================== 4966 4967 This directive emits SIZE bytes, each of value FILL. Both SIZE and 4968 FILL are absolute expressions. If the comma and FILL are omitted, FILL 4969 is assumed to be zero. This is the same as `.skip'. 4970 4971 _Warning:_ `.space' has a completely different meaning for HPPA 4972 targets; use `.block' as a substitute. See `HP9000 Series 800 4973 Assembly Language Reference Manual' (HP 92432-90001) for the 4974 meaning of the `.space' directive. *Note HPPA Assembler 4975 Directives: HPPA Directives, for a summary. 4976 4977 4978 File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 4979 4980 7.104 `.stabd, .stabn, .stabs' 4981 ============================== 4982 4983 There are three directives that begin `.stab'. All emit symbols (*note 4984 Symbols::), for use by symbolic debuggers. The symbols are not entered 4985 in the `as' hash table: they cannot be referenced elsewhere in the 4986 source file. Up to five fields are required: 4987 4988 STRING 4989 This is the symbol's name. It may contain any character except 4990 `\000', so is more general than ordinary symbol names. Some 4991 debuggers used to code arbitrarily complex structures into symbol 4992 names using this field. 4993 4994 TYPE 4995 An absolute expression. The symbol's type is set to the low 8 4996 bits of this expression. Any bit pattern is permitted, but `ld' 4997 and debuggers choke on silly bit patterns. 4998 4999 OTHER 5000 An absolute expression. The symbol's "other" attribute is set to 5001 the low 8 bits of this expression. 5002 5003 DESC 5004 An absolute expression. The symbol's descriptor is set to the low 5005 16 bits of this expression. 5006 5007 VALUE 5008 An absolute expression which becomes the symbol's value. 5009 5010 If a warning is detected while reading a `.stabd', `.stabn', or 5011 `.stabs' statement, the symbol has probably already been created; you 5012 get a half-formed symbol in your object file. This is compatible with 5013 earlier assemblers! 5014 5015 `.stabd TYPE , OTHER , DESC' 5016 The "name" of the symbol generated is not even an empty string. 5017 It is a null pointer, for compatibility. Older assemblers used a 5018 null pointer so they didn't waste space in object files with empty 5019 strings. 5020 5021 The symbol's value is set to the location counter, relocatably. 5022 When your program is linked, the value of this symbol is the 5023 address of the location counter when the `.stabd' was assembled. 5024 5025 `.stabn TYPE , OTHER , DESC , VALUE' 5026 The name of the symbol is set to the empty string `""'. 5027 5028 `.stabs STRING , TYPE , OTHER , DESC , VALUE' 5029 All five fields are specified. 5030 5031 5032 File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 5033 5034 7.105 `.string' "STR", `.string8' "STR", `.string16' 5035 ==================================================== 5036 5037 "STR", `.string32' "STR", `.string64' "STR" 5038 5039 Copy the characters in STR to the object file. You may specify more 5040 than one string to copy, separated by commas. Unless otherwise 5041 specified for a particular machine, the assembler marks the end of each 5042 string with a 0 byte. You can use any of the escape sequences 5043 described in *note Strings: Strings. 5044 5045 The variants `string16', `string32' and `string64' differ from the 5046 `string' pseudo opcode in that each 8-bit character from STR is copied 5047 and expanded to 16, 32 or 64 bits respectively. The expanded characters 5048 are stored in target endianness byte order. 5049 5050 Example: 5051 .string32 "BYE" 5052 expands to: 5053 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5054 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5055 5056 5057 File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5058 5059 7.106 `.struct EXPRESSION' 5060 ========================== 5061 5062 Switch to the absolute section, and set the section offset to 5063 EXPRESSION, which must be an absolute expression. You might use this 5064 as follows: 5065 .struct 0 5066 field1: 5067 .struct field1 + 4 5068 field2: 5069 .struct field2 + 4 5070 field3: 5071 This would define the symbol `field1' to have the value 0, the symbol 5072 `field2' to have the value 4, and the symbol `field3' to have the value 5073 8. Assembly would be left in the absolute section, and you would need 5074 to use a `.section' directive of some sort to change to some other 5075 section before further assembly. 5076 5077 5078 File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5079 5080 7.107 `.subsection NAME' 5081 ======================== 5082 5083 This is one of the ELF section stack manipulation directives. The 5084 others are `.section' (*note Section::), `.pushsection' (*note 5085 PushSection::), `.popsection' (*note PopSection::), and `.previous' 5086 (*note Previous::). 5087 5088 This directive replaces the current subsection with `name'. The 5089 current section is not changed. The replaced subsection is put onto 5090 the section stack in place of the then current top of stack subsection. 5091 5092 5093 File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5094 5095 7.108 `.symver' 5096 =============== 5097 5098 Use the `.symver' directive to bind symbols to specific version nodes 5099 within a source file. This is only supported on ELF platforms, and is 5100 typically used when assembling files to be linked into a shared library. 5101 There are cases where it may make sense to use this in objects to be 5102 bound into an application itself so as to override a versioned symbol 5103 from a shared library. 5104 5105 For ELF targets, the `.symver' directive can be used like this: 5106 .symver NAME, NAME2@NODENAME 5107 If the symbol NAME is defined within the file being assembled, the 5108 `.symver' directive effectively creates a symbol alias with the name 5109 NAME2@NODENAME, and in fact the main reason that we just don't try and 5110 create a regular alias is that the @ character isn't permitted in 5111 symbol names. The NAME2 part of the name is the actual name of the 5112 symbol by which it will be externally referenced. The name NAME itself 5113 is merely a name of convenience that is used so that it is possible to 5114 have definitions for multiple versions of a function within a single 5115 source file, and so that the compiler can unambiguously know which 5116 version of a function is being mentioned. The NODENAME portion of the 5117 alias should be the name of a node specified in the version script 5118 supplied to the linker when building a shared library. If you are 5119 attempting to override a versioned symbol from a shared library, then 5120 NODENAME should correspond to the nodename of the symbol you are trying 5121 to override. 5122 5123 If the symbol NAME is not defined within the file being assembled, 5124 all references to NAME will be changed to NAME2@NODENAME. If no 5125 reference to NAME is made, NAME2@NODENAME will be removed from the 5126 symbol table. 5127 5128 Another usage of the `.symver' directive is: 5129 .symver NAME, NAME2@@NODENAME 5130 In this case, the symbol NAME must exist and be defined within the 5131 file being assembled. It is similar to NAME2@NODENAME. The difference 5132 is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5133 the linker. 5134 5135 The third usage of the `.symver' directive is: 5136 .symver NAME, NAME2@@@NODENAME 5137 When NAME is not defined within the file being assembled, it is 5138 treated as NAME2@NODENAME. When NAME is defined within the file being 5139 assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5140 5141 5142 File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5143 5144 7.109 `.tag STRUCTNAME' 5145 ======================= 5146 5147 This directive is generated by compilers to include auxiliary debugging 5148 information in the symbol table. It is only permitted inside 5149 `.def'/`.endef' pairs. Tags are used to link structure definitions in 5150 the symbol table with instances of those structures. 5151 5152 5153 File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5154 5155 7.110 `.text SUBSECTION' 5156 ======================== 5157 5158 Tells `as' to assemble the following statements onto the end of the 5159 text subsection numbered SUBSECTION, which is an absolute expression. 5160 If SUBSECTION is omitted, subsection number zero is used. 5161 5162 5163 File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops 5164 5165 7.111 `.title "HEADING"' 5166 ======================== 5167 5168 Use HEADING as the title (second line, immediately after the source 5169 file name and pagenumber) when generating assembly listings. 5170 5171 This directive affects subsequent pages, as well as the current page 5172 if it appears within ten lines of the top of a page. 5173 5174 5175 File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops 5176 5177 7.112 `.type' 5178 ============= 5179 5180 This directive is used to set the type of a symbol. 5181 5182 COFF Version 5183 ------------ 5184 5185 For COFF targets, this directive is permitted only within 5186 `.def'/`.endef' pairs. It is used like this: 5187 5188 .type INT 5189 5190 This records the integer INT as the type attribute of a symbol table 5191 entry. 5192 5193 ELF Version 5194 ----------- 5195 5196 For ELF targets, the `.type' directive is used like this: 5197 5198 .type NAME , TYPE DESCRIPTION 5199 5200 This sets the type of symbol NAME to be either a function symbol or 5201 an object symbol. There are five different syntaxes supported for the 5202 TYPE DESCRIPTION field, in order to provide compatibility with various 5203 other assemblers. 5204 5205 Because some of the characters used in these syntaxes (such as `@' 5206 and `#') are comment characters for some architectures, some of the 5207 syntaxes below do not work on all architectures. The first variant 5208 will be accepted by the GNU assembler on all architectures so that 5209 variant should be used for maximum portability, if you do not need to 5210 assemble your code with other assemblers. 5211 5212 The syntaxes supported are: 5213 5214 .type <name> STT_<TYPE_IN_UPPER_CASE> 5215 .type <name>,#<type> 5216 .type <name>,@<type> 5217 .type <name>,%<type> 5218 .type <name>,"<type>" 5219 5220 The types supported are: 5221 5222 `STT_FUNC' 5223 `function' 5224 Mark the symbol as being a function name. 5225 5226 `STT_GNU_IFUNC' 5227 `gnu_indirect_function' 5228 Mark the symbol as an indirect function when evaluated during reloc 5229 processing. (This is only supported on Linux targeted assemblers). 5230 5231 `STT_OBJECT' 5232 `object' 5233 Mark the symbol as being a data object. 5234 5235 `STT_TLS' 5236 `tls_object' 5237 Mark the symbol as being a thead-local data object. 5238 5239 `STT_COMMON' 5240 `common' 5241 Mark the symbol as being a common data object. 5242 5243 `STT_NOTYPE' 5244 `notype' 5245 Does not mark the symbol in any way. It is supported just for 5246 completeness. 5247 5248 `gnu_unique_object' 5249 Marks the symbol as being a globally unique data object. The 5250 dynamic linker will make sure that in the entire process there is 5251 just one symbol with this name and type in use. (This is only 5252 supported on Linux targeted assemblers). 5253 5254 5255 Note: Some targets support extra types in addition to those listed 5256 above. 5257 5258 5259 File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 5260 5261 7.113 `.uleb128 EXPRESSIONS' 5262 ============================ 5263 5264 ULEB128 stands for "unsigned little endian base 128." This is a 5265 compact, variable length representation of numbers used by the DWARF 5266 symbolic debugging format. *Note `.sleb128': Sleb128. 5267 5268 5269 File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 5270 5271 7.114 `.val ADDR' 5272 ================= 5273 5274 This directive, permitted only within `.def'/`.endef' pairs, records 5275 the address ADDR as the value attribute of a symbol table entry. 5276 5277 5278 File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 5279 5280 7.115 `.version "STRING"' 5281 ========================= 5282 5283 This directive creates a `.note' section and places into it an ELF 5284 formatted note of type NT_VERSION. The note's name is set to `string'. 5285 5286 5287 File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 5288 5289 7.116 `.vtable_entry TABLE, OFFSET' 5290 =================================== 5291 5292 This directive finds or creates a symbol `table' and creates a 5293 `VTABLE_ENTRY' relocation for it with an addend of `offset'. 5294 5295 5296 File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 5297 5298 7.117 `.vtable_inherit CHILD, PARENT' 5299 ===================================== 5300 5301 This directive finds the symbol `child' and finds or creates the symbol 5302 `parent' and then creates a `VTABLE_INHERIT' relocation for the parent 5303 whose addend is the value of the child symbol. As a special case the 5304 parent name of `0' is treated as referring to the `*ABS*' section. 5305 5306 5307 File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 5308 5309 7.118 `.warning "STRING"' 5310 ========================= 5311 5312 Similar to the directive `.error' (*note `.error "STRING"': Error.), 5313 but just emits a warning. 5314 5315 5316 File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 5317 5318 7.119 `.weak NAMES' 5319 =================== 5320 5321 This directive sets the weak attribute on the comma separated list of 5322 symbol `names'. If the symbols do not already exist, they will be 5323 created. 5324 5325 On COFF targets other than PE, weak symbols are a GNU extension. 5326 This directive sets the weak attribute on the comma separated list of 5327 symbol `names'. If the symbols do not already exist, they will be 5328 created. 5329 5330 On the PE target, weak symbols are supported natively as weak 5331 aliases. When a weak symbol is created that is not an alias, GAS 5332 creates an alternate symbol to hold the default value. 5333 5334 5335 File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 5336 5337 7.120 `.weakref ALIAS, TARGET' 5338 ============================== 5339 5340 This directive creates an alias to the target symbol that enables the 5341 symbol to be referenced with weak-symbol semantics, but without 5342 actually making it weak. If direct references or definitions of the 5343 symbol are present, then the symbol will not be weak, but if all 5344 references to it are through weak references, the symbol will be marked 5345 as weak in the symbol table. 5346 5347 The effect is equivalent to moving all references to the alias to a 5348 separate assembly source file, renaming the alias to the symbol in it, 5349 declaring the symbol as weak there, and running a reloadable link to 5350 merge the object files resulting from the assembly of the new source 5351 file and the old source file that had the references to the alias 5352 removed. 5353 5354 The alias itself never makes to the symbol table, and is entirely 5355 handled within the assembler. 5356 5357 5358 File: as.info, Node: Word, Next: Deprecated, Prev: Weakref, Up: Pseudo Ops 5359 5360 7.121 `.word EXPRESSIONS' 5361 ========================= 5362 5363 This directive expects zero or more EXPRESSIONS, of any section, 5364 separated by commas. 5365 5366 The size of the number emitted, and its byte order, depend on what 5367 target computer the assembly is for. 5368 5369 _Warning: Special Treatment to support Compilers_ 5370 5371 Machines with a 32-bit address space, but that do less than 32-bit 5372 addressing, require the following special treatment. If the machine of 5373 interest to you does 32-bit addressing (or doesn't require it; *note 5374 Machine Dependencies::), you can ignore this issue. 5375 5376 In order to assemble compiler output into something that works, `as' 5377 occasionally does strange things to `.word' directives. Directives of 5378 the form `.word sym1-sym2' are often emitted by compilers as part of 5379 jump tables. Therefore, when `as' assembles a directive of the form 5380 `.word sym1-sym2', and the difference between `sym1' and `sym2' does 5381 not fit in 16 bits, `as' creates a "secondary jump table", immediately 5382 before the next label. This secondary jump table is preceded by a 5383 short-jump to the first byte after the secondary table. This 5384 short-jump prevents the flow of control from accidentally falling into 5385 the new table. Inside the table is a long-jump to `sym2'. The 5386 original `.word' contains `sym1' minus the address of the long-jump to 5387 `sym2'. 5388 5389 If there were several occurrences of `.word sym1-sym2' before the 5390 secondary jump table, all of them are adjusted. If there was a `.word 5391 sym3-sym4', that also did not fit in sixteen bits, a long-jump to 5392 `sym4' is included in the secondary jump table, and the `.word' 5393 directives are adjusted to contain `sym3' minus the address of the 5394 long-jump to `sym4'; and so on, for as many entries in the original 5395 jump table as necessary. 5396 5397 5398 File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops 5399 5400 7.122 Deprecated Directives 5401 =========================== 5402 5403 One day these directives won't work. They are included for 5404 compatibility with older assemblers. 5405 .abort 5406 5407 .line 5408 5409 5410 File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 5411 5412 8 Object Attributes 5413 ******************* 5414 5415 `as' assembles source files written for a specific architecture into 5416 object files for that architecture. But not all object files are alike. 5417 Many architectures support incompatible variations. For instance, 5418 floating point arguments might be passed in floating point registers if 5419 the object file requires hardware floating point support--or floating 5420 point arguments might be passed in integer registers if the object file 5421 supports processors with no hardware floating point unit. Or, if two 5422 objects are built for different generations of the same architecture, 5423 the combination may require the newer generation at run-time. 5424 5425 This information is useful during and after linking. At link time, 5426 `ld' can warn about incompatible object files. After link time, tools 5427 like `gdb' can use it to process the linked file correctly. 5428 5429 Compatibility information is recorded as a series of object 5430 attributes. Each attribute has a "vendor", "tag", and "value". The 5431 vendor is a string, and indicates who sets the meaning of the tag. The 5432 tag is an integer, and indicates what property the attribute describes. 5433 The value may be a string or an integer, and indicates how the property 5434 affects this object. Missing attributes are the same as attributes 5435 with a zero value or empty string value. 5436 5437 Object attributes were developed as part of the ABI for the ARM 5438 Architecture. The file format is documented in `ELF for the ARM 5439 Architecture'. 5440 5441 * Menu: 5442 5443 * GNU Object Attributes:: GNU Object Attributes 5444 * Defining New Object Attributes:: Defining New Object Attributes 5445 5446 5447 File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 5448 5449 8.1 GNU Object Attributes 5450 ========================= 5451 5452 The `.gnu_attribute' directive records an object attribute with vendor 5453 `gnu'. 5454 5455 Except for `Tag_compatibility', which has both an integer and a 5456 string for its value, GNU attributes have a string value if the tag 5457 number is odd and an integer value if the tag number is even. The 5458 second bit (`TAG & 2' is set for architecture-independent attributes 5459 and clear for architecture-dependent ones. 5460 5461 8.1.1 Common GNU attributes 5462 --------------------------- 5463 5464 These attributes are valid on all architectures. 5465 5466 Tag_compatibility (32) 5467 The compatibility attribute takes an integer flag value and a 5468 vendor name. If the flag value is 0, the file is compatible with 5469 other toolchains. If it is 1, then the file is only compatible 5470 with the named toolchain. If it is greater than 1, the file can 5471 only be processed by other toolchains under some private 5472 arrangement indicated by the flag value and the vendor name. 5473 5474 8.1.2 MIPS Attributes 5475 --------------------- 5476 5477 Tag_GNU_MIPS_ABI_FP (4) 5478 The floating-point ABI used by this object file. The value will 5479 be: 5480 5481 * 0 for files not affected by the floating-point ABI. 5482 5483 * 1 for files using the hardware floating-point with a standard 5484 double-precision FPU. 5485 5486 * 2 for files using the hardware floating-point ABI with a 5487 single-precision FPU. 5488 5489 * 3 for files using the software floating-point ABI. 5490 5491 * 4 for files using the hardware floating-point ABI with 64-bit 5492 wide double-precision floating-point registers and 32-bit 5493 wide general purpose registers. 5494 5495 8.1.3 PowerPC Attributes 5496 ------------------------ 5497 5498 Tag_GNU_Power_ABI_FP (4) 5499 The floating-point ABI used by this object file. The value will 5500 be: 5501 5502 * 0 for files not affected by the floating-point ABI. 5503 5504 * 1 for files using double-precision hardware floating-point 5505 ABI. 5506 5507 * 2 for files using the software floating-point ABI. 5508 5509 * 3 for files using single-precision hardware floating-point 5510 ABI. 5511 5512 Tag_GNU_Power_ABI_Vector (8) 5513 The vector ABI used by this object file. The value will be: 5514 5515 * 0 for files not affected by the vector ABI. 5516 5517 * 1 for files using general purpose registers to pass vectors. 5518 5519 * 2 for files using AltiVec registers to pass vectors. 5520 5521 * 3 for files using SPE registers to pass vectors. 5522 5523 5524 File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 5525 5526 8.2 Defining New Object Attributes 5527 ================================== 5528 5529 If you want to define a new GNU object attribute, here are the places 5530 you will need to modify. New attributes should be discussed on the 5531 `binutils' mailing list. 5532 5533 * This manual, which is the official register of attributes. 5534 5535 * The header for your architecture `include/elf', to define the tag. 5536 5537 * The `bfd' support file for your architecture, to merge the 5538 attribute and issue any appropriate link warnings. 5539 5540 * Test cases in `ld/testsuite' for merging and link warnings. 5541 5542 * `binutils/readelf.c' to display your attribute. 5543 5544 * GCC, if you want the compiler to mark the attribute automatically. 5545 5546 5547 File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 5548 5549 9 Machine Dependent Features 5550 **************************** 5551 5552 The machine instruction sets are (almost by definition) different on 5553 each machine where `as' runs. Floating point representations vary as 5554 well, and `as' often supports a few additional directives or 5555 command-line options for compatibility with other assemblers on a 5556 particular platform. Finally, some versions of `as' support special 5557 pseudo-instructions for branch optimization. 5558 5559 This chapter discusses most of these differences, though it does not 5560 include details on any machine's instruction set. For details on that 5561 subject, see the hardware manufacturer's manual. 5562 5563 * Menu: 5564 5565 5566 * Alpha-Dependent:: Alpha Dependent Features 5567 5568 * ARC-Dependent:: ARC Dependent Features 5569 5570 * ARM-Dependent:: ARM Dependent Features 5571 5572 * AVR-Dependent:: AVR Dependent Features 5573 5574 * Blackfin-Dependent:: Blackfin Dependent Features 5575 5576 * CR16-Dependent:: CR16 Dependent Features 5577 5578 * CRIS-Dependent:: CRIS Dependent Features 5579 5580 * D10V-Dependent:: D10V Dependent Features 5581 5582 * D30V-Dependent:: D30V Dependent Features 5583 5584 * H8/300-Dependent:: Renesas H8/300 Dependent Features 5585 5586 * HPPA-Dependent:: HPPA Dependent Features 5587 5588 * ESA/390-Dependent:: IBM ESA/390 Dependent Features 5589 5590 * i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 5591 5592 * i860-Dependent:: Intel 80860 Dependent Features 5593 5594 * i960-Dependent:: Intel 80960 Dependent Features 5595 5596 * IA-64-Dependent:: Intel IA-64 Dependent Features 5597 5598 * IP2K-Dependent:: IP2K Dependent Features 5599 5600 * LM32-Dependent:: LM32 Dependent Features 5601 5602 * M32C-Dependent:: M32C Dependent Features 5603 5604 * M32R-Dependent:: M32R Dependent Features 5605 5606 * M68K-Dependent:: M680x0 Dependent Features 5607 5608 * M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 5609 5610 * MicroBlaze-Dependent:: MICROBLAZE Dependent Features 5611 5612 * MIPS-Dependent:: MIPS Dependent Features 5613 5614 * MMIX-Dependent:: MMIX Dependent Features 5615 5616 * MSP430-Dependent:: MSP430 Dependent Features 5617 5618 * SH-Dependent:: Renesas / SuperH SH Dependent Features 5619 * SH64-Dependent:: SuperH SH64 Dependent Features 5620 5621 * PDP-11-Dependent:: PDP-11 Dependent Features 5622 5623 * PJ-Dependent:: picoJava Dependent Features 5624 5625 * PPC-Dependent:: PowerPC Dependent Features 5626 5627 * RX-Dependent:: RX Dependent Features 5628 5629 * S/390-Dependent:: IBM S/390 Dependent Features 5630 5631 * SCORE-Dependent:: SCORE Dependent Features 5632 5633 * Sparc-Dependent:: SPARC Dependent Features 5634 5635 * TIC54X-Dependent:: TI TMS320C54x Dependent Features 5636 5637 * TIC6X-Dependent :: TI TMS320C6x Dependent Features 5638 5639 * V850-Dependent:: V850 Dependent Features 5640 5641 * Xtensa-Dependent:: Xtensa Dependent Features 5642 5643 * Z80-Dependent:: Z80 Dependent Features 5644 5645 * Z8000-Dependent:: Z8000 Dependent Features 5646 5647 * Vax-Dependent:: VAX Dependent Features 5648 5649 5650 File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Up: Machine Dependencies 5651 5652 9.1 Alpha Dependent Features 5653 ============================ 5654 5655 * Menu: 5656 5657 * Alpha Notes:: Notes 5658 * Alpha Options:: Options 5659 * Alpha Syntax:: Syntax 5660 * Alpha Floating Point:: Floating Point 5661 * Alpha Directives:: Alpha Machine Directives 5662 * Alpha Opcodes:: Opcodes 5663 5664 5665 File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 5666 5667 9.1.1 Notes 5668 ----------- 5669 5670 The documentation here is primarily for the ELF object format. `as' 5671 also supports the ECOFF and EVAX formats, but features specific to 5672 these formats are not yet documented. 5673 5674 5675 File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 5676 5677 9.1.2 Options 5678 ------------- 5679 5680 `-mCPU' 5681 This option specifies the target processor. If an attempt is made 5682 to assemble an instruction which will not execute on the target 5683 processor, the assembler may either expand the instruction as a 5684 macro or issue an error message. This option is equivalent to the 5685 `.arch' directive. 5686 5687 The following processor names are recognized: `21064', `21064a', 5688 `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a', 5689 `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6', 5690 `ev67', `ev68'. The special name `all' may be used to allow the 5691 assembler to accept instructions valid for any Alpha processor. 5692 5693 In order to support existing practice in OSF/1 with respect to 5694 `.arch', and existing practice within `MILO' (the Linux ARC 5695 bootloader), the numbered processor names (e.g. 21064) enable the 5696 processor-specific PALcode instructions, while the 5697 "electro-vlasic" names (e.g. `ev4') do not. 5698 5699 `-mdebug' 5700 `-no-mdebug' 5701 Enables or disables the generation of `.mdebug' encapsulation for 5702 stabs directives and procedure descriptors. The default is to 5703 automatically enable `.mdebug' when the first stabs directive is 5704 seen. 5705 5706 `-relax' 5707 This option forces all relocations to be put into the object file, 5708 instead of saving space and resolving some relocations at assembly 5709 time. Note that this option does not propagate all symbol 5710 arithmetic into the object file, because not all symbol arithmetic 5711 can be represented. However, the option can still be useful in 5712 specific applications. 5713 5714 `-replace' 5715 `-noreplace' 5716 Enables or disables the optimization of procedure calls, both at 5717 assemblage and at link time. These options are only available for 5718 VMS targets and `-replace' is the default. See section 1.4.1 of 5719 the OpenVMS Linker Utility Manual. 5720 5721 `-g' 5722 This option is used when the compiler generates debug information. 5723 When `gcc' is using `mips-tfile' to generate debug information for 5724 ECOFF, local labels must be passed through to the object file. 5725 Otherwise this option has no effect. 5726 5727 `-GSIZE' 5728 A local common symbol larger than SIZE is placed in `.bss', while 5729 smaller symbols are placed in `.sbss'. 5730 5731 `-F' 5732 `-32addr' 5733 These options are ignored for backward compatibility. 5734 5735 5736 File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 5737 5738 9.1.3 Syntax 5739 ------------ 5740 5741 The assembler syntax closely follow the Alpha Reference Manual; 5742 assembler directives and general syntax closely follow the OSF/1 and 5743 OpenVMS syntax, with a few differences for ELF. 5744 5745 * Menu: 5746 5747 * Alpha-Chars:: Special Characters 5748 * Alpha-Regs:: Register Names 5749 * Alpha-Relocs:: Relocations 5750 5751 5752 File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 5753 5754 9.1.3.1 Special Characters 5755 .......................... 5756 5757 `#' is the line comment character. 5758 5759 `;' can be used instead of a newline to separate statements. 5760 5761 5762 File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 5763 5764 9.1.3.2 Register Names 5765 ...................... 5766 5767 The 32 integer registers are referred to as `$N' or `$rN'. In 5768 addition, registers 15, 28, 29, and 30 may be referred to by the 5769 symbols `$fp', `$at', `$gp', and `$sp' respectively. 5770 5771 The 32 floating-point registers are referred to as `$fN'. 5772 5773 5774 File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 5775 5776 9.1.3.3 Relocations 5777 ................... 5778 5779 Some of these relocations are available for ECOFF, but mostly only for 5780 ELF. They are modeled after the relocation format introduced in 5781 Digital Unix 4.0, but there are additions. 5782 5783 The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the 5784 relocation. In some cases NUMBER is used to relate specific 5785 instructions. 5786 5787 The relocation is placed at the end of the instruction like so: 5788 5789 ldah $0,a($29) !gprelhigh 5790 lda $0,a($0) !gprellow 5791 ldq $1,b($29) !literal!100 5792 ldl $2,0($1) !lituse_base!100 5793 5794 `!literal' 5795 `!literal!N' 5796 Used with an `ldq' instruction to load the address of a symbol 5797 from the GOT. 5798 5799 A sequence number N is optional, and if present is used to pair 5800 `lituse' relocations with this `literal' relocation. The `lituse' 5801 relocations are used by the linker to optimize the code based on 5802 the final location of the symbol. 5803 5804 Note that these optimizations are dependent on the data flow of the 5805 program. Therefore, if _any_ `lituse' is paired with a `literal' 5806 relocation, then _all_ uses of the register set by the `literal' 5807 instruction must also be marked with `lituse' relocations. This 5808 is because the original `literal' instruction may be deleted or 5809 transformed into another instruction. 5810 5811 Also note that there may be a one-to-many relationship between 5812 `literal' and `lituse', but not a many-to-one. That is, if there 5813 are two code paths that load up the same address and feed the 5814 value to a single use, then the use may not use a `lituse' 5815 relocation. 5816 5817 `!lituse_base!N' 5818 Used with any memory format instruction (e.g. `ldl') to indicate 5819 that the literal is used for an address load. The offset field of 5820 the instruction must be zero. During relaxation, the code may be 5821 altered to use a gp-relative load. 5822 5823 `!lituse_jsr!N' 5824 Used with a register branch format instruction (e.g. `jsr') to 5825 indicate that the literal is used for a call. During relaxation, 5826 the code may be altered to use a direct branch (e.g. `bsr'). 5827 5828 `!lituse_jsrdirect!N' 5829 Similar to `lituse_jsr', but also that this call cannot be vectored 5830 through a PLT entry. This is useful for functions with special 5831 calling conventions which do not allow the normal call-clobbered 5832 registers to be clobbered. 5833 5834 `!lituse_bytoff!N' 5835 Used with a byte mask instruction (e.g. `extbl') to indicate that 5836 only the low 3 bits of the address are relevant. During 5837 relaxation, the code may be altered to use an immediate instead of 5838 a register shift. 5839 5840 `!lituse_addr!N' 5841 Used with any other instruction to indicate that the original 5842 address is in fact used, and the original `ldq' instruction may 5843 not be altered or deleted. This is useful in conjunction with 5844 `lituse_jsr' to test whether a weak symbol is defined. 5845 5846 ldq $27,foo($29) !literal!1 5847 beq $27,is_undef !lituse_addr!1 5848 jsr $26,($27),foo !lituse_jsr!1 5849 5850 `!lituse_tlsgd!N' 5851 Used with a register branch format instruction to indicate that the 5852 literal is the call to `__tls_get_addr' used to compute the 5853 address of the thread-local storage variable whose descriptor was 5854 loaded with `!tlsgd!N'. 5855 5856 `!lituse_tlsldm!N' 5857 Used with a register branch format instruction to indicate that the 5858 literal is the call to `__tls_get_addr' used to compute the 5859 address of the base of the thread-local storage block for the 5860 current module. The descriptor for the module must have been 5861 loaded with `!tlsldm!N'. 5862 5863 `!gpdisp!N' 5864 Used with `ldah' and `lda' to load the GP from the current 5865 address, a-la the `ldgp' macro. The source register for the 5866 `ldah' instruction must contain the address of the `ldah' 5867 instruction. There must be exactly one `lda' instruction paired 5868 with the `ldah' instruction, though it may appear anywhere in the 5869 instruction stream. The immediate operands must be zero. 5870 5871 bsr $26,foo 5872 ldah $29,0($26) !gpdisp!1 5873 lda $29,0($29) !gpdisp!1 5874 5875 `!gprelhigh' 5876 Used with an `ldah' instruction to add the high 16 bits of a 5877 32-bit displacement from the GP. 5878 5879 `!gprellow' 5880 Used with any memory format instruction to add the low 16 bits of a 5881 32-bit displacement from the GP. 5882 5883 `!gprel' 5884 Used with any memory format instruction to add a 16-bit 5885 displacement from the GP. 5886 5887 `!samegp' 5888 Used with any branch format instruction to skip the GP load at the 5889 target address. The referenced symbol must have the same GP as the 5890 source object file, and it must be declared to either not use `$27' 5891 or perform a standard GP load in the first two instructions via the 5892 `.prologue' directive. 5893 5894 `!tlsgd' 5895 `!tlsgd!N' 5896 Used with an `lda' instruction to load the address of a TLS 5897 descriptor for a symbol in the GOT. 5898 5899 The sequence number N is optional, and if present it used to pair 5900 the descriptor load with both the `literal' loading the address of 5901 the `__tls_get_addr' function and the `lituse_tlsgd' marking the 5902 call to that function. 5903 5904 For proper relaxation, both the `tlsgd', `literal' and `lituse' 5905 relocations must be in the same extended basic block. That is, 5906 the relocation with the lowest address must be executed first at 5907 runtime. 5908 5909 `!tlsldm' 5910 `!tlsldm!N' 5911 Used with an `lda' instruction to load the address of a TLS 5912 descriptor for the current module in the GOT. 5913 5914 Similar in other respects to `tlsgd'. 5915 5916 `!gotdtprel' 5917 Used with an `ldq' instruction to load the offset of the TLS 5918 symbol within its module's thread-local storage block. Also known 5919 as the dynamic thread pointer offset or dtp-relative offset. 5920 5921 `!dtprelhi' 5922 `!dtprello' 5923 `!dtprel' 5924 Like `gprel' relocations except they compute dtp-relative offsets. 5925 5926 `!gottprel' 5927 Used with an `ldq' instruction to load the offset of the TLS 5928 symbol from the thread pointer. Also known as the tp-relative 5929 offset. 5930 5931 `!tprelhi' 5932 `!tprello' 5933 `!tprel' 5934 Like `gprel' relocations except they compute tp-relative offsets. 5935 5936 5937 File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 5938 5939 9.1.4 Floating Point 5940 -------------------- 5941 5942 The Alpha family uses both IEEE and VAX floating-point numbers. 5943 5944 5945 File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 5946 5947 9.1.5 Alpha Assembler Directives 5948 -------------------------------- 5949 5950 `as' for the Alpha supports many additional directives for 5951 compatibility with the native assembler. This section describes them 5952 only briefly. 5953 5954 These are the additional directives in `as' for the Alpha: 5955 5956 `.arch CPU' 5957 Specifies the target processor. This is equivalent to the `-mCPU' 5958 command-line option. *Note Options: Alpha Options, for a list of 5959 values for CPU. 5960 5961 `.ent FUNCTION[, N]' 5962 Mark the beginning of FUNCTION. An optional number may follow for 5963 compatibility with the OSF/1 assembler, but is ignored. When 5964 generating `.mdebug' information, this will create a procedure 5965 descriptor for the function. In ELF, it will mark the symbol as a 5966 function a-la the generic `.type' directive. 5967 5968 `.end FUNCTION' 5969 Mark the end of FUNCTION. In ELF, it will set the size of the 5970 symbol a-la the generic `.size' directive. 5971 5972 `.mask MASK, OFFSET' 5973 Indicate which of the integer registers are saved in the current 5974 function's stack frame. MASK is interpreted a bit mask in which 5975 bit N set indicates that register N is saved. The registers are 5976 saved in a block located OFFSET bytes from the "canonical frame 5977 address" (CFA) which is the value of the stack pointer on entry to 5978 the function. The registers are saved sequentially, except that 5979 the return address register (normally `$26') is saved first. 5980 5981 This and the other directives that describe the stack frame are 5982 currently only used when generating `.mdebug' information. They 5983 may in the future be used to generate DWARF2 `.debug_frame' unwind 5984 information for hand written assembly. 5985 5986 `.fmask MASK, OFFSET' 5987 Indicate which of the floating-point registers are saved in the 5988 current stack frame. The MASK and OFFSET parameters are 5989 interpreted as with `.mask'. 5990 5991 `.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' 5992 Describes the shape of the stack frame. The frame pointer in use 5993 is FRAMEREG; normally this is either `$fp' or `$sp'. The frame 5994 pointer is FRAMEOFFSET bytes below the CFA. The return address is 5995 initially located in RETREG until it is saved as indicated in 5996 `.mask'. For compatibility with OSF/1 an optional ARGOFFSET 5997 parameter is accepted and ignored. It is believed to indicate the 5998 offset from the CFA to the saved argument registers. 5999 6000 `.prologue N' 6001 Indicate that the stack frame is set up and all registers have been 6002 spilled. The argument N indicates whether and how the function 6003 uses the incoming "procedure vector" (the address of the called 6004 function) in `$27'. 0 indicates that `$27' is not used; 1 6005 indicates that the first two instructions of the function use `$27' 6006 to perform a load of the GP register; 2 indicates that `$27' is 6007 used in some non-standard way and so the linker cannot elide the 6008 load of the procedure vector during relaxation. 6009 6010 `.usepv FUNCTION, WHICH' 6011 Used to indicate the use of the `$27' register, similar to 6012 `.prologue', but without the other semantics of needing to be 6013 inside an open `.ent'/`.end' block. 6014 6015 The WHICH argument should be either `no', indicating that `$27' is 6016 not used, or `std', indicating that the first two instructions of 6017 the function perform a GP load. 6018 6019 One might use this directive instead of `.prologue' if you are 6020 also using dwarf2 CFI directives. 6021 6022 `.gprel32 EXPRESSION' 6023 Computes the difference between the address in EXPRESSION and the 6024 GP for the current object file, and stores it in 4 bytes. In 6025 addition to being smaller than a full 8 byte address, this also 6026 does not require a dynamic relocation when used in a shared 6027 library. 6028 6029 `.t_floating EXPRESSION' 6030 Stores EXPRESSION as an IEEE double precision value. 6031 6032 `.s_floating EXPRESSION' 6033 Stores EXPRESSION as an IEEE single precision value. 6034 6035 `.f_floating EXPRESSION' 6036 Stores EXPRESSION as a VAX F format value. 6037 6038 `.g_floating EXPRESSION' 6039 Stores EXPRESSION as a VAX G format value. 6040 6041 `.d_floating EXPRESSION' 6042 Stores EXPRESSION as a VAX D format value. 6043 6044 `.set FEATURE' 6045 Enables or disables various assembler features. Using the positive 6046 name of the feature enables while using `noFEATURE' disables. 6047 6048 `at' 6049 Indicates that macro expansions may clobber the "assembler 6050 temporary" (`$at' or `$28') register. Some macros may not be 6051 expanded without this and will generate an error message if 6052 `noat' is in effect. When `at' is in effect, a warning will 6053 be generated if `$at' is used by the programmer. 6054 6055 `macro' 6056 Enables the expansion of macro instructions. Note that 6057 variants of real instructions, such as `br label' vs `br 6058 $31,label' are considered alternate forms and not macros. 6059 6060 `move' 6061 `reorder' 6062 `volatile' 6063 These control whether and how the assembler may re-order 6064 instructions. Accepted for compatibility with the OSF/1 6065 assembler, but `as' does not do instruction scheduling, so 6066 these features are ignored. 6067 6068 The following directives are recognized for compatibility with the 6069 OSF/1 assembler but are ignored. 6070 6071 .proc .aproc 6072 .reguse .livereg 6073 .option .aent 6074 .ugen .eflag 6075 .alias .noalias 6076 6077 6078 File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 6079 6080 9.1.6 Opcodes 6081 ------------- 6082 6083 For detailed information on the Alpha machine instruction set, see the 6084 Alpha Architecture Handbook 6085 (ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 6086 6087 6088 File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 6089 6090 9.2 ARC Dependent Features 6091 ========================== 6092 6093 * Menu: 6094 6095 * ARC Options:: Options 6096 * ARC Syntax:: Syntax 6097 * ARC Floating Point:: Floating Point 6098 * ARC Directives:: ARC Machine Directives 6099 * ARC Opcodes:: Opcodes 6100 6101 6102 File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 6103 6104 9.2.1 Options 6105 ------------- 6106 6107 `-marc[5|6|7|8]' 6108 This option selects the core processor variant. Using `-marc' is 6109 the same as `-marc6', which is also the default. 6110 6111 `arc5' 6112 Base instruction set. 6113 6114 `arc6' 6115 Jump-and-link (jl) instruction. No requirement of an 6116 instruction between setting flags and conditional jump. For 6117 example: 6118 6119 mov.f r0,r1 6120 beq foo 6121 6122 `arc7' 6123 Break (brk) and sleep (sleep) instructions. 6124 6125 `arc8' 6126 Software interrupt (swi) instruction. 6127 6128 6129 Note: the `.option' directive can to be used to select a core 6130 variant from within assembly code. 6131 6132 `-EB' 6133 This option specifies that the output generated by the assembler 6134 should be marked as being encoded for a big-endian processor. 6135 6136 `-EL' 6137 This option specifies that the output generated by the assembler 6138 should be marked as being encoded for a little-endian processor - 6139 this is the default. 6140 6141 6142 6143 File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent 6144 6145 9.2.2 Syntax 6146 ------------ 6147 6148 * Menu: 6149 6150 * ARC-Chars:: Special Characters 6151 * ARC-Regs:: Register Names 6152 6153 6154 File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 6155 6156 9.2.2.1 Special Characters 6157 .......................... 6158 6159 *TODO* 6160 6161 6162 File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 6163 6164 9.2.2.2 Register Names 6165 ...................... 6166 6167 *TODO* 6168 6169 6170 File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Syntax, Up: ARC-Dependent 6171 6172 9.2.3 Floating Point 6173 -------------------- 6174 6175 The ARC core does not currently have hardware floating point support. 6176 Software floating point support is provided by `GCC' and uses IEEE 6177 floating-point numbers. 6178 6179 6180 File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Point, Up: ARC-Dependent 6181 6182 9.2.4 ARC Machine Directives 6183 ---------------------------- 6184 6185 The ARC version of `as' supports the following additional machine 6186 directives: 6187 6188 `.2byte EXPRESSIONS' 6189 *TODO* 6190 6191 `.3byte EXPRESSIONS' 6192 *TODO* 6193 6194 `.4byte EXPRESSIONS' 6195 *TODO* 6196 6197 `.extAuxRegister NAME,ADDRESS,MODE' 6198 The ARCtangent A4 has extensible auxiliary register space. The 6199 auxiliary registers can be defined in the assembler source code by 6200 using this directive. The first parameter is the NAME of the new 6201 auxiallry register. The second parameter is the ADDRESS of the 6202 register in the auxiliary register memory map for the variant of 6203 the ARC. The third parameter specifies the MODE in which the 6204 register can be operated is and it can be one of: 6205 6206 `r (readonly)' 6207 6208 `w (write only)' 6209 6210 `r|w (read or write)' 6211 6212 For example: 6213 6214 .extAuxRegister mulhi,0x12,w 6215 6216 This specifies an extension auxiliary register called _mulhi_ 6217 which is at address 0x12 in the memory space and which is only 6218 writable. 6219 6220 `.extCondCode SUFFIX,VALUE' 6221 The condition codes on the ARCtangent A4 are extensible and can be 6222 specified by means of this assembler directive. They are specified 6223 by the suffix and the value for the condition code. They can be 6224 used to specify extra condition codes with any values. For 6225 example: 6226 6227 .extCondCode is_busy,0x14 6228 6229 add.is_busy r1,r2,r3 6230 bis_busy _main 6231 6232 `.extCoreRegister NAME,REGNUM,MODE,SHORTCUT' 6233 Specifies an extension core register NAME for the application. 6234 This allows a register NAME with a valid REGNUM between 0 and 60, 6235 with the following as valid values for MODE 6236 6237 `_r_ (readonly)' 6238 6239 `_w_ (write only)' 6240 6241 `_r|w_ (read or write)' 6242 6243 The other parameter gives a description of the register having a 6244 SHORTCUT in the pipeline. The valid values are: 6245 6246 `can_shortcut' 6247 6248 `cannot_shortcut' 6249 6250 For example: 6251 6252 .extCoreRegister mlo,57,r,can_shortcut 6253 6254 This defines an extension core register mlo with the value 57 which 6255 can shortcut the pipeline. 6256 6257 `.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS' 6258 The ARCtangent A4 allows the user to specify extension 6259 instructions. The extension instructions are not macros. The 6260 assembler creates encodings for use of these instructions 6261 according to the specification by the user. The parameters are: 6262 6263 *NAME 6264 Name of the extension instruction 6265 6266 *OPCODE 6267 Opcode to be used. (Bits 27:31 in the encoding). Valid values 6268 0x10-0x1f or 0x03 6269 6270 *SUBOPCODE 6271 Subopcode to be used. Valid values are from 0x09-0x3f. 6272 However the correct value also depends on SYNTAXCLASS 6273 6274 *SUFFIXCLASS 6275 Determines the kinds of suffixes to be allowed. Valid values 6276 are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' which 6277 indicates the absence or presence of conditional suffixes and 6278 flag setting by the extension instruction. It is also 6279 possible to specify that an instruction sets the flags and is 6280 conditional by using `SUFFIX_CODE' | `SUFFIX_FLAG'. 6281 6282 *SYNTAXCLASS 6283 Determines the syntax class for the instruction. It can have 6284 the following values: 6285 6286 ``SYNTAX_2OP':' 6287 2 Operand Instruction 6288 6289 ``SYNTAX_3OP':' 6290 3 Operand Instruction 6291 6292 In addition there could be modifiers for the syntax class as 6293 described below: 6294 6295 Syntax Class Modifiers are: 6296 6297 - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP, 6298 specifying that the first operand of a three-operand 6299 instruction must be an immediate (i.e., the result is 6300 discarded). OP1_MUST_BE_IMM is used by bitwise ORing it 6301 with SYNTAX_3OP as given in the example below. This 6302 could usually be used to set the flags using specific 6303 instructions and not retain results. 6304 6305 - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it 6306 specifies that there is an implied immediate destination 6307 operand which does not appear in the syntax. For 6308 example, if the source code contains an instruction like: 6309 6310 inst r1,r2 6311 6312 it really means that the first argument is an implied 6313 immediate (that is, the result is discarded). This is 6314 the same as though the source code were: inst 0,r1,r2. 6315 You use OP1_IMM_IMPLIED by bitwise ORing it with 6316 SYNTAX_20P. 6317 6318 6319 For example, defining 64-bit multiplier with immediate operands: 6320 6321 .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , 6322 SYNTAX_3OP|OP1_MUST_BE_IMM 6323 6324 The above specifies an extension instruction called mp64 which has 6325 3 operands, sets the flags, can be used with a condition code, for 6326 which the first operand is an immediate. (Equivalent to 6327 discarding the result of the operation). 6328 6329 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED 6330 6331 This describes a 2 operand instruction with an implicit first 6332 immediate operand. The result of this operation would be 6333 discarded. 6334 6335 `.half EXPRESSIONS' 6336 *TODO* 6337 6338 `.long EXPRESSIONS' 6339 *TODO* 6340 6341 `.option ARC|ARC5|ARC6|ARC7|ARC8' 6342 The `.option' directive must be followed by the desired core 6343 version. Again `arc' is an alias for `arc6'. 6344 6345 Note: the `.option' directive overrides the command line option 6346 `-marc'; a warning is emitted when the version is not consistent 6347 between the two - even for the implicit default core version 6348 (arc6). 6349 6350 `.short EXPRESSIONS' 6351 *TODO* 6352 6353 `.word EXPRESSIONS' 6354 *TODO* 6355 6356 6357 6358 File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent 6359 6360 9.2.5 Opcodes 6361 ------------- 6362 6363 For information on the ARC instruction set, see `ARC Programmers 6364 Reference Manual', ARC International (www.arc.com) 6365 6366 6367 File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 6368 6369 9.3 ARM Dependent Features 6370 ========================== 6371 6372 * Menu: 6373 6374 * ARM Options:: Options 6375 * ARM Syntax:: Syntax 6376 * ARM Floating Point:: Floating Point 6377 * ARM Directives:: ARM Machine Directives 6378 * ARM Opcodes:: Opcodes 6379 * ARM Mapping Symbols:: Mapping Symbols 6380 * ARM Unwinding Tutorial:: Unwinding 6381 6382 6383 File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 6384 6385 9.3.1 Options 6386 ------------- 6387 6388 `-mcpu=PROCESSOR[+EXTENSION...]' 6389 This option specifies the target processor. The assembler will 6390 issue an error message if an attempt is made to assemble an 6391 instruction which will not execute on the target processor. The 6392 following processor names are recognized: `arm1', `arm2', `arm250', 6393 `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', 6394 `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', 6395 `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t', 6396 `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi', 6397 `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1', 6398 `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920', 6399 `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday 6400 FA526 processor), `fa626' (Faraday FA626 processor), `arm9e', 6401 `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', 6402 `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t', 6403 `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e', 6404 `arm1022e', `arm1026ej-s', `fa626te' (Faraday FA626TE processor), 6405 `fa726te' (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s', 6406 `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', 6407 `mpcore', `mpcorenovfp', `cortex-a5', `cortex-a8', `cortex-a9', 6408 `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-m4', `cortex-m3', 6409 `cortex-m1', `cortex-m0', `ep9312' (ARM920 with Cirrus Maverick 6410 coprocessor), `i80200' (Intel XScale processor) `iwmmxt' (Intel(r) 6411 XScale processor with Wireless MMX(tm) technology coprocessor) and 6412 `xscale'. The special name `all' may be used to allow the 6413 assembler to accept instructions valid for any ARM processor. 6414 6415 In addition to the basic instruction set, the assembler can be 6416 told to accept various extension mnemonics that extend the 6417 processor using the co-processor instruction space. For example, 6418 `-mcpu=arm920+maverick' is equivalent to specifying `-mcpu=ep9312'. 6419 6420 Multiple extensions may be specified, separated by a `+'. The 6421 extensions should be specified in ascending alphabetical order. 6422 6423 Some extensions may be restricted to particular architectures; 6424 this is documented in the list of extensions below. 6425 6426 Extension mnemonics may also be removed from those the assembler 6427 accepts. This is done be prepending `no' to the option that adds 6428 the extension. Extensions that are removed should be listed after 6429 all extensions which have been added, again in ascending 6430 alphabetical order. For example, `-mcpu=ep9312+nomaverick' is 6431 equivalent to specifying `-mcpu=arm920'. 6432 6433 The following extensions are currently supported: `idiv', (Integer 6434 Divide Extensions for v7-A architecture), `iwmmxt', `iwmmxt2', 6435 `maverick', `mp' (Multiprocessing Extensions for v7-A and v7-R 6436 architectures), `os' (Operating System for v6M architecture), 6437 `sec' (Security Extensions for v6K and v7-A architectures), `virt' 6438 (Virtualization Extensions for v7-A architecture, implies `idiv'), 6439 and `xscale'. 6440 6441 `-march=ARCHITECTURE[+EXTENSION...]' 6442 This option specifies the target architecture. The assembler will 6443 issue an error message if an attempt is made to assemble an 6444 instruction which will not execute on the target architecture. 6445 The following architecture names are recognized: `armv1', `armv2', 6446 `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm', 6447 `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te', 6448 `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk', 6449 `armv6-m', `armv6s-m', `armv7', `armv7-a', `armv7-r', `armv7-m', 6450 `armv7e-m', `iwmmxt' and `xscale'. If both `-mcpu' and `-march' 6451 are specified, the assembler will use the setting for `-mcpu'. 6452 6453 The architecture option can be extended with the same instruction 6454 set extension options as the `-mcpu' option. 6455 6456 `-mfpu=FLOATING-POINT-FORMAT' 6457 This option specifies the floating point format to assemble for. 6458 The assembler will issue an error message if an attempt is made to 6459 assemble an instruction which will not execute on the target 6460 floating point unit. The following format options are recognized: 6461 `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11', 6462 `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0', 6463 `vfp9', `vfpxd', `vfpv2', `vfpv3', `vfpv3-fp16', `vfpv3-d16', 6464 `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-d16', `vfpv4', `vfpv4-d16', 6465 `fpv4-sp-d16', `arm1020t', `arm1020e', `arm1136jf-s', `maverick', 6466 `neon', and `neon-vfpv4'. 6467 6468 In addition to determining which instructions are assembled, this 6469 option also affects the way in which the `.double' assembler 6470 directive behaves when assembling little-endian code. 6471 6472 The default is dependent on the processor selected. For 6473 Architecture 5 or later, the default is to assembler for VFP 6474 instructions; for earlier architectures the default is to assemble 6475 for FPA instructions. 6476 6477 `-mthumb' 6478 This option specifies that the assembler should start assembling 6479 Thumb instructions; that is, it should behave as though the file 6480 starts with a `.code 16' directive. 6481 6482 `-mthumb-interwork' 6483 This option specifies that the output generated by the assembler 6484 should be marked as supporting interworking. 6485 6486 `-mimplicit-it=never' 6487 `-mimplicit-it=always' 6488 `-mimplicit-it=arm' 6489 `-mimplicit-it=thumb' 6490 The `-mimplicit-it' option controls the behavior of the assembler 6491 when conditional instructions are not enclosed in IT blocks. 6492 There are four possible behaviors. If `never' is specified, such 6493 constructs cause a warning in ARM code and an error in Thumb-2 6494 code. If `always' is specified, such constructs are accepted in 6495 both ARM and Thumb-2 code, where the IT instruction is added 6496 implicitly. If `arm' is specified, such constructs are accepted 6497 in ARM code and cause an error in Thumb-2 code. If `thumb' is 6498 specified, such constructs cause a warning in ARM code and are 6499 accepted in Thumb-2 code. If you omit this option, the behavior 6500 is equivalent to `-mimplicit-it=arm'. 6501 6502 `-mapcs-26' 6503 `-mapcs-32' 6504 These options specify that the output generated by the assembler 6505 should be marked as supporting the indicated version of the Arm 6506 Procedure. Calling Standard. 6507 6508 `-matpcs' 6509 This option specifies that the output generated by the assembler 6510 should be marked as supporting the Arm/Thumb Procedure Calling 6511 Standard. If enabled this option will cause the assembler to 6512 create an empty debugging section in the object file called 6513 .arm.atpcs. Debuggers can use this to determine the ABI being 6514 used by. 6515 6516 `-mapcs-float' 6517 This indicates the floating point variant of the APCS should be 6518 used. In this variant floating point arguments are passed in FP 6519 registers rather than integer registers. 6520 6521 `-mapcs-reentrant' 6522 This indicates that the reentrant variant of the APCS should be 6523 used. This variant supports position independent code. 6524 6525 `-mfloat-abi=ABI' 6526 This option specifies that the output generated by the assembler 6527 should be marked as using specified floating point ABI. The 6528 following values are recognized: `soft', `softfp' and `hard'. 6529 6530 `-meabi=VER' 6531 This option specifies which EABI version the produced object files 6532 should conform to. The following values are recognized: `gnu', `4' 6533 and `5'. 6534 6535 `-EB' 6536 This option specifies that the output generated by the assembler 6537 should be marked as being encoded for a big-endian processor. 6538 6539 `-EL' 6540 This option specifies that the output generated by the assembler 6541 should be marked as being encoded for a little-endian processor. 6542 6543 `-k' 6544 This option specifies that the output of the assembler should be 6545 marked as position-independent code (PIC). 6546 6547 `--fix-v4bx' 6548 Allow `BX' instructions in ARMv4 code. This is intended for use 6549 with the linker option of the same name. 6550 6551 `-mwarn-deprecated' 6552 `-mno-warn-deprecated' 6553 Enable or disable warnings about using deprecated options or 6554 features. The default is to warn. 6555 6556 6557 6558 File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 6559 6560 9.3.2 Syntax 6561 ------------ 6562 6563 * Menu: 6564 6565 * ARM-Instruction-Set:: Instruction Set 6566 * ARM-Chars:: Special Characters 6567 * ARM-Regs:: Register Names 6568 * ARM-Relocations:: Relocations 6569 * ARM-Neon-Alignment:: NEON Alignment Specifiers 6570 6571 6572 File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 6573 6574 9.3.2.1 Instruction Set Syntax 6575 .............................. 6576 6577 Two slightly different syntaxes are support for ARM and THUMB 6578 instructions. The default, `divided', uses the old style where ARM and 6579 THUMB instructions had their own, separate syntaxes. The new, 6580 `unified' syntax, which can be selected via the `.syntax' directive, 6581 and has the following main features: 6582 6583 * 6584 Immediate operands do not require a `#' prefix. 6585 6586 * 6587 The `IT' instruction may appear, and if it does it is validated 6588 against subsequent conditional affixes. In ARM mode it does not 6589 generate machine code, in THUMB mode it does. 6590 6591 * 6592 For ARM instructions the conditional affixes always appear at the 6593 end of the instruction. For THUMB instructions conditional 6594 affixes can be used, but only inside the scope of an `IT' 6595 instruction. 6596 6597 * 6598 All of the instructions new to the V6T2 architecture (and later) 6599 are available. (Only a few such instructions can be written in the 6600 `divided' syntax). 6601 6602 * 6603 The `.N' and `.W' suffixes are recognized and honored. 6604 6605 * 6606 All instructions set the flags if and only if they have an `s' 6607 affix. 6608 6609 6610 File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 6611 6612 9.3.2.2 Special Characters 6613 .......................... 6614 6615 The presence of a `@' on a line indicates the start of a comment that 6616 extends to the end of the current line. If a `#' appears as the first 6617 character of a line, the whole line is treated as a comment. 6618 6619 The `;' character can be used instead of a newline to separate 6620 statements. 6621 6622 Either `#' or `$' can be used to indicate immediate operands. 6623 6624 *TODO* Explain about /data modifier on symbols. 6625 6626 6627 File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 6628 6629 9.3.2.3 Register Names 6630 ...................... 6631 6632 *TODO* Explain about ARM register naming, and the predefined names. 6633 6634 6635 File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 6636 6637 9.3.2.4 NEON Alignment Specifiers 6638 ................................. 6639 6640 Some NEON load/store instructions allow an optional address alignment 6641 qualifier. The ARM documentation specifies that this is indicated by 6642 `@ ALIGN'. However GAS already interprets the `@' character as a "line 6643 comment" start, so `: ALIGN' is used instead. For example: 6644 6645 vld1.8 {q0}, [r0, :128] 6646 6647 6648 File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 6649 6650 9.3.3 Floating Point 6651 -------------------- 6652 6653 The ARM family uses IEEE floating-point numbers. 6654 6655 6656 File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 6657 6658 9.3.3.1 ARM relocation generation 6659 ................................. 6660 6661 Specific data relocations can be generated by putting the relocation 6662 name in parentheses after the symbol name. For example: 6663 6664 .word foo(TARGET1) 6665 6666 This will generate an `R_ARM_TARGET1' relocation against the symbol 6667 FOO. The following relocations are supported: `GOT', `GOTOFF', 6668 `TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `GOTTPOFF', 6669 `GOT_PREL' and `TPOFF'. 6670 6671 For compatibility with older toolchains the assembler also accepts 6672 `(PLT)' after branch targets. This will generate the deprecated 6673 `R_ARM_PLT32' relocation. 6674 6675 Relocations for `MOVW' and `MOVT' instructions can be generated by 6676 prefixing the value with `#:lower16:' and `#:upper16' respectively. 6677 For example to load the 32-bit address of foo into r0: 6678 6679 MOVW r0, #:lower16:foo 6680 MOVT r0, #:upper16:foo 6681 6682 6683 File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 6684 6685 9.3.4 ARM Machine Directives 6686 ---------------------------- 6687 6688 `.2byte EXPRESSION [, EXPRESSION]*' 6689 `.4byte EXPRESSION [, EXPRESSION]*' 6690 `.8byte EXPRESSION [, EXPRESSION]*' 6691 These directives write 2, 4 or 8 byte values to the output section. 6692 6693 `.align EXPRESSION [, EXPRESSION]' 6694 This is the generic .ALIGN directive. For the ARM however if the 6695 first argument is zero (ie no alignment is needed) the assembler 6696 will behave as if the argument had been 2 (ie pad to the next four 6697 byte boundary). This is for compatibility with ARM's own 6698 assembler. 6699 6700 `.arch NAME' 6701 Select the target architecture. Valid values for NAME are the 6702 same as for the `-march' commandline option. 6703 6704 Specifying `.arch' clears any previously selected architecture 6705 extensions. 6706 6707 `.arch_extension NAME' 6708 Add or remove an architecture extension to the target 6709 architecture. Valid values for NAME are the same as those 6710 accepted as architectural extensions by the `-mcpu' commandline 6711 option. 6712 6713 `.arch_extension' may be used multiple times to add or remove 6714 extensions incrementally to the architecture being compiled for. 6715 6716 `.arm' 6717 This performs the same action as .CODE 32. 6718 6719 `.pad #COUNT' 6720 Generate unwinder annotations for a stack adjustment of COUNT 6721 bytes. A positive value indicates the function prologue allocated 6722 stack space by decrementing the stack pointer. 6723 6724 `.bss' 6725 This directive switches to the `.bss' section. 6726 6727 `.cantunwind' 6728 Prevents unwinding through the current function. No personality 6729 routine or exception table data is required or permitted. 6730 6731 `.code `[16|32]'' 6732 This directive selects the instruction set being generated. The 6733 value 16 selects Thumb, with the value 32 selecting ARM. 6734 6735 `.cpu NAME' 6736 Select the target processor. Valid values for NAME are the same as 6737 for the `-mcpu' commandline option. 6738 6739 Specifying `.cpu' clears any previously selected architecture 6740 extensions. 6741 6742 `NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' 6743 `NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' 6744 The `dn' and `qn' directives are used to create typed and/or 6745 indexed register aliases for use in Advanced SIMD Extension (Neon) 6746 instructions. The former should be used to create aliases of 6747 double-precision registers, and the latter to create aliases of 6748 quad-precision registers. 6749 6750 If these directives are used to create typed aliases, those 6751 aliases can be used in Neon instructions instead of writing types 6752 after the mnemonic or after each operand. For example: 6753 6754 x .dn d2.f32 6755 y .dn d3.f32 6756 z .dn d4.f32[1] 6757 vmul x,y,z 6758 6759 This is equivalent to writing the following: 6760 6761 vmul.f32 d2,d3,d4[1] 6762 6763 Aliases created using `dn' or `qn' can be destroyed using `unreq'. 6764 6765 `.eabi_attribute TAG, VALUE' 6766 Set the EABI object attribute TAG to VALUE. 6767 6768 The TAG is either an attribute number, or one of the following: 6769 `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch', 6770 `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use', 6771 `Tag_FP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch', 6772 `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data', 6773 `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use', 6774 `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding', 6775 `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions', 6776 `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model', 6777 `Tag_ABI_align_needed', `Tag_ABI_align_preserved', 6778 `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args', 6779 `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals', 6780 `Tag_ABI_FP_optimization_goals', `Tag_compatibility', 6781 `Tag_CPU_unaligned_access', `Tag_FP_HP_extension', 6782 `Tag_ABI_FP_16bit_format', `Tag_MPextension_use', `Tag_DIV_use', 6783 `Tag_nodefaults', `Tag_also_compatible_with', `Tag_conformance', 6784 `Tag_T2EE_use', `Tag_Virtualization_use' 6785 6786 The VALUE is either a `number', `"string"', or `number, "string"' 6787 depending on the tag. 6788 6789 Note - the following legacy values are also accepted by TAG: 6790 `Tag_VFP_arch', `Tag_ABI_align8_needed', 6791 `Tag_ABI_align8_preserved', `Tag_VFP_HP_extension', 6792 6793 `.even' 6794 This directive aligns to an even-numbered address. 6795 6796 `.extend EXPRESSION [, EXPRESSION]*' 6797 `.ldouble EXPRESSION [, EXPRESSION]*' 6798 These directives write 12byte long double floating-point values to 6799 the output section. These are not compatible with current ARM 6800 processors or ABIs. 6801 6802 `.fnend' 6803 Marks the end of a function with an unwind table entry. The 6804 unwind index table entry is created when this directive is 6805 processed. 6806 6807 If no personality routine has been specified then standard 6808 personality routine 0 or 1 will be used, depending on the number 6809 of unwind opcodes required. 6810 6811 `.fnstart' 6812 Marks the start of a function with an unwind table entry. 6813 6814 `.force_thumb' 6815 This directive forces the selection of Thumb instructions, even if 6816 the target processor does not support those instructions 6817 6818 `.fpu NAME' 6819 Select the floating-point unit to assemble for. Valid values for 6820 NAME are the same as for the `-mfpu' commandline option. 6821 6822 `.handlerdata' 6823 Marks the end of the current function, and the start of the 6824 exception table entry for that function. Anything between this 6825 directive and the `.fnend' directive will be added to the 6826 exception table entry. 6827 6828 Must be preceded by a `.personality' or `.personalityindex' 6829 directive. 6830 6831 `.inst OPCODE [ , ... ]' 6832 `.inst.n OPCODE [ , ... ]' 6833 `.inst.w OPCODE [ , ... ]' 6834 Generates the instruction corresponding to the numerical value 6835 OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size 6836 to be specified explicitly, overriding the normal encoding rules. 6837 6838 `.ldouble EXPRESSION [, EXPRESSION]*' 6839 See `.extend'. 6840 6841 `.ltorg' 6842 This directive causes the current contents of the literal pool to 6843 be dumped into the current section (which is assumed to be the 6844 .text section) at the current location (aligned to a word 6845 boundary). `GAS' maintains a separate literal pool for each 6846 section and each sub-section. The `.ltorg' directive will only 6847 affect the literal pool of the current section and sub-section. 6848 At the end of assembly all remaining, un-empty literal pools will 6849 automatically be dumped. 6850 6851 Note - older versions of `GAS' would dump the current literal pool 6852 any time a section change occurred. This is no longer done, since 6853 it prevents accurate control of the placement of literal pools. 6854 6855 `.movsp REG [, #OFFSET]' 6856 Tell the unwinder that REG contains an offset from the current 6857 stack pointer. If OFFSET is not specified then it is assumed to be 6858 zero. 6859 6860 `.object_arch NAME' 6861 Override the architecture recorded in the EABI object attribute 6862 section. Valid values for NAME are the same as for the `.arch' 6863 directive. Typically this is useful when code uses runtime 6864 detection of CPU features. 6865 6866 `.packed EXPRESSION [, EXPRESSION]*' 6867 This directive writes 12-byte packed floating-point values to the 6868 output section. These are not compatible with current ARM 6869 processors or ABIs. 6870 6871 `.pad #COUNT' 6872 Generate unwinder annotations for a stack adjustment of COUNT 6873 bytes. A positive value indicates the function prologue allocated 6874 stack space by decrementing the stack pointer. 6875 6876 `.personality NAME' 6877 Sets the personality routine for the current function to NAME. 6878 6879 `.personalityindex INDEX' 6880 Sets the personality routine for the current function to the EABI 6881 standard routine number INDEX 6882 6883 `.pool' 6884 This is a synonym for .ltorg. 6885 6886 `NAME .req REGISTER NAME' 6887 This creates an alias for REGISTER NAME called NAME. For example: 6888 6889 foo .req r0 6890 6891 `.save REGLIST' 6892 Generate unwinder annotations to restore the registers in REGLIST. 6893 The format of REGLIST is the same as the corresponding 6894 store-multiple instruction. 6895 6896 _core registers_ 6897 .save {r4, r5, r6, lr} 6898 stmfd sp!, {r4, r5, r6, lr} 6899 _FPA registers_ 6900 .save f4, 2 6901 sfmfd f4, 2, [sp]! 6902 _VFP registers_ 6903 .save {d8, d9, d10} 6904 fstmdx sp!, {d8, d9, d10} 6905 _iWMMXt registers_ 6906 .save {wr10, wr11} 6907 wstrd wr11, [sp, #-8]! 6908 wstrd wr10, [sp, #-8]! 6909 or 6910 .save wr11 6911 wstrd wr11, [sp, #-8]! 6912 .save wr10 6913 wstrd wr10, [sp, #-8]! 6914 6915 `.setfp FPREG, SPREG [, #OFFSET]' 6916 Make all unwinder annotations relative to a frame pointer. 6917 Without this the unwinder will use offsets from the stack pointer. 6918 6919 The syntax of this directive is the same as the `add' or `mov' 6920 instruction used to set the frame pointer. SPREG must be either 6921 `sp' or mentioned in a previous `.movsp' directive. 6922 6923 .movsp ip 6924 mov ip, sp 6925 ... 6926 .setfp fp, ip, #4 6927 add fp, ip, #4 6928 6929 `.secrel32 EXPRESSION [, EXPRESSION]*' 6930 This directive emits relocations that evaluate to the 6931 section-relative offset of each expression's symbol. This 6932 directive is only supported for PE targets. 6933 6934 `.syntax [`unified' | `divided']' 6935 This directive sets the Instruction Set Syntax as described in the 6936 *note ARM-Instruction-Set:: section. 6937 6938 `.thumb' 6939 This performs the same action as .CODE 16. 6940 6941 `.thumb_func' 6942 This directive specifies that the following symbol is the name of a 6943 Thumb encoded function. This information is necessary in order to 6944 allow the assembler and linker to generate correct code for 6945 interworking between Arm and Thumb instructions and should be used 6946 even if interworking is not going to be performed. The presence 6947 of this directive also implies `.thumb' 6948 6949 This directive is not neccessary when generating EABI objects. On 6950 these targets the encoding is implicit when generating Thumb code. 6951 6952 `.thumb_set' 6953 This performs the equivalent of a `.set' directive in that it 6954 creates a symbol which is an alias for another symbol (possibly 6955 not yet defined). This directive also has the added property in 6956 that it marks the aliased symbol as being a thumb function entry 6957 point, in the same way that the `.thumb_func' directive does. 6958 6959 `.unreq ALIAS-NAME' 6960 This undefines a register alias which was previously defined using 6961 the `req', `dn' or `qn' directives. For example: 6962 6963 foo .req r0 6964 .unreq foo 6965 6966 An error occurs if the name is undefined. Note - this pseudo op 6967 can be used to delete builtin in register name aliases (eg 'r0'). 6968 This should only be done if it is really necessary. 6969 6970 `.unwind_raw OFFSET, BYTE1, ...' 6971 Insert one of more arbitary unwind opcode bytes, which are known 6972 to adjust the stack pointer by OFFSET bytes. 6973 6974 For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save 6975 {r0}' 6976 6977 `.vsave VFP-REGLIST' 6978 Generate unwinder annotations to restore the VFP registers in 6979 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are 6980 to be restored using VLDM. The format of VFP-REGLIST is the same 6981 as the corresponding store-multiple instruction. 6982 6983 _VFP registers_ 6984 .vsave {d8, d9, d10} 6985 fstmdd sp!, {d8, d9, d10} 6986 _VFPv3 registers_ 6987 .vsave {d15, d16, d17} 6988 vstm sp!, {d15, d16, d17} 6989 6990 Since FLDMX and FSTMX are now deprecated, this directive should be 6991 used in favour of `.save' for saving VFP registers for ARMv6 and 6992 above. 6993 6994 6995 6996 File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 6997 6998 9.3.5 Opcodes 6999 ------------- 7000 7001 `as' implements all the standard ARM opcodes. It also implements 7002 several pseudo opcodes, including several synthetic load instructions. 7003 7004 `NOP' 7005 nop 7006 7007 This pseudo op will always evaluate to a legal ARM instruction 7008 that does nothing. Currently it will evaluate to MOV r0, r0. 7009 7010 `LDR' 7011 ldr <register> , = <expression> 7012 7013 If expression evaluates to a numeric constant then a MOV or MVN 7014 instruction will be used in place of the LDR instruction, if the 7015 constant can be generated by either of these instructions. 7016 Otherwise the constant will be placed into the nearest literal 7017 pool (if it not already there) and a PC relative LDR instruction 7018 will be generated. 7019 7020 `ADR' 7021 adr <register> <label> 7022 7023 This instruction will load the address of LABEL into the indicated 7024 register. The instruction will evaluate to a PC relative ADD or 7025 SUB instruction depending upon where the label is located. If the 7026 label is out of range, or if it is not defined in the same file 7027 (and section) as the ADR instruction, then an error will be 7028 generated. This instruction will not make use of the literal pool. 7029 7030 `ADRL' 7031 adrl <register> <label> 7032 7033 This instruction will load the address of LABEL into the indicated 7034 register. The instruction will evaluate to one or two PC relative 7035 ADD or SUB instructions depending upon where the label is located. 7036 If a second instruction is not needed a NOP instruction will be 7037 generated in its place, so that this instruction is always 8 bytes 7038 long. 7039 7040 If the label is out of range, or if it is not defined in the same 7041 file (and section) as the ADRL instruction, then an error will be 7042 generated. This instruction will not make use of the literal pool. 7043 7044 7045 For information on the ARM or Thumb instruction sets, see `ARM 7046 Software Development Toolkit Reference Manual', Advanced RISC Machines 7047 Ltd. 7048 7049 7050 File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 7051 7052 9.3.6 Mapping Symbols 7053 --------------------- 7054 7055 The ARM ELF specification requires that special symbols be inserted 7056 into object files to mark certain features: 7057 7058 `$a' 7059 At the start of a region of code containing ARM instructions. 7060 7061 `$t' 7062 At the start of a region of code containing THUMB instructions. 7063 7064 `$d' 7065 At the start of a region of data. 7066 7067 7068 The assembler will automatically insert these symbols for you - there 7069 is no need to code them yourself. Support for tagging symbols ($b, $f, 7070 $p and $m) which is also mentioned in the current ARM ELF specification 7071 is not implemented. This is because they have been dropped from the 7072 new EABI and so tools cannot rely upon their presence. 7073 7074 7075 File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 7076 7077 9.3.7 Unwinding 7078 --------------- 7079 7080 The ABI for the ARM Architecture specifies a standard format for 7081 exception unwind information. This information is used when an 7082 exception is thrown to determine where control should be transferred. 7083 In particular, the unwind information is used to determine which 7084 function called the function that threw the exception, and which 7085 function called that one, and so forth. This information is also used 7086 to restore the values of callee-saved registers in the function 7087 catching the exception. 7088 7089 If you are writing functions in assembly code, and those functions 7090 call other functions that throw exceptions, you must use assembly 7091 pseudo ops to ensure that appropriate exception unwind information is 7092 generated. Otherwise, if one of the functions called by your assembly 7093 code throws an exception, the run-time library will be unable to unwind 7094 the stack through your assembly code and your program will not behave 7095 correctly. 7096 7097 To illustrate the use of these pseudo ops, we will examine the code 7098 that G++ generates for the following C++ input: 7099 7100 void callee (int *); 7101 7102 int 7103 caller () 7104 { 7105 int i; 7106 callee (&i); 7107 return i; 7108 } 7109 7110 This example does not show how to throw or catch an exception from 7111 assembly code. That is a much more complex operation and should always 7112 be done in a high-level language, such as C++, that directly supports 7113 exceptions. 7114 7115 The code generated by one particular version of G++ when compiling 7116 the example above is: 7117 7118 _Z6callerv: 7119 .fnstart 7120 .LFB2: 7121 @ Function supports interworking. 7122 @ args = 0, pretend = 0, frame = 8 7123 @ frame_needed = 1, uses_anonymous_args = 0 7124 stmfd sp!, {fp, lr} 7125 .save {fp, lr} 7126 .LCFI0: 7127 .setfp fp, sp, #4 7128 add fp, sp, #4 7129 .LCFI1: 7130 .pad #8 7131 sub sp, sp, #8 7132 .LCFI2: 7133 sub r3, fp, #8 7134 mov r0, r3 7135 bl _Z6calleePi 7136 ldr r3, [fp, #-8] 7137 mov r0, r3 7138 sub sp, fp, #4 7139 ldmfd sp!, {fp, lr} 7140 bx lr 7141 .LFE2: 7142 .fnend 7143 7144 Of course, the sequence of instructions varies based on the options 7145 you pass to GCC and on the version of GCC in use. The exact 7146 instructions are not important since we are focusing on the pseudo ops 7147 that are used to generate unwind information. 7148 7149 An important assumption made by the unwinder is that the stack frame 7150 does not change during the body of the function. In particular, since 7151 we assume that the assembly code does not itself throw an exception, 7152 the only point where an exception can be thrown is from a call, such as 7153 the `bl' instruction above. At each call site, the same saved 7154 registers (including `lr', which indicates the return address) must be 7155 located in the same locations relative to the frame pointer. 7156 7157 The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op 7158 appears immediately before the first instruction of the function while 7159 the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears 7160 immediately after the last instruction of the function. These pseudo 7161 ops specify the range of the function. 7162 7163 Only the order of the other pseudos ops (e.g., `.setfp' or `.pad') 7164 matters; their exact locations are irrelevant. In the example above, 7165 the compiler emits the pseudo ops with particular instructions. That 7166 makes it easier to understand the code, but it is not required for 7167 correctness. It would work just as well to emit all of the pseudo ops 7168 other than `.fnend' in the same order, but immediately after `.fnstart'. 7169 7170 The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates 7171 registers that have been saved to the stack so that they can be 7172 restored before the function returns. The argument to the `.save' 7173 pseudo op is a list of registers to save. If a register is 7174 "callee-saved" (as specified by the ABI) and is modified by the 7175 function you are writing, then your code must save the value before it 7176 is modified and restore the original value before the function returns. 7177 If an exception is thrown, the run-time library restores the values of 7178 these registers from their locations on the stack before returning 7179 control to the exception handler. (Of course, if an exception is not 7180 thrown, the function that contains the `.save' pseudo op restores these 7181 registers in the function epilogue, as is done with the `ldmfd' 7182 instruction above.) 7183 7184 You do not have to save callee-saved registers at the very beginning 7185 of the function and you do not need to use the `.save' pseudo op 7186 immediately following the point at which the registers are saved. 7187 However, if you modify a callee-saved register, you must save it on the 7188 stack before modifying it and before calling any functions which might 7189 throw an exception. And, you must use the `.save' pseudo op to 7190 indicate that you have done so. 7191 7192 The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification 7193 of the stack pointer that does not save any registers. The argument is 7194 the number of bytes (in decimal) that are subtracted from the stack 7195 pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 7196 the stack pointer increases the size of the stack.) 7197 7198 The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op 7199 indicates the register that contains the frame pointer. The first 7200 argument is the register that is set, which is typically `fp'. The 7201 second argument indicates the register from which the frame pointer 7202 takes its value. The third argument, if present, is the value (in 7203 decimal) added to the register specified by the second argument to 7204 compute the value of the frame pointer. You should not modify the 7205 frame pointer in the body of the function. 7206 7207 If you do not use a frame pointer, then you should not use the 7208 `.setfp' pseudo op. If you do not use a frame pointer, then you should 7209 avoid modifying the stack pointer outside of the function prologue. 7210 Otherwise, the run-time library will be unable to find saved registers 7211 when it is unwinding the stack. 7212 7213 The pseudo ops described above are sufficient for writing assembly 7214 code that calls functions which may throw exceptions. If you need to 7215 know more about the object-file format used to represent unwind 7216 information, you may consult the `Exception Handling ABI for the ARM 7217 Architecture' available from `http://infocenter.arm.com'. 7218 7219 7220 File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 7221 7222 9.4 AVR Dependent Features 7223 ========================== 7224 7225 * Menu: 7226 7227 * AVR Options:: Options 7228 * AVR Syntax:: Syntax 7229 * AVR Opcodes:: Opcodes 7230 7231 7232 File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 7233 7234 9.4.1 Options 7235 ------------- 7236 7237 `-mmcu=MCU' 7238 Specify ATMEL AVR instruction set or MCU type. 7239 7240 Instruction set avr1 is for the minimal AVR core, not supported by 7241 the C compiler, only for assembler programs (MCU types: at90s1200, 7242 attiny11, attiny12, attiny15, attiny28). 7243 7244 Instruction set avr2 (default) is for the classic AVR core with up 7245 to 8K program memory space (MCU types: at90s2313, at90s2323, 7246 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 7247 at90s4434, at90s8515, at90c8534, at90s8535). 7248 7249 Instruction set avr25 is for the classic AVR core with up to 8K 7250 program memory space plus the MOVW instruction (MCU types: 7251 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 7252 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 7253 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 7254 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 7255 at86rf401, ata6289). 7256 7257 Instruction set avr3 is for the classic AVR core with up to 128K 7258 program memory space (MCU types: at43usb355, at76c711). 7259 7260 Instruction set avr31 is for the classic AVR core with exactly 7261 128K program memory space (MCU types: atmega103, at43usb320). 7262 7263 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 7264 JMP instructions (MCU types: attiny167, at90usb82, at90usb162, 7265 atmega8u2, atmega16u2, atmega32u2). 7266 7267 Instruction set avr4 is for the enhanced AVR core with up to 8K 7268 program memory space (MCU types: atmega48, atmega48a, atmega48p, 7269 atmega8, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, 7270 atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, 7271 at90pwm3b, at90pwm81). 7272 7273 Instruction set avr5 is for the enhanced AVR core with up to 128K 7274 program memory space (MCU types: atmega16, atmega16a, atmega161, 7275 atmega162, atmega163, atmega164a, atmega164p, atmega165, 7276 atmega165a, atmega165p, atmega168, atmega168a, atmega168p, 7277 atmega169, atmega169a, atmega169p, atmega169pa, atmega32, 7278 atmega323, atmega324a, atmega324p, atmega325, atmega325a, 7279 atmega325p, atmega3250, atmega3250a, atmega3250p, atmega328, 7280 atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, 7281 atmega3290, atmega3290a, atmega3290p, atmega406, atmega64, 7282 atmega640, atmega644, atmega644a, atmega644p, atmega644pa, 7283 atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, 7284 atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, 7285 atmega6490a, atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, 7286 atmega32hvb, atmega64hve, at90can32, at90can64, at90pwm216, 7287 at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, 7288 atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, 7289 at90usb647, at94k, at90scr100). 7290 7291 Instruction set avr51 is for the enhanced AVR core with exactly 7292 128K program memory space (MCU types: atmega128, atmega1280, 7293 atmega1281, atmega1284p, atmega128rfa1, at90can128, at90usb1286, 7294 at90usb1287, m3000). 7295 7296 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 7297 (MCU types: atmega2560, atmega2561). 7298 7299 `-mall-opcodes' 7300 Accept all AVR opcodes, even if not supported by `-mmcu'. 7301 7302 `-mno-skip-bug' 7303 This option disable warnings for skipping two-word instructions. 7304 7305 `-mno-wrap' 7306 This option reject `rjmp/rcall' instructions with 8K wrap-around. 7307 7308 7309 7310 File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 7311 7312 9.4.2 Syntax 7313 ------------ 7314 7315 * Menu: 7316 7317 * AVR-Chars:: Special Characters 7318 * AVR-Regs:: Register Names 7319 * AVR-Modifiers:: Relocatable Expression Modifiers 7320 7321 7322 File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 7323 7324 9.4.2.1 Special Characters 7325 .......................... 7326 7327 The presence of a `;' on a line indicates the start of a comment that 7328 extends to the end of the current line. If a `#' appears as the first 7329 character of a line, the whole line is treated as a comment. 7330 7331 The `$' character can be used instead of a newline to separate 7332 statements. 7333 7334 7335 File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 7336 7337 9.4.2.2 Register Names 7338 ...................... 7339 7340 The AVR has 32 x 8-bit general purpose working registers `r0', `r1', 7341 ... `r31'. Six of the 32 registers can be used as three 16-bit 7342 indirect address register pointers for Data Space addressing. One of 7343 the these address pointers can also be used as an address pointer for 7344 look up tables in Flash program memory. These added function registers 7345 are the 16-bit `X', `Y' and `Z' - registers. 7346 7347 X = r26:r27 7348 Y = r28:r29 7349 Z = r30:r31 7350 7351 7352 File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 7353 7354 9.4.2.3 Relocatable Expression Modifiers 7355 ........................................ 7356 7357 The assembler supports several modifiers when using relocatable 7358 addresses in AVR instruction operands. The general syntax is the 7359 following: 7360 7361 modifier(relocatable-expression) 7362 7363 `lo8' 7364 This modifier allows you to use bits 0 through 7 of an address 7365 expression as 8 bit relocatable expression. 7366 7367 `hi8' 7368 This modifier allows you to use bits 7 through 15 of an address 7369 expression as 8 bit relocatable expression. This is useful with, 7370 for example, the AVR `ldi' instruction and `lo8' modifier. 7371 7372 For example 7373 7374 ldi r26, lo8(sym+10) 7375 ldi r27, hi8(sym+10) 7376 7377 `hh8' 7378 This modifier allows you to use bits 16 through 23 of an address 7379 expression as 8 bit relocatable expression. Also, can be useful 7380 for loading 32 bit constants. 7381 7382 `hlo8' 7383 Synonym of `hh8'. 7384 7385 `hhi8' 7386 This modifier allows you to use bits 24 through 31 of an 7387 expression as 8 bit expression. This is useful with, for example, 7388 the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8', 7389 modifier. 7390 7391 For example 7392 7393 ldi r26, lo8(285774925) 7394 ldi r27, hi8(285774925) 7395 ldi r28, hlo8(285774925) 7396 ldi r29, hhi8(285774925) 7397 ; r29,r28,r27,r26 = 285774925 7398 7399 `pm_lo8' 7400 This modifier allows you to use bits 0 through 7 of an address 7401 expression as 8 bit relocatable expression. This modifier useful 7402 for addressing data or code from Flash/Program memory. The using 7403 of `pm_lo8' similar to `lo8'. 7404 7405 `pm_hi8' 7406 This modifier allows you to use bits 8 through 15 of an address 7407 expression as 8 bit relocatable expression. This modifier useful 7408 for addressing data or code from Flash/Program memory. 7409 7410 `pm_hh8' 7411 This modifier allows you to use bits 15 through 23 of an address 7412 expression as 8 bit relocatable expression. This modifier useful 7413 for addressing data or code from Flash/Program memory. 7414 7415 7416 7417 File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent 7418 7419 9.4.3 Opcodes 7420 ------------- 7421 7422 For detailed information on the AVR machine instruction set, see 7423 `www.atmel.com/products/AVR'. 7424 7425 `as' implements all the standard AVR opcodes. The following table 7426 summarizes the AVR opcodes, and their arguments. 7427 7428 Legend: 7429 r any register 7430 d `ldi' register (r16-r31) 7431 v `movw' even register (r0, r2, ..., r28, r30) 7432 a `fmul' register (r16-r23) 7433 w `adiw' register (r24,r26,r28,r30) 7434 e pointer registers (X,Y,Z) 7435 b base pointer register and displacement ([YZ]+disp) 7436 z Z pointer register (for [e]lpm Rd,Z[+]) 7437 M immediate value from 0 to 255 7438 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 7439 s immediate value from 0 to 7 7440 P Port address value from 0 to 63. (in, out) 7441 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 7442 K immediate value from 0 to 63 (used in `adiw', `sbiw') 7443 i immediate value 7444 l signed pc relative offset from -64 to 63 7445 L signed pc relative offset from -2048 to 2047 7446 h absolute code address (call, jmp) 7447 S immediate value from 0 to 7 (S = s << 4) 7448 ? use this opcode entry if no parameters, else use next opcode entry 7449 7450 1001010010001000 clc 7451 1001010011011000 clh 7452 1001010011111000 cli 7453 1001010010101000 cln 7454 1001010011001000 cls 7455 1001010011101000 clt 7456 1001010010111000 clv 7457 1001010010011000 clz 7458 1001010000001000 sec 7459 1001010001011000 seh 7460 1001010001111000 sei 7461 1001010000101000 sen 7462 1001010001001000 ses 7463 1001010001101000 set 7464 1001010000111000 sev 7465 1001010000011000 sez 7466 100101001SSS1000 bclr S 7467 100101000SSS1000 bset S 7468 1001010100001001 icall 7469 1001010000001001 ijmp 7470 1001010111001000 lpm ? 7471 1001000ddddd010+ lpm r,z 7472 1001010111011000 elpm ? 7473 1001000ddddd011+ elpm r,z 7474 0000000000000000 nop 7475 1001010100001000 ret 7476 1001010100011000 reti 7477 1001010110001000 sleep 7478 1001010110011000 break 7479 1001010110101000 wdr 7480 1001010111101000 spm 7481 000111rdddddrrrr adc r,r 7482 000011rdddddrrrr add r,r 7483 001000rdddddrrrr and r,r 7484 000101rdddddrrrr cp r,r 7485 000001rdddddrrrr cpc r,r 7486 000100rdddddrrrr cpse r,r 7487 001001rdddddrrrr eor r,r 7488 001011rdddddrrrr mov r,r 7489 100111rdddddrrrr mul r,r 7490 001010rdddddrrrr or r,r 7491 000010rdddddrrrr sbc r,r 7492 000110rdddddrrrr sub r,r 7493 001001rdddddrrrr clr r 7494 000011rdddddrrrr lsl r 7495 000111rdddddrrrr rol r 7496 001000rdddddrrrr tst r 7497 0111KKKKddddKKKK andi d,M 7498 0111KKKKddddKKKK cbr d,n 7499 1110KKKKddddKKKK ldi d,M 7500 11101111dddd1111 ser d 7501 0110KKKKddddKKKK ori d,M 7502 0110KKKKddddKKKK sbr d,M 7503 0011KKKKddddKKKK cpi d,M 7504 0100KKKKddddKKKK sbci d,M 7505 0101KKKKddddKKKK subi d,M 7506 1111110rrrrr0sss sbrc r,s 7507 1111111rrrrr0sss sbrs r,s 7508 1111100ddddd0sss bld r,s 7509 1111101ddddd0sss bst r,s 7510 10110PPdddddPPPP in r,P 7511 10111PPrrrrrPPPP out P,r 7512 10010110KKddKKKK adiw w,K 7513 10010111KKddKKKK sbiw w,K 7514 10011000pppppsss cbi p,s 7515 10011010pppppsss sbi p,s 7516 10011001pppppsss sbic p,s 7517 10011011pppppsss sbis p,s 7518 111101lllllll000 brcc l 7519 111100lllllll000 brcs l 7520 111100lllllll001 breq l 7521 111101lllllll100 brge l 7522 111101lllllll101 brhc l 7523 111100lllllll101 brhs l 7524 111101lllllll111 brid l 7525 111100lllllll111 brie l 7526 111100lllllll000 brlo l 7527 111100lllllll100 brlt l 7528 111100lllllll010 brmi l 7529 111101lllllll001 brne l 7530 111101lllllll010 brpl l 7531 111101lllllll000 brsh l 7532 111101lllllll110 brtc l 7533 111100lllllll110 brts l 7534 111101lllllll011 brvc l 7535 111100lllllll011 brvs l 7536 111101lllllllsss brbc s,l 7537 111100lllllllsss brbs s,l 7538 1101LLLLLLLLLLLL rcall L 7539 1100LLLLLLLLLLLL rjmp L 7540 1001010hhhhh111h call h 7541 1001010hhhhh110h jmp h 7542 1001010rrrrr0101 asr r 7543 1001010rrrrr0000 com r 7544 1001010rrrrr1010 dec r 7545 1001010rrrrr0011 inc r 7546 1001010rrrrr0110 lsr r 7547 1001010rrrrr0001 neg r 7548 1001000rrrrr1111 pop r 7549 1001001rrrrr1111 push r 7550 1001010rrrrr0111 ror r 7551 1001010rrrrr0010 swap r 7552 00000001ddddrrrr movw v,v 7553 00000010ddddrrrr muls d,d 7554 000000110ddd0rrr mulsu a,a 7555 000000110ddd1rrr fmul a,a 7556 000000111ddd0rrr fmuls a,a 7557 000000111ddd1rrr fmulsu a,a 7558 1001001ddddd0000 sts i,r 7559 1001000ddddd0000 lds r,i 7560 10o0oo0dddddbooo ldd r,b 7561 100!000dddddee-+ ld r,e 7562 10o0oo1rrrrrbooo std b,r 7563 100!001rrrrree-+ st e,r 7564 1001010100011001 eicall 7565 1001010000011001 eijmp 7566 7567 7568 File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 7569 7570 9.5 Blackfin Dependent Features 7571 =============================== 7572 7573 * Menu: 7574 7575 * Blackfin Options:: Blackfin Options 7576 * Blackfin Syntax:: Blackfin Syntax 7577 * Blackfin Directives:: Blackfin Directives 7578 7579 7580 File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 7581 7582 9.5.1 Options 7583 ------------- 7584 7585 `-mcpu=PROCESSOR[-SIREVISION]' 7586 This option specifies the target processor. The optional 7587 SIREVISION is not used in assembler. It's here such that GCC can 7588 easily pass down its `-mcpu=' option. The assembler will issue an 7589 error message if an attempt is made to assemble an instruction 7590 which will not execute on the target processor. The following 7591 processor names are recognized: `bf504', `bf506', `bf512', `bf514', 7592 `bf516', `bf518', `bf522', `bf523', `bf524', `bf525', `bf526', 7593 `bf527', `bf531', `bf532', `bf533', `bf534', `bf535' (not 7594 implemented yet), `bf536', `bf537', `bf538', `bf539', `bf542', 7595 `bf542m', `bf544', `bf544m', `bf547', `bf547m', `bf548', `bf548m', 7596 `bf549', `bf549m', `bf561', and `bf592'. 7597 7598 `-mfdpic' 7599 Assemble for the FDPIC ABI. 7600 7601 `-mno-fdpic' 7602 `-mnopic' 7603 Disable -mfdpic. 7604 7605 7606 File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 7607 7608 9.5.2 Syntax 7609 ------------ 7610 7611 `Special Characters' 7612 Assembler input is free format and may appear anywhere on the line. 7613 One instruction may extend across multiple lines or more than one 7614 instruction may appear on the same line. White space (space, tab, 7615 comments or newline) may appear anywhere between tokens. A token 7616 must not have embedded spaces. Tokens include numbers, register 7617 names, keywords, user identifiers, and also some multicharacter 7618 special symbols like "+=", "/*" or "||". 7619 7620 `Instruction Delimiting' 7621 A semicolon must terminate every instruction. Sometimes a complete 7622 instruction will consist of more than one operation. There are two 7623 cases where this occurs. The first is when two general operations 7624 are combined. Normally a comma separates the different parts, as 7625 in 7626 7627 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 7628 7629 The second case occurs when a general instruction is combined with 7630 one or two memory references for joint issue. The latter portions 7631 are set off by a "||" token. 7632 7633 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 7634 7635 `Register Names' 7636 The assembler treats register names and instruction keywords in a 7637 case insensitive manner. User identifiers are case sensitive. 7638 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 7639 assembler. 7640 7641 Register names are reserved and may not be used as program 7642 identifiers. 7643 7644 Some operations (such as "Move Register") require a register pair. 7645 Register pairs are always data registers and are denoted using a 7646 colon, eg., R3:2. The larger number must be written firsts. Note 7647 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 7648 R3:2, and R1:0. 7649 7650 Some instructions (such as -SP (Push Multiple)) require a group of 7651 adjacent registers. Adjacent registers are denoted in the syntax 7652 by the range enclosed in parentheses and separated by a colon, 7653 eg., (R7:3). Again, the larger number appears first. 7654 7655 Portions of a particular register may be individually specified. 7656 This is written with a dot (".") following the register name and 7657 then a letter denoting the desired portion. For 32-bit registers, 7658 ".H" denotes the most significant ("High") portion. ".L" denotes 7659 the least-significant portion. The subdivisions of the 40-bit 7660 registers are described later. 7661 7662 `Accumulators' 7663 The set of 40-bit registers A1 and A0 that normally contain data 7664 that is being manipulated. Each accumulator can be accessed in 7665 four ways. 7666 7667 `one 40-bit register' 7668 The register will be referred to as A1 or A0. 7669 7670 `one 32-bit register' 7671 The registers are designated as A1.W or A0.W. 7672 7673 `two 16-bit registers' 7674 The registers are designated as A1.H, A1.L, A0.H or A0.L. 7675 7676 `one 8-bit register' 7677 The registers are designated as A1.X or A0.X for the bits that 7678 extend beyond bit 31. 7679 7680 `Data Registers' 7681 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 7682 that normally contain data for manipulation. These are 7683 abbreviated as D-register or Dreg. Data registers can be accessed 7684 as 32-bit registers or as two independent 16-bit registers. The 7685 least significant 16 bits of each register is called the "low" 7686 half and is designated with ".L" following the register name. The 7687 most significant 16 bits are called the "high" half and is 7688 designated with ".H" following the name. 7689 7690 R7.L, r2.h, r4.L, R0.H 7691 7692 `Pointer Registers' 7693 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 7694 that normally contain byte addresses of data structures. These are 7695 abbreviated as P-register or Preg. 7696 7697 p2, p5, fp, sp 7698 7699 `Stack Pointer SP' 7700 The stack pointer contains the 32-bit address of the last occupied 7701 byte location in the stack. The stack grows by decrementing the 7702 stack pointer. 7703 7704 `Frame Pointer FP' 7705 The frame pointer contains the 32-bit address of the previous frame 7706 pointer in the stack. It is located at the top of a frame. 7707 7708 `Loop Top' 7709 LT0 and LT1. These registers contain the 32-bit address of the 7710 top of a zero overhead loop. 7711 7712 `Loop Count' 7713 LC0 and LC1. These registers contain the 32-bit counter of the 7714 zero overhead loop executions. 7715 7716 `Loop Bottom' 7717 LB0 and LB1. These registers contain the 32-bit address of the 7718 bottom of a zero overhead loop. 7719 7720 `Index Registers' 7721 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 7722 byte addresses of data structures. Abbreviated I-register or Ireg. 7723 7724 `Modify Registers' 7725 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 7726 offset values that are added and subracted to one of the index 7727 registers. Abbreviated as Mreg. 7728 7729 `Length Registers' 7730 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 7731 the length in bytes of the circular buffer. Abbreviated as Lreg. 7732 Clear the Lreg to disable circular addressing for the 7733 corresponding Ireg. 7734 7735 `Base Registers' 7736 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 7737 the base address in bytes of the circular buffer. Abbreviated as 7738 Breg. 7739 7740 `Floating Point' 7741 The Blackfin family has no hardware floating point but the .float 7742 directive generates ieee floating point numbers for use with 7743 software floating point libraries. 7744 7745 `Blackfin Opcodes' 7746 For detailed information on the Blackfin machine instruction set, 7747 see the Blackfin(r) Processor Instruction Set Reference. 7748 7749 7750 7751 File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 7752 7753 9.5.3 Directives 7754 ---------------- 7755 7756 The following directives are provided for compatibility with the VDSP 7757 assembler. 7758 7759 `.byte2' 7760 Initializes a four byte data object. 7761 7762 `.byte4' 7763 Initializes a two byte data object. 7764 7765 `.db' 7766 TBD 7767 7768 `.dd' 7769 TBD 7770 7771 `.dw' 7772 TBD 7773 7774 `.var' 7775 Define and initialize a 32 bit data object. 7776 7777 7778 File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 7779 7780 9.6 CR16 Dependent Features 7781 =========================== 7782 7783 * Menu: 7784 7785 * CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 7786 7787 7788 File: as.info, Node: CR16 Operand Qualifiers, Up: CR16-Dependent 7789 7790 9.6.1 CR16 Operand Qualifiers 7791 ----------------------------- 7792 7793 The National Semiconductor CR16 target of `as' has a few machine 7794 dependent operand qualifiers. 7795 7796 Operand expression type qualifier is an optional field in the 7797 instruction operand, to determines the type of the expression field of 7798 an operand. The `@' is required. CR16 architecture uses one of the 7799 following expression qualifiers: 7800 7801 `s' 7802 - `Specifies expression operand type as small' 7803 7804 `m' 7805 - `Specifies expression operand type as medium' 7806 7807 `l' 7808 - `Specifies expression operand type as large' 7809 7810 `c' 7811 - `Specifies the CR16 Assembler generates a relocation entry for 7812 the operand, where pc has implied bit, the expression is adjusted 7813 accordingly. The linker uses the relocation entry to update the 7814 operand address at link time.' 7815 7816 `got/GOT' 7817 - `Specifies the CR16 Assembler generates a relocation entry for 7818 the operand, offset from Global Offset Table. The linker uses this 7819 relocation entry to update the operand address at link time' 7820 7821 `cgot/cGOT' 7822 - `Specifies the CompactRISC Assembler generates a relocation 7823 entry for the operand, where pc has implied bit, the expression is 7824 adjusted accordingly. The linker uses the relocation entry to 7825 update the operand address at link time.' 7826 7827 CR16 target operand qualifiers and its size (in bits): 7828 7829 `Immediate Operand' 7830 - s --- 4 bits 7831 7832 `' 7833 - m --- 16 bits, for movb and movw instructions. 7834 7835 `' 7836 - m --- 20 bits, movd instructions. 7837 7838 `' 7839 - l --- 32 bits 7840 7841 `Absolute Operand' 7842 - s --- Illegal specifier for this operand. 7843 7844 `' 7845 - m --- 20 bits, movd instructions. 7846 7847 `Displacement Operand' 7848 - s --- 8 bits 7849 7850 `' 7851 - m --- 16 bits 7852 7853 `' 7854 - l --- 24 bits 7855 7856 For example: 7857 1 `movw $_myfun@c,r1' 7858 7859 This loads the address of _myfun, shifted right by 1, into r1. 7860 7861 2 `movd $_myfun@c,(r2,r1)' 7862 7863 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 7864 7865 3 `_myfun_ptr:' 7866 `.long _myfun@c' 7867 `loadd _myfun_ptr, (r1,r0)' 7868 `jal (r1,r0)' 7869 7870 This .long directive, the address of _myfunc, shifted right by 1 at link time. 7871 7872 4 `loadd _data1@GOT(r12), (r1,r0)' 7873 7874 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 7875 7876 5 `loadd _myfunc@cGOT(r12), (r1,r0)' 7877 7878 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 7879 7880 7881 File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 7882 7883 9.7 CRIS Dependent Features 7884 =========================== 7885 7886 * Menu: 7887 7888 * CRIS-Opts:: Command-line Options 7889 * CRIS-Expand:: Instruction expansion 7890 * CRIS-Symbols:: Symbols 7891 * CRIS-Syntax:: Syntax 7892 7893 7894 File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 7895 7896 9.7.1 Command-line Options 7897 -------------------------- 7898 7899 The CRIS version of `as' has these machine-dependent command-line 7900 options. 7901 7902 The format of the generated object files can be either ELF or a.out, 7903 specified by the command-line options `--emulation=crisaout' and 7904 `--emulation=criself'. The default is ELF (criself), unless `as' has 7905 been configured specifically for a.out by using the configuration name 7906 `cris-axis-aout'. 7907 7908 There are two different link-incompatible ELF object file variants 7909 for CRIS, for use in environments where symbols are expected to be 7910 prefixed by a leading `_' character and for environments without such a 7911 symbol prefix. The variant used for GNU/Linux port has no symbol 7912 prefix. Which variant to produce is specified by either of the options 7913 `--underscore' and `--no-underscore'. The default is `--underscore'. 7914 Since symbols in CRIS a.out objects are expected to have a `_' prefix, 7915 specifying `--no-underscore' when generating a.out objects is an error. 7916 Besides the object format difference, the effect of this option is to 7917 parse register names differently (*note crisnous::). The 7918 `--no-underscore' option makes a `$' register prefix mandatory. 7919 7920 The option `--pic' must be passed to `as' in order to recognize the 7921 symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 7922 crispic::). This will also affect expansion of instructions. The 7923 expansion with `--pic' will use PC-relative rather than (slightly 7924 faster) absolute addresses in those expansions. 7925 7926 The option `--march=ARCHITECTURE' specifies the recognized 7927 instruction set and recognized register names. It also controls the 7928 architecture type of the object file. Valid values for ARCHITECTURE 7929 are: 7930 `v0_v10' 7931 All instructions and register names for any architecture variant 7932 in the set v0...v10 are recognized. This is the default if the 7933 target is configured as cris-*. 7934 7935 `v10' 7936 Only instructions and register names for CRIS v10 (as found in 7937 ETRAX 100 LX) are recognized. This is the default if the target 7938 is configured as crisv10-*. 7939 7940 `v32' 7941 Only instructions and register names for CRIS v32 (code name 7942 Guinness) are recognized. This is the default if the target is 7943 configured as crisv32-*. This value implies `--no-mul-bug-abort'. 7944 (A subsequent `--mul-bug-abort' will turn it back on.) 7945 7946 `common_v10_v32' 7947 Only instructions with register names and addressing modes with 7948 opcodes common to the v10 and v32 are recognized. 7949 7950 When `-N' is specified, `as' will emit a warning when a 16-bit 7951 branch instruction is expanded into a 32-bit multiple-instruction 7952 construct (*note CRIS-Expand::). 7953 7954 Some versions of the CRIS v10, for example in the Etrax 100 LX, 7955 contain a bug that causes destabilizing memory accesses when a multiply 7956 instruction is executed with certain values in the first operand just 7957 before a cache-miss. When the `--mul-bug-abort' command line option is 7958 active (the default value), `as' will refuse to assemble a file 7959 containing a multiply instruction at a dangerous offset, one that could 7960 be the last on a cache-line, or is in a section with insufficient 7961 alignment. This placement checking does not catch any case where the 7962 multiply instruction is dangerously placed because it is located in a 7963 delay-slot. The `--mul-bug-abort' command line option turns off the 7964 checking. 7965 7966 7967 File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 7968 7969 9.7.2 Instruction expansion 7970 --------------------------- 7971 7972 `as' will silently choose an instruction that fits the operand size for 7973 `[register+constant]' operands. For example, the offset `127' in 7974 `move.d [r3+127],r4' fits in an instruction using a signed-byte offset. 7975 Similarly, `move.d [r2+32767],r1' will generate an instruction using a 7976 16-bit offset. For symbolic expressions and constants that do not fit 7977 in 16 bits including the sign bit, a 32-bit offset is generated. 7978 7979 For branches, `as' will expand from a 16-bit branch instruction into 7980 a sequence of instructions that can reach a full 32-bit address. Since 7981 this does not correspond to a single instruction, such expansions can 7982 optionally be warned about. *Note CRIS-Opts::. 7983 7984 If the operand is found to fit the range, a `lapc' mnemonic will 7985 translate to a `lapcq' instruction. Use `lapc.d' to force the 32-bit 7986 `lapc' instruction. 7987 7988 Similarly, the `addo' mnemonic will translate to the shortest 7989 fitting instruction of `addoq', `addo.w' and `addo.d', when used with a 7990 operand that is a constant known at assembly time. 7991 7992 7993 File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 7994 7995 9.7.3 Symbols 7996 ------------- 7997 7998 Some symbols are defined by the assembler. They're intended to be used 7999 in conditional assembly, for example: 8000 .if ..asm.arch.cris.v32 8001 CODE FOR CRIS V32 8002 .elseif ..asm.arch.cris.common_v10_v32 8003 CODE COMMON TO CRIS V32 AND CRIS V10 8004 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 8005 CODE FOR V10 8006 .else 8007 .error "Code needs to be added here." 8008 .endif 8009 8010 These symbols are defined in the assembler, reflecting command-line 8011 options, either when specified or the default. They are always 8012 defined, to 0 or 1. 8013 `..asm.arch.cris.any_v0_v10' 8014 This symbol is non-zero when `--march=v0_v10' is specified or the 8015 default. 8016 8017 `..asm.arch.cris.common_v10_v32' 8018 Set according to the option `--march=common_v10_v32'. 8019 8020 `..asm.arch.cris.v10' 8021 Reflects the option `--march=v10'. 8022 8023 `..asm.arch.cris.v32' 8024 Corresponds to `--march=v10'. 8025 8026 Speaking of symbols, when a symbol is used in code, it can have a 8027 suffix modifying its value for use in position-independent code. *Note 8028 CRIS-Pic::. 8029 8030 8031 File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 8032 8033 9.7.4 Syntax 8034 ------------ 8035 8036 There are different aspects of the CRIS assembly syntax. 8037 8038 * Menu: 8039 8040 * CRIS-Chars:: Special Characters 8041 * CRIS-Pic:: Position-Independent Code Symbols 8042 * CRIS-Regs:: Register Names 8043 * CRIS-Pseudos:: Assembler Directives 8044 8045 8046 File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 8047 8048 9.7.4.1 Special Characters 8049 .......................... 8050 8051 The character `#' is a line comment character. It starts a comment if 8052 and only if it is placed at the beginning of a line. 8053 8054 A `;' character starts a comment anywhere on the line, causing all 8055 characters up to the end of the line to be ignored. 8056 8057 A `@' character is handled as a line separator equivalent to a 8058 logical new-line character (except in a comment), so separate 8059 instructions can be specified on a single line. 8060 8061 8062 File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 8063 8064 9.7.4.2 Symbols in position-independent code 8065 ............................................ 8066 8067 When generating position-independent code (SVR4 PIC) for use in 8068 cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 8069 suffixes are used to specify what kind of run-time symbol lookup will 8070 be used, expressed in the object as different _relocation types_. 8071 Usually, all absolute symbol values must be located in a table, the 8072 _global offset table_, leaving the code position-independent; 8073 independent of values of global symbols and independent of the address 8074 of the code. The suffix modifies the value of the symbol, into for 8075 example an index into the global offset table where the real symbol 8076 value is entered, or a PC-relative value, or a value relative to the 8077 start of the global offset table. All symbol suffixes start with the 8078 character `:' (omitted in the list below). Every symbol use in code or 8079 a read-only section must therefore have a PIC suffix to enable a useful 8080 shared library to be created. Usually, these constructs must not be 8081 used with an additive constant offset as is usually allowed, i.e. no 4 8082 as in `symbol + 4' is allowed. This restriction is checked at 8083 link-time, not at assembly-time. 8084 8085 `GOT' 8086 Attaching this suffix to a symbol in an instruction causes the 8087 symbol to be entered into the global offset table. The value is a 8088 32-bit index for that symbol into the global offset table. The 8089 name of the corresponding relocation is `R_CRIS_32_GOT'. Example: 8090 `move.d [$r0+extsym:GOT],$r9' 8091 8092 `GOT16' 8093 Same as for `GOT', but the value is a 16-bit index into the global 8094 offset table. The corresponding relocation is `R_CRIS_16_GOT'. 8095 Example: `move.d [$r0+asymbol:GOT16],$r10' 8096 8097 `PLT' 8098 This suffix is used for function symbols. It causes a _procedure 8099 linkage table_, an array of code stubs, to be created at the time 8100 the shared object is created or linked against, together with a 8101 global offset table entry. The value is a pc-relative offset to 8102 the corresponding stub code in the procedure linkage table. This 8103 arrangement causes the run-time symbol resolver to be called to 8104 look up and set the value of the symbol the first time the 8105 function is called (at latest; depending environment variables). 8106 It is only safe to leave the symbol unresolved this way if all 8107 references are function calls. The name of the relocation is 8108 `R_CRIS_32_PLT_PCREL'. Example: `add.d fnname:PLT,$pc' 8109 8110 `PLTG' 8111 Like PLT, but the value is relative to the beginning of the global 8112 offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example: 8113 `move.d fnname:PLTG,$r3' 8114 8115 `GOTPLT' 8116 Similar to `PLT', but the value of the symbol is a 32-bit index 8117 into the global offset table. This is somewhat of a mix between 8118 the effect of the `GOT' and the `PLT' suffix; the difference to 8119 `GOT' is that there will be a procedure linkage table entry 8120 created, and that the symbol is assumed to be a function entry and 8121 will be resolved by the run-time resolver as with `PLT'. The 8122 relocation is `R_CRIS_32_GOTPLT'. Example: `jsr 8123 [$r0+fnname:GOTPLT]' 8124 8125 `GOTPLT16' 8126 A variant of `GOTPLT' giving a 16-bit value. Its relocation name 8127 is `R_CRIS_16_GOTPLT'. Example: `jsr [$r0+fnname:GOTPLT16]' 8128 8129 `GOTOFF' 8130 This suffix must only be attached to a local symbol, but may be 8131 used in an expression adding an offset. The value is the address 8132 of the symbol relative to the start of the global offset table. 8133 The relocation name is `R_CRIS_32_GOTREL'. Example: `move.d 8134 [$r0+localsym:GOTOFF],r3' 8135 8136 8137 File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 8138 8139 9.7.4.3 Register names 8140 ...................... 8141 8142 A `$' character may always prefix a general or special register name in 8143 an instruction operand but is mandatory when the option 8144 `--no-underscore' is specified or when the `.syntax register_prefix' 8145 directive is in effect (*note crisnous::). Register names are 8146 case-insensitive. 8147 8148 8149 File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 8150 8151 9.7.4.4 Assembler Directives 8152 ............................ 8153 8154 There are a few CRIS-specific pseudo-directives in addition to the 8155 generic ones. *Note Pseudo Ops::. Constants emitted by 8156 pseudo-directives are in little-endian order for CRIS. There is no 8157 support for floating-point-specific directives for CRIS. 8158 8159 `.dword EXPRESSIONS' 8160 The `.dword' directive is a synonym for `.int', expecting zero or 8161 more EXPRESSIONS, separated by commas. For each expression, a 8162 32-bit little-endian constant is emitted. 8163 8164 `.syntax ARGUMENT' 8165 The `.syntax' directive takes as ARGUMENT one of the following 8166 case-sensitive choices. 8167 8168 `no_register_prefix' 8169 The `.syntax no_register_prefix' directive makes a `$' 8170 character prefix on all registers optional. It overrides a 8171 previous setting, including the corresponding effect of the 8172 option `--no-underscore'. If this directive is used when 8173 ordinary symbols do not have a `_' character prefix, care 8174 must be taken to avoid ambiguities whether an operand is a 8175 register or a symbol; using symbols with names the same as 8176 general or special registers then invoke undefined behavior. 8177 8178 `register_prefix' 8179 This directive makes a `$' character prefix on all registers 8180 mandatory. It overrides a previous setting, including the 8181 corresponding effect of the option `--underscore'. 8182 8183 `leading_underscore' 8184 This is an assertion directive, emitting an error if the 8185 `--no-underscore' option is in effect. 8186 8187 `no_leading_underscore' 8188 This is the opposite of the `.syntax leading_underscore' 8189 directive and emits an error if the option `--underscore' is 8190 in effect. 8191 8192 `.arch ARGUMENT' 8193 This is an assertion directive, giving an error if the specified 8194 ARGUMENT is not the same as the specified or default value for the 8195 `--march=ARCHITECTURE' option (*note march-option::). 8196 8197 8198 8199 File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 8200 8201 9.8 D10V Dependent Features 8202 =========================== 8203 8204 * Menu: 8205 8206 * D10V-Opts:: D10V Options 8207 * D10V-Syntax:: Syntax 8208 * D10V-Float:: Floating Point 8209 * D10V-Opcodes:: Opcodes 8210 8211 8212 File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 8213 8214 9.8.1 D10V Options 8215 ------------------ 8216 8217 The Mitsubishi D10V version of `as' has a few machine dependent options. 8218 8219 `-O' 8220 The D10V can often execute two sub-instructions in parallel. When 8221 this option is used, `as' will attempt to optimize its output by 8222 detecting when instructions can be executed in parallel. 8223 8224 `--nowarnswap' 8225 To optimize execution performance, `as' will sometimes swap the 8226 order of instructions. Normally this generates a warning. When 8227 this option is used, no warning will be generated when 8228 instructions are swapped. 8229 8230 `--gstabs-packing' 8231 `--no-gstabs-packing' 8232 `as' packs adjacent short instructions into a single packed 8233 instruction. `--no-gstabs-packing' turns instruction packing off if 8234 `--gstabs' is specified as well; `--gstabs-packing' (the default) 8235 turns instruction packing on even when `--gstabs' is specified. 8236 8237 8238 File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 8239 8240 9.8.2 Syntax 8241 ------------ 8242 8243 The D10V syntax is based on the syntax in Mitsubishi's D10V 8244 architecture manual. The differences are detailed below. 8245 8246 * Menu: 8247 8248 * D10V-Size:: Size Modifiers 8249 * D10V-Subs:: Sub-Instructions 8250 * D10V-Chars:: Special Characters 8251 * D10V-Regs:: Register Names 8252 * D10V-Addressing:: Addressing Modes 8253 * D10V-Word:: @WORD Modifier 8254 8255 8256 File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 8257 8258 9.8.2.1 Size Modifiers 8259 ...................... 8260 8261 The D10V version of `as' uses the instruction names in the D10V 8262 Architecture Manual. However, the names in the manual are sometimes 8263 ambiguous. There are instruction names that can assemble to a short or 8264 long form opcode. How does the assembler pick the correct form? `as' 8265 will always pick the smallest form if it can. When dealing with a 8266 symbol that is not defined yet when a line is being assembled, it will 8267 always use the long form. If you need to force the assembler to use 8268 either the short or long form of the instruction, you can append either 8269 `.s' (short) or `.l' (long) to it. For example, if you are writing an 8270 assembly program and you want to do a branch to a symbol that is 8271 defined later in your program, you can write `bra.s foo'. Objdump 8272 and GDB will always append `.s' or `.l' to instructions which have both 8273 short and long forms. 8274 8275 8276 File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 8277 8278 9.8.2.2 Sub-Instructions 8279 ........................ 8280 8281 The D10V assembler takes as input a series of instructions, either 8282 one-per-line, or in the special two-per-line format described in the 8283 next section. Some of these instructions will be short-form or 8284 sub-instructions. These sub-instructions can be packed into a single 8285 instruction. The assembler will do this automatically. It will also 8286 detect when it should not pack instructions. For example, when a label 8287 is defined, the next instruction will never be packaged with the 8288 previous one. Whenever a branch and link instruction is called, it 8289 will not be packaged with the next instruction so the return address 8290 will be valid. Nops are automatically inserted when necessary. 8291 8292 If you do not want the assembler automatically making these 8293 decisions, you can control the packaging and execution type (parallel 8294 or sequential) with the special execution symbols described in the next 8295 section. 8296 8297 8298 File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 8299 8300 9.8.2.3 Special Characters 8301 .......................... 8302 8303 `;' and `#' are the line comment characters. Sub-instructions may be 8304 executed in order, in reverse-order, or in parallel. Instructions 8305 listed in the standard one-per-line format will be executed 8306 sequentially. To specify the executing order, use the following 8307 symbols: 8308 `->' 8309 Sequential with instruction on the left first. 8310 8311 `<-' 8312 Sequential with instruction on the right first. 8313 8314 `||' 8315 Parallel 8316 The D10V syntax allows either one instruction per line, one 8317 instruction per line with the execution symbol, or two instructions per 8318 line. For example 8319 `abs a1 -> abs r0' 8320 Execute these sequentially. The instruction on the right is in 8321 the right container and is executed second. 8322 8323 `abs r0 <- abs a1' 8324 Execute these reverse-sequentially. The instruction on the right 8325 is in the right container, and is executed first. 8326 8327 `ld2w r2,@r8+ || mac a0,r0,r7' 8328 Execute these in parallel. 8329 8330 `ld2w r2,@r8+ ||' 8331 `mac a0,r0,r7' 8332 Two-line format. Execute these in parallel. 8333 8334 `ld2w r2,@r8+' 8335 `mac a0,r0,r7' 8336 Two-line format. Execute these sequentially. Assembler will put 8337 them in the proper containers. 8338 8339 `ld2w r2,@r8+ ->' 8340 `mac a0,r0,r7' 8341 Two-line format. Execute these sequentially. Same as above but 8342 second instruction will always go into right container. 8343 Since `$' has no special meaning, you may use it in symbol names. 8344 8345 8346 File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 8347 8348 9.8.2.4 Register Names 8349 ...................... 8350 8351 You can use the predefined symbols `r0' through `r15' to refer to the 8352 D10V registers. You can also use `sp' as an alias for `r15'. The 8353 accumulators are `a0' and `a1'. There are special register-pair names 8354 that may optionally be used in opcodes that require even-numbered 8355 registers. Register names are not case sensitive. 8356 8357 Register Pairs 8358 `r0-r1' 8359 8360 `r2-r3' 8361 8362 `r4-r5' 8363 8364 `r6-r7' 8365 8366 `r8-r9' 8367 8368 `r10-r11' 8369 8370 `r12-r13' 8371 8372 `r14-r15' 8373 8374 The D10V also has predefined symbols for these control registers and 8375 status bits: 8376 `psw' 8377 Processor Status Word 8378 8379 `bpsw' 8380 Backup Processor Status Word 8381 8382 `pc' 8383 Program Counter 8384 8385 `bpc' 8386 Backup Program Counter 8387 8388 `rpt_c' 8389 Repeat Count 8390 8391 `rpt_s' 8392 Repeat Start address 8393 8394 `rpt_e' 8395 Repeat End address 8396 8397 `mod_s' 8398 Modulo Start address 8399 8400 `mod_e' 8401 Modulo End address 8402 8403 `iba' 8404 Instruction Break Address 8405 8406 `f0' 8407 Flag 0 8408 8409 `f1' 8410 Flag 1 8411 8412 `c' 8413 Carry flag 8414 8415 8416 File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 8417 8418 9.8.2.5 Addressing Modes 8419 ........................ 8420 8421 `as' understands the following addressing modes for the D10V. `RN' in 8422 the following refers to any of the numbered registers, but _not_ the 8423 control registers. 8424 `RN' 8425 Register direct 8426 8427 `@RN' 8428 Register indirect 8429 8430 `@RN+' 8431 Register indirect with post-increment 8432 8433 `@RN-' 8434 Register indirect with post-decrement 8435 8436 `@-SP' 8437 Register indirect with pre-decrement 8438 8439 `@(DISP, RN)' 8440 Register indirect with displacement 8441 8442 `ADDR' 8443 PC relative address (for branch or rep). 8444 8445 `#IMM' 8446 Immediate data (the `#' is optional and ignored) 8447 8448 8449 File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 8450 8451 9.8.2.6 @WORD Modifier 8452 ...................... 8453 8454 Any symbol followed by `@word' will be replaced by the symbol's value 8455 shifted right by 2. This is used in situations such as loading a 8456 register with the address of a function (or any other code fragment). 8457 For example, if you want to load a register with the location of the 8458 function `main' then jump to that function, you could do it as follows: 8459 ldi r2, main@word 8460 jmp r2 8461 8462 8463 File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 8464 8465 9.8.3 Floating Point 8466 -------------------- 8467 8468 The D10V has no hardware floating point, but the `.float' and `.double' 8469 directives generates IEEE floating-point numbers for compatibility with 8470 other development tools. 8471 8472 8473 File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 8474 8475 9.8.4 Opcodes 8476 ------------- 8477 8478 For detailed information on the D10V machine instruction set, see `D10V 8479 Architecture: A VLIW Microprocessor for Multimedia Applications' 8480 (Mitsubishi Electric Corp.). `as' implements all the standard D10V 8481 opcodes. The only changes are those described in the section on size 8482 modifiers 8483 8484 8485 File: as.info, Node: D30V-Dependent, Next: H8/300-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 8486 8487 9.9 D30V Dependent Features 8488 =========================== 8489 8490 * Menu: 8491 8492 * D30V-Opts:: D30V Options 8493 * D30V-Syntax:: Syntax 8494 * D30V-Float:: Floating Point 8495 * D30V-Opcodes:: Opcodes 8496 8497 8498 File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 8499 8500 9.9.1 D30V Options 8501 ------------------ 8502 8503 The Mitsubishi D30V version of `as' has a few machine dependent options. 8504 8505 `-O' 8506 The D30V can often execute two sub-instructions in parallel. When 8507 this option is used, `as' will attempt to optimize its output by 8508 detecting when instructions can be executed in parallel. 8509 8510 `-n' 8511 When this option is used, `as' will issue a warning every time it 8512 adds a nop instruction. 8513 8514 `-N' 8515 When this option is used, `as' will issue a warning if it needs to 8516 insert a nop after a 32-bit multiply before a load or 16-bit 8517 multiply instruction. 8518 8519 8520 File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 8521 8522 9.9.2 Syntax 8523 ------------ 8524 8525 The D30V syntax is based on the syntax in Mitsubishi's D30V 8526 architecture manual. The differences are detailed below. 8527 8528 * Menu: 8529 8530 * D30V-Size:: Size Modifiers 8531 * D30V-Subs:: Sub-Instructions 8532 * D30V-Chars:: Special Characters 8533 * D30V-Guarded:: Guarded Execution 8534 * D30V-Regs:: Register Names 8535 * D30V-Addressing:: Addressing Modes 8536 8537 8538 File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 8539 8540 9.9.2.1 Size Modifiers 8541 ...................... 8542 8543 The D30V version of `as' uses the instruction names in the D30V 8544 Architecture Manual. However, the names in the manual are sometimes 8545 ambiguous. There are instruction names that can assemble to a short or 8546 long form opcode. How does the assembler pick the correct form? `as' 8547 will always pick the smallest form if it can. When dealing with a 8548 symbol that is not defined yet when a line is being assembled, it will 8549 always use the long form. If you need to force the assembler to use 8550 either the short or long form of the instruction, you can append either 8551 `.s' (short) or `.l' (long) to it. For example, if you are writing an 8552 assembly program and you want to do a branch to a symbol that is 8553 defined later in your program, you can write `bra.s foo'. Objdump and 8554 GDB will always append `.s' or `.l' to instructions which have both 8555 short and long forms. 8556 8557 8558 File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 8559 8560 9.9.2.2 Sub-Instructions 8561 ........................ 8562 8563 The D30V assembler takes as input a series of instructions, either 8564 one-per-line, or in the special two-per-line format described in the 8565 next section. Some of these instructions will be short-form or 8566 sub-instructions. These sub-instructions can be packed into a single 8567 instruction. The assembler will do this automatically. It will also 8568 detect when it should not pack instructions. For example, when a label 8569 is defined, the next instruction will never be packaged with the 8570 previous one. Whenever a branch and link instruction is called, it 8571 will not be packaged with the next instruction so the return address 8572 will be valid. Nops are automatically inserted when necessary. 8573 8574 If you do not want the assembler automatically making these 8575 decisions, you can control the packaging and execution type (parallel 8576 or sequential) with the special execution symbols described in the next 8577 section. 8578 8579 8580 File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 8581 8582 9.9.2.3 Special Characters 8583 .......................... 8584 8585 `;' and `#' are the line comment characters. Sub-instructions may be 8586 executed in order, in reverse-order, or in parallel. Instructions 8587 listed in the standard one-per-line format will be executed 8588 sequentially unless you use the `-O' option. 8589 8590 To specify the executing order, use the following symbols: 8591 `->' 8592 Sequential with instruction on the left first. 8593 8594 `<-' 8595 Sequential with instruction on the right first. 8596 8597 `||' 8598 Parallel 8599 8600 The D30V syntax allows either one instruction per line, one 8601 instruction per line with the execution symbol, or two instructions per 8602 line. For example 8603 `abs r2,r3 -> abs r4,r5' 8604 Execute these sequentially. The instruction on the right is in 8605 the right container and is executed second. 8606 8607 `abs r2,r3 <- abs r4,r5' 8608 Execute these reverse-sequentially. The instruction on the right 8609 is in the right container, and is executed first. 8610 8611 `abs r2,r3 || abs r4,r5' 8612 Execute these in parallel. 8613 8614 `ldw r2,@(r3,r4) ||' 8615 `mulx r6,r8,r9' 8616 Two-line format. Execute these in parallel. 8617 8618 `mulx a0,r8,r9' 8619 `stw r2,@(r3,r4)' 8620 Two-line format. Execute these sequentially unless `-O' option is 8621 used. If the `-O' option is used, the assembler will determine if 8622 the instructions could be done in parallel (the above two 8623 instructions can be done in parallel), and if so, emit them as 8624 parallel instructions. The assembler will put them in the proper 8625 containers. In the above example, the assembler will put the 8626 `stw' instruction in left container and the `mulx' instruction in 8627 the right container. 8628 8629 `stw r2,@(r3,r4) ->' 8630 `mulx a0,r8,r9' 8631 Two-line format. Execute the `stw' instruction followed by the 8632 `mulx' instruction sequentially. The first instruction goes in the 8633 left container and the second instruction goes into right 8634 container. The assembler will give an error if the machine 8635 ordering constraints are violated. 8636 8637 `stw r2,@(r3,r4) <-' 8638 `mulx a0,r8,r9' 8639 Same as previous example, except that the `mulx' instruction is 8640 executed before the `stw' instruction. 8641 8642 Since `$' has no special meaning, you may use it in symbol names. 8643 8644 8645 File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 8646 8647 9.9.2.4 Guarded Execution 8648 ......................... 8649 8650 `as' supports the full range of guarded execution directives for each 8651 instruction. Just append the directive after the instruction proper. 8652 The directives are: 8653 8654 `/tx' 8655 Execute the instruction if flag f0 is true. 8656 8657 `/fx' 8658 Execute the instruction if flag f0 is false. 8659 8660 `/xt' 8661 Execute the instruction if flag f1 is true. 8662 8663 `/xf' 8664 Execute the instruction if flag f1 is false. 8665 8666 `/tt' 8667 Execute the instruction if both flags f0 and f1 are true. 8668 8669 `/tf' 8670 Execute the instruction if flag f0 is true and flag f1 is false. 8671 8672 8673 File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 8674 8675 9.9.2.5 Register Names 8676 ...................... 8677 8678 You can use the predefined symbols `r0' through `r63' to refer to the 8679 D30V registers. You can also use `sp' as an alias for `r63' and `link' 8680 as an alias for `r62'. The accumulators are `a0' and `a1'. 8681 8682 The D30V also has predefined symbols for these control registers and 8683 status bits: 8684 `psw' 8685 Processor Status Word 8686 8687 `bpsw' 8688 Backup Processor Status Word 8689 8690 `pc' 8691 Program Counter 8692 8693 `bpc' 8694 Backup Program Counter 8695 8696 `rpt_c' 8697 Repeat Count 8698 8699 `rpt_s' 8700 Repeat Start address 8701 8702 `rpt_e' 8703 Repeat End address 8704 8705 `mod_s' 8706 Modulo Start address 8707 8708 `mod_e' 8709 Modulo End address 8710 8711 `iba' 8712 Instruction Break Address 8713 8714 `f0' 8715 Flag 0 8716 8717 `f1' 8718 Flag 1 8719 8720 `f2' 8721 Flag 2 8722 8723 `f3' 8724 Flag 3 8725 8726 `f4' 8727 Flag 4 8728 8729 `f5' 8730 Flag 5 8731 8732 `f6' 8733 Flag 6 8734 8735 `f7' 8736 Flag 7 8737 8738 `s' 8739 Same as flag 4 (saturation flag) 8740 8741 `v' 8742 Same as flag 5 (overflow flag) 8743 8744 `va' 8745 Same as flag 6 (sticky overflow flag) 8746 8747 `c' 8748 Same as flag 7 (carry/borrow flag) 8749 8750 `b' 8751 Same as flag 7 (carry/borrow flag) 8752 8753 8754 File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 8755 8756 9.9.2.6 Addressing Modes 8757 ........................ 8758 8759 `as' understands the following addressing modes for the D30V. `RN' in 8760 the following refers to any of the numbered registers, but _not_ the 8761 control registers. 8762 `RN' 8763 Register direct 8764 8765 `@RN' 8766 Register indirect 8767 8768 `@RN+' 8769 Register indirect with post-increment 8770 8771 `@RN-' 8772 Register indirect with post-decrement 8773 8774 `@-SP' 8775 Register indirect with pre-decrement 8776 8777 `@(DISP, RN)' 8778 Register indirect with displacement 8779 8780 `ADDR' 8781 PC relative address (for branch or rep). 8782 8783 `#IMM' 8784 Immediate data (the `#' is optional and ignored) 8785 8786 8787 File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 8788 8789 9.9.3 Floating Point 8790 -------------------- 8791 8792 The D30V has no hardware floating point, but the `.float' and `.double' 8793 directives generates IEEE floating-point numbers for compatibility with 8794 other development tools. 8795 8796 8797 File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 8798 8799 9.9.4 Opcodes 8800 ------------- 8801 8802 For detailed information on the D30V machine instruction set, see `D30V 8803 Architecture: A VLIW Microprocessor for Multimedia Applications' 8804 (Mitsubishi Electric Corp.). `as' implements all the standard D30V 8805 opcodes. The only changes are those described in the section on size 8806 modifiers 8807 8808 8809 File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 8810 8811 9.10 H8/300 Dependent Features 8812 ============================== 8813 8814 * Menu: 8815 8816 * H8/300 Options:: Options 8817 * H8/300 Syntax:: Syntax 8818 * H8/300 Floating Point:: Floating Point 8819 * H8/300 Directives:: H8/300 Machine Directives 8820 * H8/300 Opcodes:: Opcodes 8821 8822 8823 File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 8824 8825 9.10.1 Options 8826 -------------- 8827 8828 The Renesas H8/300 version of `as' has one machine-dependent option: 8829 8830 `-h-tick-hex' 8831 Support H'00 style hex constants in addition to 0x00 style. 8832 8833 8834 8835 File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 8836 8837 9.10.2 Syntax 8838 ------------- 8839 8840 * Menu: 8841 8842 * H8/300-Chars:: Special Characters 8843 * H8/300-Regs:: Register Names 8844 * H8/300-Addressing:: Addressing Modes 8845 8846 8847 File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 8848 8849 9.10.2.1 Special Characters 8850 ........................... 8851 8852 `;' is the line comment character. 8853 8854 `$' can be used instead of a newline to separate statements. 8855 Therefore _you may not use `$' in symbol names_ on the H8/300. 8856 8857 8858 File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 8859 8860 9.10.2.2 Register Names 8861 ....................... 8862 8863 You can use predefined symbols of the form `rNh' and `rNl' to refer to 8864 the H8/300 registers as sixteen 8-bit general-purpose registers. N is 8865 a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid 8866 register names. 8867 8868 You can also use the eight predefined symbols `rN' to refer to the 8869 H8/300 registers as 16-bit registers (you must use this form for 8870 addressing). 8871 8872 On the H8/300H, you can also use the eight predefined symbols `erN' 8873 (`er0' ... `er7') to refer to the 32-bit general purpose registers. 8874 8875 The two control registers are called `pc' (program counter; a 16-bit 8876 register, except on the H8/300H where it is 24 bits) and `ccr' 8877 (condition code register; an 8-bit register). `r7' is used as the 8878 stack pointer, and can also be called `sp'. 8879 8880 8881 File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 8882 8883 9.10.2.3 Addressing Modes 8884 ......................... 8885 8886 as understands the following addressing modes for the H8/300: 8887 `rN' 8888 Register direct 8889 8890 `@rN' 8891 Register indirect 8892 8893 `@(D, rN)' 8894 `@(D:16, rN)' 8895 `@(D:24, rN)' 8896 Register indirect: 16-bit or 24-bit displacement D from register 8897 N. (24-bit displacements are only meaningful on the H8/300H.) 8898 8899 `@rN+' 8900 Register indirect with post-increment 8901 8902 `@-rN' 8903 Register indirect with pre-decrement 8904 8905 ``@'AA' 8906 ``@'AA:8' 8907 ``@'AA:16' 8908 ``@'AA:24' 8909 Absolute address `aa'. (The address size `:24' only makes sense 8910 on the H8/300H.) 8911 8912 `#XX' 8913 `#XX:8' 8914 `#XX:16' 8915 `#XX:32' 8916 Immediate data XX. You may specify the `:8', `:16', or `:32' for 8917 clarity, if you wish; but `as' neither requires this nor uses 8918 it--the data size required is taken from context. 8919 8920 ``@'`@'AA' 8921 ``@'`@'AA:8' 8922 Memory indirect. You may specify the `:8' for clarity, if you 8923 wish; but `as' neither requires this nor uses it. 8924 8925 8926 File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 8927 8928 9.10.3 Floating Point 8929 --------------------- 8930 8931 The H8/300 family has no hardware floating point, but the `.float' 8932 directive generates IEEE floating-point numbers for compatibility with 8933 other development tools. 8934 8935 8936 File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 8937 8938 9.10.4 H8/300 Machine Directives 8939 -------------------------------- 8940 8941 `as' has the following machine-dependent directives for the H8/300: 8942 8943 `.h8300h' 8944 Recognize and emit additional instructions for the H8/300H 8945 variant, and also make `.int' emit 32-bit numbers rather than the 8946 usual (16-bit) for the H8/300 family. 8947 8948 `.h8300s' 8949 Recognize and emit additional instructions for the H8S variant, and 8950 also make `.int' emit 32-bit numbers rather than the usual (16-bit) 8951 for the H8/300 family. 8952 8953 `.h8300hn' 8954 Recognize and emit additional instructions for the H8/300H variant 8955 in normal mode, and also make `.int' emit 32-bit numbers rather 8956 than the usual (16-bit) for the H8/300 family. 8957 8958 `.h8300sn' 8959 Recognize and emit additional instructions for the H8S variant in 8960 normal mode, and also make `.int' emit 32-bit numbers rather than 8961 the usual (16-bit) for the H8/300 family. 8962 8963 On the H8/300 family (including the H8/300H) `.word' directives 8964 generate 16-bit numbers. 8965 8966 8967 File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 8968 8969 9.10.5 Opcodes 8970 -------------- 8971 8972 For detailed information on the H8/300 machine instruction set, see 8973 `H8/300 Series Programming Manual'. For information specific to the 8974 H8/300H, see `H8/300H Series Programming Manual' (Renesas). 8975 8976 `as' implements all the standard H8/300 opcodes. No additional 8977 pseudo-instructions are needed on this family. 8978 8979 The following table summarizes the H8/300 opcodes, and their 8980 arguments. Entries marked `*' are opcodes used only on the H8/300H. 8981 8982 Legend: 8983 Rs source register 8984 Rd destination register 8985 abs absolute address 8986 imm immediate data 8987 disp:N N-bit displacement from a register 8988 pcrel:N N-bit displacement relative to program counter 8989 8990 add.b #imm,rd * andc #imm,ccr 8991 add.b rs,rd band #imm,rd 8992 add.w rs,rd band #imm,@rd 8993 * add.w #imm,rd band #imm,@abs:8 8994 * add.l rs,rd bra pcrel:8 8995 * add.l #imm,rd * bra pcrel:16 8996 adds #imm,rd bt pcrel:8 8997 addx #imm,rd * bt pcrel:16 8998 addx rs,rd brn pcrel:8 8999 and.b #imm,rd * brn pcrel:16 9000 and.b rs,rd bf pcrel:8 9001 * and.w rs,rd * bf pcrel:16 9002 * and.w #imm,rd bhi pcrel:8 9003 * and.l #imm,rd * bhi pcrel:16 9004 * and.l rs,rd bls pcrel:8 9005 9006 * bls pcrel:16 bld #imm,rd 9007 bcc pcrel:8 bld #imm,@rd 9008 * bcc pcrel:16 bld #imm,@abs:8 9009 bhs pcrel:8 bnot #imm,rd 9010 * bhs pcrel:16 bnot #imm,@rd 9011 bcs pcrel:8 bnot #imm,@abs:8 9012 * bcs pcrel:16 bnot rs,rd 9013 blo pcrel:8 bnot rs,@rd 9014 * blo pcrel:16 bnot rs,@abs:8 9015 bne pcrel:8 bor #imm,rd 9016 * bne pcrel:16 bor #imm,@rd 9017 beq pcrel:8 bor #imm,@abs:8 9018 * beq pcrel:16 bset #imm,rd 9019 bvc pcrel:8 bset #imm,@rd 9020 * bvc pcrel:16 bset #imm,@abs:8 9021 bvs pcrel:8 bset rs,rd 9022 * bvs pcrel:16 bset rs,@rd 9023 bpl pcrel:8 bset rs,@abs:8 9024 * bpl pcrel:16 bsr pcrel:8 9025 bmi pcrel:8 bsr pcrel:16 9026 * bmi pcrel:16 bst #imm,rd 9027 bge pcrel:8 bst #imm,@rd 9028 * bge pcrel:16 bst #imm,@abs:8 9029 blt pcrel:8 btst #imm,rd 9030 * blt pcrel:16 btst #imm,@rd 9031 bgt pcrel:8 btst #imm,@abs:8 9032 * bgt pcrel:16 btst rs,rd 9033 ble pcrel:8 btst rs,@rd 9034 * ble pcrel:16 btst rs,@abs:8 9035 bclr #imm,rd bxor #imm,rd 9036 bclr #imm,@rd bxor #imm,@rd 9037 bclr #imm,@abs:8 bxor #imm,@abs:8 9038 bclr rs,rd cmp.b #imm,rd 9039 bclr rs,@rd cmp.b rs,rd 9040 bclr rs,@abs:8 cmp.w rs,rd 9041 biand #imm,rd cmp.w rs,rd 9042 biand #imm,@rd * cmp.w #imm,rd 9043 biand #imm,@abs:8 * cmp.l #imm,rd 9044 bild #imm,rd * cmp.l rs,rd 9045 bild #imm,@rd daa rs 9046 bild #imm,@abs:8 das rs 9047 bior #imm,rd dec.b rs 9048 bior #imm,@rd * dec.w #imm,rd 9049 bior #imm,@abs:8 * dec.l #imm,rd 9050 bist #imm,rd divxu.b rs,rd 9051 bist #imm,@rd * divxu.w rs,rd 9052 bist #imm,@abs:8 * divxs.b rs,rd 9053 bixor #imm,rd * divxs.w rs,rd 9054 bixor #imm,@rd eepmov 9055 bixor #imm,@abs:8 * eepmovw 9056 9057 * exts.w rd mov.w rs,@abs:16 9058 * exts.l rd * mov.l #imm,rd 9059 * extu.w rd * mov.l rs,rd 9060 * extu.l rd * mov.l @rs,rd 9061 inc rs * mov.l @(disp:16,rs),rd 9062 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 9063 * inc.l #imm,rd * mov.l @rs+,rd 9064 jmp @rs * mov.l @abs:16,rd 9065 jmp abs * mov.l @abs:24,rd 9066 jmp @@abs:8 * mov.l rs,@rd 9067 jsr @rs * mov.l rs,@(disp:16,rd) 9068 jsr abs * mov.l rs,@(disp:24,rd) 9069 jsr @@abs:8 * mov.l rs,@-rd 9070 ldc #imm,ccr * mov.l rs,@abs:16 9071 ldc rs,ccr * mov.l rs,@abs:24 9072 * ldc @abs:16,ccr movfpe @abs:16,rd 9073 * ldc @abs:24,ccr movtpe rs,@abs:16 9074 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 9075 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 9076 * ldc @rs+,ccr * mulxs.b rs,rd 9077 * ldc @rs,ccr * mulxs.w rs,rd 9078 * mov.b @(disp:24,rs),rd neg.b rs 9079 * mov.b rs,@(disp:24,rd) * neg.w rs 9080 mov.b @abs:16,rd * neg.l rs 9081 mov.b rs,rd nop 9082 mov.b @abs:8,rd not.b rs 9083 mov.b rs,@abs:8 * not.w rs 9084 mov.b rs,rd * not.l rs 9085 mov.b #imm,rd or.b #imm,rd 9086 mov.b @rs,rd or.b rs,rd 9087 mov.b @(disp:16,rs),rd * or.w #imm,rd 9088 mov.b @rs+,rd * or.w rs,rd 9089 mov.b @abs:8,rd * or.l #imm,rd 9090 mov.b rs,@rd * or.l rs,rd 9091 mov.b rs,@(disp:16,rd) orc #imm,ccr 9092 mov.b rs,@-rd pop.w rs 9093 mov.b rs,@abs:8 * pop.l rs 9094 mov.w rs,@rd push.w rs 9095 * mov.w @(disp:24,rs),rd * push.l rs 9096 * mov.w rs,@(disp:24,rd) rotl.b rs 9097 * mov.w @abs:24,rd * rotl.w rs 9098 * mov.w rs,@abs:24 * rotl.l rs 9099 mov.w rs,rd rotr.b rs 9100 mov.w #imm,rd * rotr.w rs 9101 mov.w @rs,rd * rotr.l rs 9102 mov.w @(disp:16,rs),rd rotxl.b rs 9103 mov.w @rs+,rd * rotxl.w rs 9104 mov.w @abs:16,rd * rotxl.l rs 9105 mov.w rs,@(disp:16,rd) rotxr.b rs 9106 mov.w rs,@-rd * rotxr.w rs 9107 9108 * rotxr.l rs * stc ccr,@(disp:24,rd) 9109 bpt * stc ccr,@-rd 9110 rte * stc ccr,@abs:16 9111 rts * stc ccr,@abs:24 9112 shal.b rs sub.b rs,rd 9113 * shal.w rs sub.w rs,rd 9114 * shal.l rs * sub.w #imm,rd 9115 shar.b rs * sub.l rs,rd 9116 * shar.w rs * sub.l #imm,rd 9117 * shar.l rs subs #imm,rd 9118 shll.b rs subx #imm,rd 9119 * shll.w rs subx rs,rd 9120 * shll.l rs * trapa #imm 9121 shlr.b rs xor #imm,rd 9122 * shlr.w rs xor rs,rd 9123 * shlr.l rs * xor.w #imm,rd 9124 sleep * xor.w rs,rd 9125 stc ccr,rd * xor.l #imm,rd 9126 * stc ccr,@rs * xor.l rs,rd 9127 * stc ccr,@(disp:16,rd) xorc #imm,ccr 9128 9129 Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined 9130 with variants using the suffixes `.b', `.w', and `.l' to specify the 9131 size of a memory operand. `as' supports these suffixes, but does not 9132 require them; since one of the operands is always a register, `as' can 9133 deduce the correct size. 9134 9135 For example, since `r0' refers to a 16-bit register, 9136 mov r0,@foo 9137 is equivalent to 9138 mov.w r0,@foo 9139 9140 If you use the size suffixes, `as' issues a warning when the suffix 9141 and the register size do not match. 9142 9143 9144 File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 9145 9146 9.11 HPPA Dependent Features 9147 ============================ 9148 9149 * Menu: 9150 9151 * HPPA Notes:: Notes 9152 * HPPA Options:: Options 9153 * HPPA Syntax:: Syntax 9154 * HPPA Floating Point:: Floating Point 9155 * HPPA Directives:: HPPA Machine Directives 9156 * HPPA Opcodes:: Opcodes 9157 9158 9159 File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 9160 9161 9.11.1 Notes 9162 ------------ 9163 9164 As a back end for GNU CC `as' has been throughly tested and should work 9165 extremely well. We have tested it only minimally on hand written 9166 assembly code and no one has tested it much on the assembly output from 9167 the HP compilers. 9168 9169 The format of the debugging sections has changed since the original 9170 `as' port (version 1.3X) was released; therefore, you must rebuild all 9171 HPPA objects and libraries with the new assembler so that you can debug 9172 the final executable. 9173 9174 The HPPA `as' port generates a small subset of the relocations 9175 available in the SOM and ELF object file formats. Additional relocation 9176 support will be added as it becomes necessary. 9177 9178 9179 File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 9180 9181 9.11.2 Options 9182 -------------- 9183 9184 `as' has no machine-dependent command-line options for the HPPA. 9185 9186 9187 File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 9188 9189 9.11.3 Syntax 9190 ------------- 9191 9192 The assembler syntax closely follows the HPPA instruction set reference 9193 manual; assembler directives and general syntax closely follow the HPPA 9194 assembly language reference manual, with a few noteworthy differences. 9195 9196 First, a colon may immediately follow a label definition. This is 9197 simply for compatibility with how most assembly language programmers 9198 write code. 9199 9200 Some obscure expression parsing problems may affect hand written 9201 code which uses the `spop' instructions, or code which makes significant 9202 use of the `!' line separator. 9203 9204 `as' is much less forgiving about missing arguments and other 9205 similar oversights than the HP assembler. `as' notifies you of missing 9206 arguments as syntax errors; this is regarded as a feature, not a bug. 9207 9208 Finally, `as' allows you to use an external symbol without 9209 explicitly importing the symbol. _Warning:_ in the future this will be 9210 an error for HPPA targets. 9211 9212 Special characters for HPPA targets include: 9213 9214 `;' is the line comment character. 9215 9216 `!' can be used instead of a newline to separate statements. 9217 9218 Since `$' has no special meaning, you may use it in symbol names. 9219 9220 9221 File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 9222 9223 9.11.4 Floating Point 9224 --------------------- 9225 9226 The HPPA family uses IEEE floating-point numbers. 9227 9228 9229 File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 9230 9231 9.11.5 HPPA Assembler Directives 9232 -------------------------------- 9233 9234 `as' for the HPPA supports many additional directives for compatibility 9235 with the native assembler. This section describes them only briefly. 9236 For detailed information on HPPA-specific assembler directives, see 9237 `HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). 9238 9239 `as' does _not_ support the following assembler directives described 9240 in the HP manual: 9241 9242 .endm .liston 9243 .enter .locct 9244 .leave .macro 9245 .listoff 9246 9247 Beyond those implemented for compatibility, `as' supports one 9248 additional assembler directive for the HPPA: `.param'. It conveys 9249 register argument locations for static functions. Its syntax closely 9250 follows the `.export' directive. 9251 9252 These are the additional directives in `as' for the HPPA: 9253 9254 `.block N' 9255 `.blockz N' 9256 Reserve N bytes of storage, and initialize them to zero. 9257 9258 `.call' 9259 Mark the beginning of a procedure call. Only the special case 9260 with _no arguments_ is allowed. 9261 9262 `.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' 9263 Specify a number of parameters and flags that define the 9264 environment for a procedure. 9265 9266 PARAM may be any of `frame' (frame size), `entry_gr' (end of 9267 general register range), `entry_fr' (end of float register range), 9268 `entry_sr' (end of space register range). 9269 9270 The values for FLAG are `calls' or `caller' (proc has 9271 subroutines), `no_calls' (proc does not call subroutines), 9272 `save_rp' (preserve return pointer), `save_sp' (proc preserves 9273 stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' 9274 (proc is interrupt routine). 9275 9276 `.code' 9277 Assemble into the standard section called `$TEXT$', subsection 9278 `$CODE$'. 9279 9280 `.copyright "STRING"' 9281 In the SOM object format, insert STRING into the object code, 9282 marked as a copyright string. 9283 9284 `.copyright "STRING"' 9285 In the ELF object format, insert STRING into the object code, 9286 marked as a version string. 9287 9288 `.enter' 9289 Not yet supported; the assembler rejects programs containing this 9290 directive. 9291 9292 `.entry' 9293 Mark the beginning of a procedure. 9294 9295 `.exit' 9296 Mark the end of a procedure. 9297 9298 `.export NAME [ ,TYP ] [ ,PARAM=R ]' 9299 Make a procedure NAME available to callers. TYP, if present, must 9300 be one of `absolute', `code' (ELF only, not SOM), `data', `entry', 9301 `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'. 9302 9303 PARAM, if present, provides either relocation information for the 9304 procedure arguments and result, or a privilege level. PARAM may be 9305 `argwN' (where N ranges from `0' to `3', and indicates one of four 9306 one-word arguments); `rtnval' (the procedure's result); or 9307 `priv_lev' (privilege level). For arguments or the result, R 9308 specifies how to relocate, and must be one of `no' (not 9309 relocatable), `gr' (argument is in general register), `fr' (in 9310 floating point register), or `fu' (upper half of float register). 9311 For `priv_lev', R is an integer. 9312 9313 `.half N' 9314 Define a two-byte integer constant N; synonym for the portable 9315 `as' directive `.short'. 9316 9317 `.import NAME [ ,TYP ]' 9318 Converse of `.export'; make a procedure available to call. The 9319 arguments use the same conventions as the first two arguments for 9320 `.export'. 9321 9322 `.label NAME' 9323 Define NAME as a label for the current assembly location. 9324 9325 `.leave' 9326 Not yet supported; the assembler rejects programs containing this 9327 directive. 9328 9329 `.origin LC' 9330 Advance location counter to LC. Synonym for the `as' portable 9331 directive `.org'. 9332 9333 `.param NAME [ ,TYP ] [ ,PARAM=R ]' 9334 Similar to `.export', but used for static procedures. 9335 9336 `.proc' 9337 Use preceding the first statement of a procedure. 9338 9339 `.procend' 9340 Use following the last statement of a procedure. 9341 9342 `LABEL .reg EXPR' 9343 Synonym for `.equ'; define LABEL with the absolute expression EXPR 9344 as its value. 9345 9346 `.space SECNAME [ ,PARAMS ]' 9347 Switch to section SECNAME, creating a new section by that name if 9348 necessary. You may only use PARAMS when creating a new section, 9349 not when switching to an existing one. SECNAME may identify a 9350 section by number rather than by name. 9351 9352 If specified, the list PARAMS declares attributes of the section, 9353 identified by keywords. The keywords recognized are `spnum=EXP' 9354 (identify this section by the number EXP, an absolute expression), 9355 `sort=EXP' (order sections according to this sort key when linking; 9356 EXP is an absolute expression), `unloadable' (section contains no 9357 loadable data), `notdefined' (this section defined elsewhere), and 9358 `private' (data in this section not available to other programs). 9359 9360 `.spnum SECNAM' 9361 Allocate four bytes of storage, and initialize them with the 9362 section number of the section named SECNAM. (You can define the 9363 section number with the HPPA `.space' directive.) 9364 9365 `.string "STR"' 9366 Copy the characters in the string STR to the object file. *Note 9367 Strings: Strings, for information on escape sequences you can use 9368 in `as' strings. 9369 9370 _Warning!_ The HPPA version of `.string' differs from the usual 9371 `as' definition: it does _not_ write a zero byte after copying STR. 9372 9373 `.stringz "STR"' 9374 Like `.string', but appends a zero byte after copying STR to object 9375 file. 9376 9377 `.subspa NAME [ ,PARAMS ]' 9378 `.nsubspa NAME [ ,PARAMS ]' 9379 Similar to `.space', but selects a subsection NAME within the 9380 current section. You may only specify PARAMS when you create a 9381 subsection (in the first instance of `.subspa' for this NAME). 9382 9383 If specified, the list PARAMS declares attributes of the 9384 subsection, identified by keywords. The keywords recognized are 9385 `quad=EXPR' ("quadrant" for this subsection), `align=EXPR' 9386 (alignment for beginning of this subsection; a power of two), 9387 `access=EXPR' (value for "access rights" field), `sort=EXPR' 9388 (sorting order for this subspace in link), `code_only' (subsection 9389 contains only code), `unloadable' (subsection cannot be loaded 9390 into memory), `comdat' (subsection is comdat), `common' 9391 (subsection is common block), `dup_comm' (subsection may have 9392 duplicate names), or `zero' (subsection is all zeros, do not write 9393 in object file). 9394 9395 `.nsubspa' always creates a new subspace with the given name, even 9396 if one with the same name already exists. 9397 9398 `comdat', `common' and `dup_comm' can be used to implement various 9399 flavors of one-only support when using the SOM linker. The SOM 9400 linker only supports specific combinations of these flags. The 9401 details are not documented. A brief description is provided here. 9402 9403 `comdat' provides a form of linkonce support. It is useful for 9404 both code and data subspaces. A `comdat' subspace has a key symbol 9405 marked by the `is_comdat' flag or `ST_COMDAT'. Only the first 9406 subspace for any given key is selected. The key symbol becomes 9407 universal in shared links. This is similar to the behavior of 9408 `secondary_def' symbols. 9409 9410 `common' provides Fortran named common support. It is only useful 9411 for data subspaces. Symbols with the flag `is_common' retain this 9412 flag in shared links. Referencing a `is_common' symbol in a shared 9413 library from outside the library doesn't work. Thus, `is_common' 9414 symbols must be output whenever they are needed. 9415 9416 `common' and `dup_comm' together provide Cobol common support. 9417 The subspaces in this case must all be the same length. 9418 Otherwise, this support is similar to the Fortran common support. 9419 9420 `dup_comm' by itself provides a type of one-only support for code. 9421 Only the first `dup_comm' subspace is selected. There is a rather 9422 complex algorithm to compare subspaces. Code symbols marked with 9423 the `dup_common' flag are hidden. This support was intended for 9424 "C++ duplicate inlines". 9425 9426 A simplified technique is used to mark the flags of symbols based 9427 on the flags of their subspace. A symbol with the scope 9428 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 9429 the corresponding settings of `comdat', `common' and `dup_comm' 9430 from the subspace, respectively. This avoids having to introduce 9431 additional directives to mark these symbols. The HP assembler 9432 sets `is_common' from `common'. However, it doesn't set the 9433 `dup_common' from `dup_comm'. It doesn't have `comdat' support. 9434 9435 `.version "STR"' 9436 Write STR as version identifier in object code. 9437 9438 9439 File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 9440 9441 9.11.6 Opcodes 9442 -------------- 9443 9444 For detailed information on the HPPA machine instruction set, see 9445 `PA-RISC Architecture and Instruction Set Reference Manual' (HP 9446 09740-90039). 9447 9448 9449 File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 9450 9451 9.12 ESA/390 Dependent Features 9452 =============================== 9453 9454 * Menu: 9455 9456 * ESA/390 Notes:: Notes 9457 * ESA/390 Options:: Options 9458 * ESA/390 Syntax:: Syntax 9459 * ESA/390 Floating Point:: Floating Point 9460 * ESA/390 Directives:: ESA/390 Machine Directives 9461 * ESA/390 Opcodes:: Opcodes 9462 9463 9464 File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent 9465 9466 9.12.1 Notes 9467 ------------ 9468 9469 The ESA/390 `as' port is currently intended to be a back-end for the 9470 GNU CC compiler. It is not HLASM compatible, although it does support 9471 a subset of some of the HLASM directives. The only supported binary 9472 file format is ELF; none of the usual MVS/VM/OE/USS object file 9473 formats, such as ESD or XSD, are supported. 9474 9475 When used with the GNU CC compiler, the ESA/390 `as' will produce 9476 correct, fully relocated, functional binaries, and has been used to 9477 compile and execute large projects. However, many aspects should still 9478 be considered experimental; these include shared library support, 9479 dynamically loadable objects, and any relocation other than the 31-bit 9480 relocation. 9481 9482 9483 File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent 9484 9485 9.12.2 Options 9486 -------------- 9487 9488 `as' has no machine-dependent command-line options for the ESA/390. 9489 9490 9491 File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent 9492 9493 9.12.3 Syntax 9494 ------------- 9495 9496 The opcode/operand syntax follows the ESA/390 Principles of Operation 9497 manual; assembler directives and general syntax are loosely based on the 9498 prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives 9499 are _not_ supported for the most part, with the exception of those 9500 described herein. 9501 9502 A leading dot in front of directives is optional, and the case of 9503 directives is ignored; thus for example, .using and USING have the same 9504 effect. 9505 9506 A colon may immediately follow a label definition. This is simply 9507 for compatibility with how most assembly language programmers write 9508 code. 9509 9510 `#' is the line comment character. 9511 9512 `;' can be used instead of a newline to separate statements. 9513 9514 Since `$' has no special meaning, you may use it in symbol names. 9515 9516 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, 9517 fp6. By using thesse symbolic names, `as' can detect simple syntax 9518 errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for 9519 r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base 9520 for r3 and rpgt or r.pgt for r4. 9521 9522 `*' is the current location counter. Unlike `.' it is always 9523 relative to the last USING directive. Note that this means that 9524 expressions cannot use multiplication, as any occurrence of `*' will be 9525 interpreted as a location counter. 9526 9527 All labels are relative to the last USING. Thus, branches to a label 9528 always imply the use of base+displacement. 9529 9530 Many of the usual forms of address constants / address literals are 9531 supported. Thus, 9532 .using *,r3 9533 L r15,=A(some_routine) 9534 LM r6,r7,=V(some_longlong_extern) 9535 A r1,=F'12' 9536 AH r0,=H'42' 9537 ME r6,=E'3.1416' 9538 MD r6,=D'3.14159265358979' 9539 O r6,=XL4'cacad0d0' 9540 .ltorg 9541 should all behave as expected: that is, an entry in the literal pool 9542 will be created (or reused if it already exists), and the instruction 9543 operands will be the displacement into the literal pool using the 9544 current base register (as last declared with the `.using' directive). 9545 9546 9547 File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent 9548 9549 9.12.4 Floating Point 9550 --------------------- 9551 9552 The assembler generates only IEEE floating-point numbers. The older 9553 floating point formats are not supported. 9554 9555 9556 File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent 9557 9558 9.12.5 ESA/390 Assembler Directives 9559 ----------------------------------- 9560 9561 `as' for the ESA/390 supports all of the standard ELF/SVR4 assembler 9562 directives that are documented in the main part of this documentation. 9563 Several additional directives are supported in order to implement the 9564 ESA/390 addressing model. The most important of these are `.using' and 9565 `.ltorg' 9566 9567 These are the additional directives in `as' for the ESA/390: 9568 9569 `.dc' 9570 A small subset of the usual DC directive is supported. 9571 9572 `.drop REGNO' 9573 Stop using REGNO as the base register. The REGNO must have been 9574 previously declared with a `.using' directive in the same section 9575 as the current section. 9576 9577 `.ebcdic STRING' 9578 Emit the EBCDIC equivalent of the indicated string. The emitted 9579 string will be null terminated. Note that the directives 9580 `.string' etc. emit ascii strings by default. 9581 9582 `EQU' 9583 The standard HLASM-style EQU directive is not supported; however, 9584 the standard `as' directive .equ can be used to the same effect. 9585 9586 `.ltorg' 9587 Dump the literal pool accumulated so far; begin a new literal pool. 9588 The literal pool will be written in the current section; in order 9589 to generate correct assembly, a `.using' must have been previously 9590 specified in the same section. 9591 9592 `.using EXPR,REGNO' 9593 Use REGNO as the base register for all subsequent RX, RS, and SS 9594 form instructions. The EXPR will be evaluated to obtain the base 9595 address; usually, EXPR will merely be `*'. 9596 9597 This assembler allows two `.using' directives to be simultaneously 9598 outstanding, one in the `.text' section, and one in another section 9599 (typically, the `.data' section). This feature allows dynamically 9600 loaded objects to be implemented in a relatively straightforward 9601 way. A `.using' directive must always be specified in the `.text' 9602 section; this will specify the base register that will be used for 9603 branches in the `.text' section. A second `.using' may be 9604 specified in another section; this will specify the base register 9605 that is used for non-label address literals. When a second 9606 `.using' is specified, then the subsequent `.ltorg' must be put in 9607 the same section; otherwise an error will result. 9608 9609 Thus, for example, the following code uses `r3' to address branch 9610 targets and `r4' to address the literal pool, which has been 9611 written to the `.data' section. The is, the constants 9612 `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in 9613 the `.data' section. 9614 9615 .data 9616 .using LITPOOL,r4 9617 .text 9618 BASR r3,0 9619 .using *,r3 9620 B START 9621 .long LITPOOL 9622 START: 9623 L r4,4(,r3) 9624 L r15,=A(some_routine) 9625 LTR r15,r15 9626 BNE LABEL 9627 AH r0,=H'42' 9628 LABEL: 9629 ME r6,=E'3.1416' 9630 .data 9631 LITPOOL: 9632 .ltorg 9633 9634 Note that this dual-`.using' directive semantics extends and is 9635 not compatible with HLASM semantics. Note that this assembler 9636 directive does not support the full range of HLASM semantics. 9637 9638 9639 9640 File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent 9641 9642 9.12.6 Opcodes 9643 -------------- 9644 9645 For detailed information on the ESA/390 machine instruction set, see 9646 `ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). 9647 9648 9649 File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies 9650 9651 9.13 80386 Dependent Features 9652 ============================= 9653 9654 The i386 version `as' supports both the original Intel 386 9655 architecture in both 16 and 32-bit mode as well as AMD x86-64 9656 architecture extending the Intel architecture to 64-bits. 9657 9658 * Menu: 9659 9660 * i386-Options:: Options 9661 * i386-Directives:: X86 specific directives 9662 * i386-Syntax:: AT&T Syntax versus Intel Syntax 9663 * i386-Mnemonics:: Instruction Naming 9664 * i386-Regs:: Register Naming 9665 * i386-Prefixes:: Instruction Prefixes 9666 * i386-Memory:: Memory References 9667 * i386-Jumps:: Handling of Jump Instructions 9668 * i386-Float:: Floating Point 9669 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 9670 * i386-LWP:: AMD's Lightweight Profiling Instructions 9671 * i386-16bit:: Writing 16-bit Code 9672 * i386-Arch:: Specifying an x86 CPU architecture 9673 * i386-Bugs:: AT&T Syntax bugs 9674 * i386-Notes:: Notes 9675 9676 9677 File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 9678 9679 9.13.1 Options 9680 -------------- 9681 9682 The i386 version of `as' has a few machine dependent options: 9683 9684 `--32 | --64' 9685 Select the word size, either 32 bits or 64 bits. Selecting 32-bit 9686 implies Intel i386 architecture, while 64-bit implies AMD x86-64 9687 architecture. 9688 9689 These options are only available with the ELF object file format, 9690 and require that the necessary BFD support has been included (on a 9691 32-bit platform you have to add -enable-64-bit-bfd to configure 9692 enable 64-bit usage and use x86-64 as target platform). 9693 9694 `-n' 9695 By default, x86 GAS replaces multiple nop instructions used for 9696 alignment within code sections with multi-byte nop instructions 9697 such as leal 0(%esi,1),%esi. This switch disables the 9698 optimization. 9699 9700 `--divide' 9701 On SVR4-derived platforms, the character `/' is treated as a 9702 comment character, which means that it cannot be used in 9703 expressions. The `--divide' option turns `/' into a normal 9704 character. This does not disable `/' at the beginning of a line 9705 starting a comment, or affect using `#' for starting a comment. 9706 9707 `-march=CPU[+EXTENSION...]' 9708 This option specifies the target processor. The assembler will 9709 issue an error message if an attempt is made to assemble an 9710 instruction which will not execute on the target processor. The 9711 following processor names are recognized: `i8086', `i186', `i286', 9712 `i386', `i486', `i586', `i686', `pentium', `pentiumpro', 9713 `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona', 9714 `core', `core2', `corei7', `l1om', `k6', `k6_2', `athlon', 9715 `opteron', `k8', `amdfam10', `bdver1', `generic32' and `generic64'. 9716 9717 In addition to the basic instruction set, the assembler can be 9718 told to accept various extension mnemonics. For example, 9719 `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The 9720 following extensions are currently supported: `8087', `287', `387', 9721 `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1', 9722 `sse4.2', `sse4', `nosse', `avx', `noavx', `vmx', `smx', `xsave', 9723 `xsaveopt', `aes', `pclmul', `fsgsbase', `rdrnd', `f16c', `fma', 9724 `movbe', `ept', `clflush', `lwp', `fma4', `xop', `syscall', 9725 `rdtscp', `3dnow', `3dnowa', `sse4a', `sse5', `svme', `abm' and 9726 `padlock'. Note that rather than extending a basic instruction 9727 set, the extension mnemonics starting with `no' revoke the 9728 respective functionality. 9729 9730 When the `.arch' directive is used with `-march', the `.arch' 9731 directive will take precedent. 9732 9733 `-mtune=CPU' 9734 This option specifies a processor to optimize for. When used in 9735 conjunction with the `-march' option, only instructions of the 9736 processor specified by the `-march' option will be generated. 9737 9738 Valid CPU values are identical to the processor list of 9739 `-march=CPU'. 9740 9741 `-msse2avx' 9742 This option specifies that the assembler should encode SSE 9743 instructions with VEX prefix. 9744 9745 `-msse-check=NONE' 9746 `-msse-check=WARNING' 9747 `-msse-check=ERROR' 9748 These options control if the assembler should check SSE 9749 intructions. `-msse-check=NONE' will make the assembler not to 9750 check SSE instructions, which is the default. 9751 `-msse-check=WARNING' will make the assembler issue a warning for 9752 any SSE intruction. `-msse-check=ERROR' will make the assembler 9753 issue an error for any SSE intruction. 9754 9755 `-mavxscalar=128' 9756 `-mavxscalar=256' 9757 This options control how the assembler should encode scalar AVX 9758 instructions. `-mavxscalar=128' will encode scalar AVX 9759 instructions with 128bit vector length, which is the default. 9760 `-mavxscalar=256' will encode scalar AVX instructions with 256bit 9761 vector length. 9762 9763 `-mmnemonic=ATT' 9764 `-mmnemonic=INTEL' 9765 This option specifies instruction mnemonic for matching 9766 instructions. The `.att_mnemonic' and `.intel_mnemonic' 9767 directives will take precedent. 9768 9769 `-msyntax=ATT' 9770 `-msyntax=INTEL' 9771 This option specifies instruction syntax when processing 9772 instructions. The `.att_syntax' and `.intel_syntax' directives 9773 will take precedent. 9774 9775 `-mnaked-reg' 9776 This opetion specifies that registers don't require a `%' prefix. 9777 The `.att_syntax' and `.intel_syntax' directives will take 9778 precedent. 9779 9780 9781 9782 File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 9783 9784 9.13.2 x86 specific Directives 9785 ------------------------------ 9786 9787 `.lcomm SYMBOL , LENGTH[, ALIGNMENT]' 9788 Reserve LENGTH (an absolute expression) bytes for a local common 9789 denoted by SYMBOL. The section and value of SYMBOL are those of 9790 the new local common. The addresses are allocated in the bss 9791 section, so that at run-time the bytes start off zeroed. Since 9792 SYMBOL is not declared global, it is normally not visible to `ld'. 9793 The optional third parameter, ALIGNMENT, specifies the desired 9794 alignment of the symbol in the bss section. 9795 9796 This directive is only available for COFF based x86 targets. 9797 9798 9799 9800 File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 9801 9802 9.13.3 AT&T Syntax versus Intel Syntax 9803 -------------------------------------- 9804 9805 `as' now supports assembly using Intel assembler syntax. 9806 `.intel_syntax' selects Intel mode, and `.att_syntax' switches back to 9807 the usual AT&T mode for compatibility with the output of `gcc'. Either 9808 of these directives may have an optional argument, `prefix', or 9809 `noprefix' specifying whether registers require a `%' prefix. AT&T 9810 System V/386 assembler syntax is quite different from Intel syntax. We 9811 mention these differences because almost all 80386 documents use Intel 9812 syntax. Notable differences between the two syntaxes are: 9813 9814 * AT&T immediate operands are preceded by `$'; Intel immediate 9815 operands are undelimited (Intel `push 4' is AT&T `pushl $4'). 9816 AT&T register operands are preceded by `%'; Intel register operands 9817 are undelimited. AT&T absolute (as opposed to PC relative) 9818 jump/call operands are prefixed by `*'; they are undelimited in 9819 Intel syntax. 9820 9821 * AT&T and Intel syntax use the opposite order for source and 9822 destination operands. Intel `add eax, 4' is `addl $4, %eax'. The 9823 `source, dest' convention is maintained for compatibility with 9824 previous Unix assemblers. Note that `bound', `invlpga', and 9825 instructions with 2 immediate operands, such as the `enter' 9826 instruction, do _not_ have reversed order. *note i386-Bugs::. 9827 9828 * In AT&T syntax the size of memory operands is determined from the 9829 last character of the instruction mnemonic. Mnemonic suffixes of 9830 `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long 9831 (32-bit) and quadruple word (64-bit) memory references. Intel 9832 syntax accomplishes this by prefixing memory operands (_not_ the 9833 instruction mnemonics) with `byte ptr', `word ptr', `dword ptr' 9834 and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO, 9835 %al' in AT&T syntax. 9836 9837 In 64-bit code, `movabs' can be used to encode the `mov' 9838 instruction with the 64-bit displacement or immediate operand. 9839 9840 * Immediate form long jumps and calls are `lcall/ljmp $SECTION, 9841 $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far 9842 SECTION:OFFSET'. Also, the far return instruction is `lret 9843 $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far 9844 STACK-ADJUST'. 9845 9846 * The AT&T assembler does not provide support for multiple section 9847 programs. Unix style systems expect all programs to be single 9848 sections. 9849 9850 9851 File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 9852 9853 9.13.4 Instruction Naming 9854 ------------------------- 9855 9856 Instruction mnemonics are suffixed with one character modifiers which 9857 specify the size of operands. The letters `b', `w', `l' and `q' 9858 specify byte, word, long and quadruple word operands. If no suffix is 9859 specified by an instruction then `as' tries to fill in the missing 9860 suffix based on the destination register operand (the last one by 9861 convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; 9862 also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is 9863 incompatible with the AT&T Unix assembler which assumes that a missing 9864 mnemonic suffix implies long operand size. (This incompatibility does 9865 not affect compiler output since compilers always explicitly specify 9866 the mnemonic suffix.) 9867 9868 Almost all instructions have the same names in AT&T and Intel format. 9869 There are a few exceptions. The sign extend and zero extend 9870 instructions need two sizes to specify them. They need a size to 9871 sign/zero extend _from_ and a size to zero extend _to_. This is 9872 accomplished by using two instruction mnemonic suffixes in AT&T syntax. 9873 Base names for sign extend and zero extend are `movs...' and `movz...' 9874 in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction 9875 mnemonic suffixes are tacked on to this base name, the _from_ suffix 9876 before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for 9877 "move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are 9878 `bl' (from byte to long), `bw' (from byte to word), `wl' (from word to 9879 long), `bq' (from byte to quadruple word), `wq' (from word to quadruple 9880 word), and `lq' (from long to quadruple word). 9881 9882 Different encoding options can be specified via optional mnemonic 9883 suffix. `.s' suffix swaps 2 register operands in encoding when moving 9884 from one register to another. `.d32' suffix forces 32bit displacement 9885 in encoding. 9886 9887 The Intel-syntax conversion instructions 9888 9889 * `cbw' -- sign-extend byte in `%al' to word in `%ax', 9890 9891 * `cwde' -- sign-extend word in `%ax' to long in `%eax', 9892 9893 * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax', 9894 9895 * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax', 9896 9897 * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64 9898 only), 9899 9900 * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax' 9901 (x86-64 only), 9902 9903 are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T 9904 naming. `as' accepts either naming for these instructions. 9905 9906 Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, 9907 but are `call far' and `jump far' in Intel convention. 9908 9909 9.13.5 AT&T Mnemonic versus Intel Mnemonic 9910 ------------------------------------------ 9911 9912 `as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects 9913 Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to 9914 the usual AT&T mnemonic with AT&T syntax for compatibility with the 9915 output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp', 9916 `fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are 9917 implemented in AT&T System V/386 assembler with different mnemonics 9918 from those in Intel IA32 specification. `gcc' generates those 9919 instructions with AT&T mnemonic. 9920 9921 9922 File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 9923 9924 9.13.6 Register Naming 9925 ---------------------- 9926 9927 Register operands are always prefixed with `%'. The 80386 registers 9928 consist of 9929 9930 * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', 9931 `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' 9932 (the stack pointer). 9933 9934 * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', 9935 `%si', `%bp', and `%sp'. 9936 9937 * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', 9938 `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', 9939 `%bx', `%cx', and `%dx') 9940 9941 * the 6 section registers `%cs' (code section), `%ds' (data 9942 section), `%ss' (stack section), `%es', `%fs', and `%gs'. 9943 9944 * the 3 processor control registers `%cr0', `%cr2', and `%cr3'. 9945 9946 * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and 9947 `%db7'. 9948 9949 * the 2 test registers `%tr6' and `%tr7'. 9950 9951 * the 8 floating point register stack `%st' or equivalently 9952 `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', 9953 `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX 9954 registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' 9955 and `%mm7'. 9956 9957 * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3', 9958 `%xmm4', `%xmm5', `%xmm6' and `%xmm7'. 9959 9960 The AMD x86-64 architecture extends the register set by: 9961 9962 * enhancing the 8 32-bit registers to 64-bit: `%rax' (the 9963 accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the 9964 frame pointer), `%rsp' (the stack pointer) 9965 9966 * the 8 extended registers `%r8'-`%r15'. 9967 9968 * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d' 9969 9970 * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w' 9971 9972 * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b' 9973 9974 * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'. 9975 9976 * the 8 debug registers: `%db8'-`%db15'. 9977 9978 * the 8 SSE registers: `%xmm8'-`%xmm15'. 9979 9980 9981 File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 9982 9983 9.13.7 Instruction Prefixes 9984 --------------------------- 9985 9986 Instruction prefixes are used to modify the following instruction. They 9987 are used to repeat string instructions, to provide section overrides, to 9988 perform bus lock operations, and to change operand and address sizes. 9989 (Most instructions that normally operate on 32-bit operands will use 9990 16-bit operands if the instruction has an "operand size" prefix.) 9991 Instruction prefixes are best written on the same line as the 9992 instruction they act upon. For example, the `scas' (scan string) 9993 instruction is repeated with: 9994 9995 repne scas %es:(%edi),%al 9996 9997 You may also place prefixes on the lines immediately preceding the 9998 instruction, but this circumvents checks that `as' does with prefixes, 9999 and will not work with all prefixes. 10000 10001 Here is a list of instruction prefixes: 10002 10003 * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. 10004 These are automatically added by specifying using the 10005 SECTION:MEMORY-OPERAND form for memory references. 10006 10007 * Operand/Address size prefixes `data16' and `addr16' change 32-bit 10008 operands/addresses into 16-bit operands/addresses, while `data32' 10009 and `addr32' change 16-bit ones (in a `.code16' section) into 10010 32-bit operands/addresses. These prefixes _must_ appear on the 10011 same line of code as the instruction they modify. For example, in 10012 a 16-bit `.code16' section, you might write: 10013 10014 addr32 jmpl *(%ebx) 10015 10016 * The bus lock prefix `lock' inhibits interrupts during execution of 10017 the instruction it precedes. (This is only valid with certain 10018 instructions; see a 80386 manual for details). 10019 10020 * The wait for coprocessor prefix `wait' waits for the coprocessor to 10021 complete the current instruction. This should never be needed for 10022 the 80386/80387 combination. 10023 10024 * The `rep', `repe', and `repne' prefixes are added to string 10025 instructions to make them repeat `%ecx' times (`%cx' times if the 10026 current address size is 16-bits). 10027 10028 * The `rex' family of prefixes is used by x86-64 to encode 10029 extensions to i386 instruction set. The `rex' prefix has four 10030 bits -- an operand size overwrite (`64') used to change operand 10031 size from 32-bit to 64-bit and X, Y and Z extensions bits used to 10032 extend the register set. 10033 10034 You may write the `rex' prefixes directly. The `rex64xyz' 10035 instruction emits `rex' prefix with all the bits set. By omitting 10036 the `64', `x', `y' or `z' you may write other prefixes as well. 10037 Normally, there is no need to write the prefixes explicitly, since 10038 gas will automatically generate them based on the instruction 10039 operands. 10040 10041 10042 File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 10043 10044 9.13.8 Memory References 10045 ------------------------ 10046 10047 An Intel syntax indirect memory reference of the form 10048 10049 SECTION:[BASE + INDEX*SCALE + DISP] 10050 10051 is translated into the AT&T syntax 10052 10053 SECTION:DISP(BASE, INDEX, SCALE) 10054 10055 where BASE and INDEX are the optional 32-bit base and index registers, 10056 DISP is the optional displacement, and SCALE, taking the values 1, 2, 10057 4, and 8, multiplies INDEX to calculate the address of the operand. If 10058 no SCALE is specified, SCALE is taken to be 1. SECTION specifies the 10059 optional section register for the memory operand, and may override the 10060 default section register (see a 80386 manual for section register 10061 defaults). Note that section overrides in AT&T syntax _must_ be 10062 preceded by a `%'. If you specify a section override which coincides 10063 with the default section register, `as' does _not_ output any section 10064 register override prefixes to assemble the given instruction. Thus, 10065 section overrides can be specified to emphasize which section register 10066 is used for a given memory operand. 10067 10068 Here are some examples of Intel and AT&T style memory references: 10069 10070 AT&T: `-4(%ebp)', Intel: `[ebp - 4]' 10071 BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default 10072 section is used (`%ss' for addressing with `%ebp' as the base 10073 register). INDEX, SCALE are both missing. 10074 10075 AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]' 10076 INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other 10077 fields are missing. The section register here defaults to `%ds'. 10078 10079 AT&T: `foo(,1)'; Intel `[foo]' 10080 This uses the value pointed to by `foo' as a memory operand. Note 10081 that BASE and INDEX are both missing, but there is only _one_ `,'. 10082 This is a syntactic exception. 10083 10084 AT&T: `%gs:foo'; Intel `gs:foo' 10085 This selects the contents of the variable `foo' with section 10086 register SECTION being `%gs'. 10087 10088 Absolute (as opposed to PC relative) call and jump operands must be 10089 prefixed with `*'. If no `*' is specified, `as' always chooses PC 10090 relative addressing for jump/call labels. 10091 10092 Any instruction that has a memory operand, but no register operand, 10093 _must_ specify its size (byte, word, long, or quadruple) with an 10094 instruction mnemonic suffix (`b', `w', `l' or `q', respectively). 10095 10096 The x86-64 architecture adds an RIP (instruction pointer relative) 10097 addressing. This addressing mode is specified by using `rip' as a base 10098 register. Only constant offsets are valid. For example: 10099 10100 AT&T: `1234(%rip)', Intel: `[rip + 1234]' 10101 Points to the address 1234 bytes past the end of the current 10102 instruction. 10103 10104 AT&T: `symbol(%rip)', Intel: `[rip + symbol]' 10105 Points to the `symbol' in RIP relative way, this is shorter than 10106 the default absolute addressing. 10107 10108 Other addressing modes remain unchanged in x86-64 architecture, 10109 except registers used are 64-bit instead of 32-bit. 10110 10111 10112 File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 10113 10114 9.13.9 Handling of Jump Instructions 10115 ------------------------------------ 10116 10117 Jump instructions are always optimized to use the smallest possible 10118 displacements. This is accomplished by using byte (8-bit) displacement 10119 jumps whenever the target is sufficiently close. If a byte displacement 10120 is insufficient a long displacement is used. We do not support word 10121 (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 10122 instruction with the `data16' instruction prefix), since the 80386 10123 insists upon masking `%eip' to 16 bits after the word displacement is 10124 added. (See also *note i386-Arch::) 10125 10126 Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' 10127 and `loopne' instructions only come in byte displacements, so that if 10128 you use these instructions (`gcc' does not use them) you may get an 10129 error message (and incorrect code). The AT&T 80386 assembler tries to 10130 get around this problem by expanding `jcxz foo' to 10131 10132 jcxz cx_zero 10133 jmp cx_nonzero 10134 cx_zero: jmp foo 10135 cx_nonzero: 10136 10137 10138 File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 10139 10140 9.13.10 Floating Point 10141 ---------------------- 10142 10143 All 80387 floating point types except packed BCD are supported. (BCD 10144 support may be added without much difficulty). These data types are 10145 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 10146 and extended (80-bit) precision floating point. Each supported type 10147 has an instruction mnemonic suffix and a constructor associated with 10148 it. Instruction mnemonic suffixes specify the operand's data type. 10149 Constructors build these data types into memory. 10150 10151 * Floating point constructors are `.float' or `.single', `.double', 10152 and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond 10153 to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 10154 80-bit (ten byte) real. The 80387 only supports this format via 10155 the `fldt' (load 80-bit real to stack top) and `fstpt' (store 10156 80-bit real and pop stack) instructions. 10157 10158 * Integer constructors are `.word', `.long' or `.int', and `.quad' 10159 for the 16-, 32-, and 64-bit integer formats. The corresponding 10160 instruction mnemonic suffixes are `s' (single), `l' (long), and 10161 `q' (quad). As with the 80-bit real format, the 64-bit `q' format 10162 is only present in the `fildq' (load quad integer to stack top) 10163 and `fistpq' (store quad integer and pop stack) instructions. 10164 10165 Register to register operations should not use instruction mnemonic 10166 suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as 10167 if you wrote `fst %st, %st(1)', since all register to register 10168 operations use 80-bit floating point operands. (Contrast this with 10169 `fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating 10170 point format, then stores the result in the 4 byte location `mem') 10171 10172 10173 File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 10174 10175 9.13.11 Intel's MMX and AMD's 3DNow! SIMD Operations 10176 ---------------------------------------------------- 10177 10178 `as' supports Intel's MMX instruction set (SIMD instructions for 10179 integer data), available on Intel's Pentium MMX processors and Pentium 10180 II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 10181 probably others. It also supports AMD's 3DNow! instruction set (SIMD 10182 instructions for 32-bit floating point data) available on AMD's K6-2 10183 processor and possibly others in the future. 10184 10185 Currently, `as' does not support Intel's floating point SIMD, Katmai 10186 (KNI). 10187 10188 The eight 64-bit MMX operands, also used by 3DNow!, are called 10189 `%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 10190 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 10191 floating point values. The MMX registers cannot be used at the same 10192 time as the floating point stack. 10193 10194 See Intel and AMD documentation, keeping in mind that the operand 10195 order in instructions is reversed from the Intel syntax. 10196 10197 10198 File: as.info, Node: i386-LWP, Next: i386-16bit, Prev: i386-SIMD, Up: i386-Dependent 10199 10200 9.13.12 AMD's Lightweight Profiling Instructions 10201 ------------------------------------------------ 10202 10203 `as' supports AMD's Lightweight Profiling (LWP) instruction set, 10204 available on AMD's Family 15h (Orochi) processors. 10205 10206 LWP enables applications to collect and manage performance data, and 10207 react to performance events. The collection of performance data 10208 requires no context switches. LWP runs in the context of a thread and 10209 so several counters can be used independently across multiple threads. 10210 LWP can be used in both 64-bit and legacy 32-bit modes. 10211 10212 For detailed information on the LWP instruction set, see the `AMD 10213 Lightweight Profiling Specification' available at Lightweight Profiling 10214 Specification (http://developer.amd.com/cpu/LWP). 10215 10216 10217 File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-LWP, Up: i386-Dependent 10218 10219 9.13.13 Writing 16-bit Code 10220 --------------------------- 10221 10222 While `as' normally writes only "pure" 32-bit i386 code or 64-bit 10223 x86-64 code depending on the default configuration, it also supports 10224 writing code to run in real mode or in 16-bit protected mode code 10225 segments. To do this, put a `.code16' or `.code16gcc' directive before 10226 the assembly language instructions to be run in 16-bit mode. You can 10227 switch `as' to writing 32-bit code with the `.code32' directive or 10228 64-bit code with the `.code64' directive. 10229 10230 `.code16gcc' provides experimental support for generating 16-bit 10231 code from gcc, and differs from `.code16' in that `call', `ret', 10232 `enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' 10233 instructions default to 32-bit size. This is so that the stack pointer 10234 is manipulated in the same way over function calls, allowing access to 10235 function parameters at the same stack offsets as in 32-bit mode. 10236 `.code16gcc' also automatically adds address size prefixes where 10237 necessary to use the 32-bit addressing modes that gcc generates. 10238 10239 The code which `as' generates in 16-bit mode will not necessarily 10240 run on a 16-bit pre-80386 processor. To write code that runs on such a 10241 processor, you must refrain from using _any_ 32-bit constructs which 10242 require `as' to output address or operand size prefixes. 10243 10244 Note that writing 16-bit code instructions by explicitly specifying a 10245 prefix or an instruction mnemonic suffix within a 32-bit code section 10246 generates different machine instructions than those generated for a 10247 16-bit code segment. In a 32-bit code section, the following code 10248 generates the machine opcode bytes `66 6a 04', which pushes the value 10249 `4' onto the stack, decrementing `%esp' by 2. 10250 10251 pushw $4 10252 10253 The same code in a 16-bit code section would generate the machine 10254 opcode bytes `6a 04' (i.e., without the operand size prefix), which is 10255 correct since the processor default operand size is assumed to be 16 10256 bits in a 16-bit code section. 10257 10258 10259 File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 10260 10261 9.13.14 AT&T Syntax bugs 10262 ------------------------ 10263 10264 The UnixWare assembler, and probably other AT&T derived ix86 Unix 10265 assemblers, generate floating point instructions with reversed source 10266 and destination registers in certain cases. Unfortunately, gcc and 10267 possibly many other programs use this reversed syntax, so we're stuck 10268 with it. 10269 10270 For example 10271 10272 fsub %st,%st(3) 10273 results in `%st(3)' being updated to `%st - %st(3)' rather than the 10274 expected `%st(3) - %st'. This happens with all the non-commutative 10275 arithmetic floating point operations with two register operands where 10276 the source register is `%st' and the destination register is `%st(i)'. 10277 10278 10279 File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent 10280 10281 9.13.15 Specifying CPU Architecture 10282 ----------------------------------- 10283 10284 `as' may be told to assemble for a particular CPU (sub-)architecture 10285 with the `.arch CPU_TYPE' directive. This directive enables a warning 10286 when gas detects an instruction that is not supported on the CPU 10287 specified. The choices for CPU_TYPE are: 10288 10289 `i8086' `i186' `i286' `i386' 10290 `i486' `i586' `i686' `pentium' 10291 `pentiumpro' `pentiumii' `pentiumiii' `pentium4' 10292 `prescott' `nocona' `core' `core2' 10293 `corei7' `l1om' 10294 `k6' `k6_2' `athlon' `k8' 10295 `amdfam10' `bdver1' 10296 `generic32' `generic64' 10297 `.mmx' `.sse' `.sse2' `.sse3' 10298 `.ssse3' `.sse4.1' `.sse4.2' `.sse4' 10299 `.avx' `.vmx' `.smx' `.ept' 10300 `.clflush' `.movbe' `.xsave' `.xsaveopt' 10301 `.aes' `.pclmul' `.fma' `.fsgsbase' 10302 `.rdrnd' `.f16c' 10303 `.3dnow' `.3dnowa' `.sse4a' `.sse5' 10304 `.syscall' `.rdtscp' `.svme' `.abm' 10305 `.lwp' `.fma4' `.xop' 10306 `.padlock' 10307 10308 Apart from the warning, there are only two other effects on `as' 10309 operation; Firstly, if you specify a CPU other than `i486', then shift 10310 by one instructions such as `sarl $1, %eax' will automatically use a 10311 two byte opcode sequence. The larger three byte opcode sequence is 10312 used on the 486 (and when no architecture is specified) because it 10313 executes faster on the 486. Note that you can explicitly request the 10314 two byte opcode by writing `sarl %eax'. Secondly, if you specify 10315 `i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte 10316 offset conditional jumps will be promoted when necessary to a two 10317 instruction sequence consisting of a conditional jump of the opposite 10318 sense around an unconditional jump to the target. 10319 10320 Following the CPU architecture (but not a sub-architecture, which 10321 are those starting with a dot), you may specify `jumps' or `nojumps' to 10322 control automatic promotion of conditional jumps. `jumps' is the 10323 default, and enables jump promotion; All external jumps will be of the 10324 long variety, and file-local jumps will be promoted as necessary. 10325 (*note i386-Jumps::) `nojumps' leaves external conditional jumps as 10326 byte offset jumps, and warns about file-local conditional jumps that 10327 `as' promotes. Unconditional jumps are treated as for `jumps'. 10328 10329 For example 10330 10331 .arch i8086,nojumps 10332 10333 10334 File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 10335 10336 9.13.16 Notes 10337 ------------- 10338 10339 There is some trickery concerning the `mul' and `imul' instructions 10340 that deserves mention. The 16-, 32-, 64- and 128-bit expanding 10341 multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') 10342 can be output only in the one operand form. Thus, `imul %ebx, %eax' 10343 does _not_ select the expanding multiply; the expanding multiply would 10344 clobber the `%edx' register, and this would confuse `gcc' output. Use 10345 `imul %ebx' to get the 64-bit product in `%edx:%eax'. 10346 10347 We have added a two operand form of `imul' when the first operand is 10348 an immediate mode expression and the second operand is a register. 10349 This is just a shorthand, so that, multiplying `%eax' by 69, for 10350 example, can be done with `imul $69, %eax' rather than `imul $69, %eax, 10351 %eax'. 10352 10353 10354 File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 10355 10356 9.14 Intel i860 Dependent Features 10357 ================================== 10358 10359 * Menu: 10360 10361 * Notes-i860:: i860 Notes 10362 * Options-i860:: i860 Command-line Options 10363 * Directives-i860:: i860 Machine Directives 10364 * Opcodes for i860:: i860 Opcodes 10365 10366 10367 File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent 10368 10369 9.14.1 i860 Notes 10370 ----------------- 10371 10372 This is a fairly complete i860 assembler which is compatible with the 10373 UNIX System V/860 Release 4 assembler. However, it does not currently 10374 support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT'). 10375 10376 Like the SVR4/860 assembler, the output object format is ELF32. 10377 Currently, this is the only supported object format. If there is 10378 sufficient interest, other formats such as COFF may be implemented. 10379 10380 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 10381 being the default. One difference is that AT&T syntax requires the '%' 10382 prefix on register names while Intel syntax does not. Another 10383 difference is in the specification of relocatable expressions. The 10384 Intel syntax is `ha%expression' whereas the SVR4 syntax is 10385 `[expression]@ha' (and similarly for the "l" and "h" selectors). 10386 10387 10388 File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent 10389 10390 9.14.2 i860 Command-line Options 10391 -------------------------------- 10392 10393 9.14.2.1 SVR4 compatibility options 10394 ................................... 10395 10396 `-V' 10397 Print assembler version. 10398 10399 `-Qy' 10400 Ignored. 10401 10402 `-Qn' 10403 Ignored. 10404 10405 9.14.2.2 Other options 10406 ...................... 10407 10408 `-EL' 10409 Select little endian output (this is the default). 10410 10411 `-EB' 10412 Select big endian output. Note that the i860 always reads 10413 instructions as little endian data, so this option only effects 10414 data and not instructions. 10415 10416 `-mwarn-expand' 10417 Emit a warning message if any pseudo-instruction expansions 10418 occurred. For example, a `or' instruction with an immediate 10419 larger than 16-bits will be expanded into two instructions. This 10420 is a very undesirable feature to rely on, so this flag can help 10421 detect any code where it happens. One use of it, for instance, has 10422 been to find and eliminate any place where `gcc' may emit these 10423 pseudo-instructions. 10424 10425 `-mxp' 10426 Enable support for the i860XP instructions and control registers. 10427 By default, this option is disabled so that only the base 10428 instruction set (i.e., i860XR) is supported. 10429 10430 `-mintel-syntax' 10431 The i860 assembler defaults to AT&T/SVR4 syntax. This option 10432 enables the Intel syntax. 10433 10434 10435 File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent 10436 10437 9.14.3 i860 Machine Directives 10438 ------------------------------ 10439 10440 `.dual' 10441 Enter dual instruction mode. While this directive is supported, the 10442 preferred way to use dual instruction mode is to explicitly code 10443 the dual bit with the `d.' prefix. 10444 10445 `.enddual' 10446 Exit dual instruction mode. While this directive is supported, the 10447 preferred way to use dual instruction mode is to explicitly code 10448 the dual bit with the `d.' prefix. 10449 10450 `.atmp' 10451 Change the temporary register used when expanding pseudo 10452 operations. The default register is `r31'. 10453 10454 The `.dual', `.enddual', and `.atmp' directives are available only 10455 in the Intel syntax mode. 10456 10457 Both syntaxes allow for the standard `.align' directive. However, 10458 the Intel syntax additionally allows keywords for the alignment 10459 parameter: "`.align type'", where `type' is one of `.short', `.long', 10460 `.quad', `.single', `.double' representing alignments of 2, 4, 16, 4, 10461 and 8, respectively. 10462 10463 10464 File: as.info, Node: Opcodes for i860, Prev: Directives-i860, Up: i860-Dependent 10465 10466 9.14.4 i860 Opcodes 10467 ------------------- 10468 10469 All of the Intel i860XR and i860XP machine instructions are supported. 10470 Please see either _i860 Microprocessor Programmer's Reference Manual_ 10471 or _i860 Microprocessor Architecture_ for more information. 10472 10473 9.14.4.1 Other instruction support (pseudo-instructions) 10474 ........................................................ 10475 10476 For compatibility with some other i860 assemblers, a number of 10477 pseudo-instructions are supported. While these are supported, they are 10478 a very undesirable feature that should be avoided - in particular, when 10479 they result in an expansion to multiple actual i860 instructions. Below 10480 are the pseudo-instructions that result in expansions. 10481 * Load large immediate into general register: 10482 10483 The pseudo-instruction `mov imm,%rn' (where the immediate does not 10484 fit within a signed 16-bit field) will be expanded into: 10485 orh large_imm@h,%r0,%rn 10486 or large_imm@l,%rn,%rn 10487 10488 * Load/store with relocatable address expression: 10489 10490 For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will 10491 be expanded into: 10492 orh addr_exp@ha,%rx,%r31 10493 ld.l addr_exp@l(%r31),%rn 10494 10495 The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, 10496 fst.x', and `pst.x' as well. 10497 10498 * Signed large immediate with add/subtract: 10499 10500 If any of the arithmetic operations `adds, addu, subs, subu' are 10501 used with an immediate larger than 16-bits (signed), then they 10502 will be expanded. For instance, the pseudo-instruction `adds 10503 large_imm,%rx,%rn' expands to: 10504 orh large_imm@h,%r0,%r31 10505 or large_imm@l,%r31,%r31 10506 adds %r31,%rx,%rn 10507 10508 * Unsigned large immediate with logical operations: 10509 10510 Logical operations (`or, andnot, or, xor') also result in 10511 expansions. The pseudo-instruction `or large_imm,%rx,%rn' results 10512 in: 10513 orh large_imm@h,%rx,%r31 10514 or large_imm@l,%r31,%rn 10515 10516 Similarly for the others, except for `and' which expands to: 10517 andnot (-1 - large_imm)@h,%rx,%r31 10518 andnot (-1 - large_imm)@l,%r31,%rn 10519 10520 10521 File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies 10522 10523 9.15 Intel 80960 Dependent Features 10524 =================================== 10525 10526 * Menu: 10527 10528 * Options-i960:: i960 Command-line Options 10529 * Floating Point-i960:: Floating Point 10530 * Directives-i960:: i960 Machine Directives 10531 * Opcodes for i960:: i960 Opcodes 10532 10533 10534 File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent 10535 10536 9.15.1 i960 Command-line Options 10537 -------------------------------- 10538 10539 `-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 10540 Select the 80960 architecture. Instructions or features not 10541 supported by the selected architecture cause fatal errors. 10542 10543 `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. 10544 Synonyms are provided for compatibility with other tools. 10545 10546 If you do not specify any of these options, `as' generates code 10547 for any instruction or feature that is supported by _some_ version 10548 of the 960 (even if this means mixing architectures!). In 10549 principle, `as' attempts to deduce the minimal sufficient 10550 processor type if none is specified; depending on the object code 10551 format, the processor type may be recorded in the object file. If 10552 it is critical that the `as' output match a specific architecture, 10553 specify that architecture explicitly. 10554 10555 `-b' 10556 Add code to collect information about conditional branches taken, 10557 for later optimization using branch prediction bits. (The 10558 conditional branch instructions have branch prediction bits in the 10559 CA, CB, and CC architectures.) If BR represents a conditional 10560 branch instruction, the following represents the code generated by 10561 the assembler when `-b' is specified: 10562 10563 call INCREMENT ROUTINE 10564 .word 0 # pre-counter 10565 Label: BR 10566 call INCREMENT ROUTINE 10567 .word 0 # post-counter 10568 10569 The counter following a branch records the number of times that 10570 branch was _not_ taken; the difference between the two counters is 10571 the number of times the branch _was_ taken. 10572 10573 A table of every such `Label' is also generated, so that the 10574 external postprocessor `gbr960' (supplied by Intel) can locate all 10575 the counters. This table is always labeled `__BRANCH_TABLE__'; 10576 this is a local symbol to permit collecting statistics for many 10577 separate object files. The table is word aligned, and begins with 10578 a two-word header. The first word, initialized to 0, is used in 10579 maintaining linked lists of branch tables. The second word is a 10580 count of the number of entries in the table, which follow 10581 immediately: each is a word, pointing to one of the labels 10582 illustrated above. 10583 10584 +------------+------------+------------+ ... +------------+ 10585 | | | | | | 10586 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | 10587 | | | | | | 10588 +------------+------------+------------+ ... +------------+ 10589 10590 __BRANCH_TABLE__ layout 10591 10592 The first word of the header is used to locate multiple branch 10593 tables, since each object file may contain one. Normally the links 10594 are maintained with a call to an initialization routine, placed at 10595 the beginning of each function in the file. The GNU C compiler 10596 generates these calls automatically when you give it a `-b' option. 10597 For further details, see the documentation of `gbr960'. 10598 10599 `-no-relax' 10600 Normally, Compare-and-Branch instructions with targets that require 10601 displacements greater than 13 bits (or that have external targets) 10602 are replaced with the corresponding compare (or `chkbit') and 10603 branch instructions. You can use the `-no-relax' option to 10604 specify that `as' should generate errors instead, if the target 10605 displacement is larger than 13 bits. 10606 10607 This option does not affect the Compare-and-Jump instructions; the 10608 code emitted for them is _always_ adjusted when necessary 10609 (depending on displacement size), regardless of whether you use 10610 `-no-relax'. 10611 10612 10613 File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent 10614 10615 9.15.2 Floating Point 10616 --------------------- 10617 10618 `as' generates IEEE floating-point numbers for the directives `.float', 10619 `.double', `.extended', and `.single'. 10620 10621 10622 File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent 10623 10624 9.15.3 i960 Machine Directives 10625 ------------------------------ 10626 10627 `.bss SYMBOL, LENGTH, ALIGN' 10628 Reserve LENGTH bytes in the bss section for a local SYMBOL, 10629 aligned to the power of two specified by ALIGN. LENGTH and ALIGN 10630 must be positive absolute expressions. This directive differs 10631 from `.lcomm' only in that it permits you to specify an alignment. 10632 *Note `.lcomm': Lcomm. 10633 10634 `.extended FLONUMS' 10635 `.extended' expects zero or more flonums, separated by commas; for 10636 each flonum, `.extended' emits an IEEE extended-format (80-bit) 10637 floating-point number. 10638 10639 `.leafproc CALL-LAB, BAL-LAB' 10640 You can use the `.leafproc' directive in conjunction with the 10641 optimized `callj' instruction to enable faster calls of leaf 10642 procedures. If a procedure is known to call no other procedures, 10643 you may define an entry point that skips procedure prolog code 10644 (and that does not depend on system-supplied saved context), and 10645 declare it as the BAL-LAB using `.leafproc'. If the procedure 10646 also has an entry point that goes through the normal prolog, you 10647 can specify that entry point as CALL-LAB. 10648 10649 A `.leafproc' declaration is meant for use in conjunction with the 10650 optimized call instruction `callj'; the directive records the data 10651 needed later to choose between converting the `callj' into a `bal' 10652 or a `call'. 10653 10654 CALL-LAB is optional; if only one argument is present, or if the 10655 two arguments are identical, the single argument is assumed to be 10656 the `bal' entry point. 10657 10658 `.sysproc NAME, INDEX' 10659 The `.sysproc' directive defines a name for a system procedure. 10660 After you define it using `.sysproc', you can use NAME to refer to 10661 the system procedure identified by INDEX when calling procedures 10662 with the optimized call instruction `callj'. 10663 10664 Both arguments are required; INDEX must be between 0 and 31 10665 (inclusive). 10666 10667 10668 File: as.info, Node: Opcodes for i960, Prev: Directives-i960, Up: i960-Dependent 10669 10670 9.15.4 i960 Opcodes 10671 ------------------- 10672 10673 All Intel 960 machine instructions are supported; *note i960 10674 Command-line Options: Options-i960. for a discussion of selecting the 10675 instruction subset for a particular 960 architecture. 10676 10677 Some opcodes are processed beyond simply emitting a single 10678 corresponding instruction: `callj', and Compare-and-Branch or 10679 Compare-and-Jump instructions with target displacements larger than 13 10680 bits. 10681 10682 * Menu: 10683 10684 * callj-i960:: `callj' 10685 * Compare-and-branch-i960:: Compare-and-Branch 10686 10687 10688 File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 10689 10690 9.15.4.1 `callj' 10691 ................ 10692 10693 You can write `callj' to have the assembler or the linker determine the 10694 most appropriate form of subroutine call: `call', `bal', or `calls'. 10695 If the assembly source contains enough information--a `.leafproc' or 10696 `.sysproc' directive defining the operand--then `as' translates the 10697 `callj'; if not, it simply emits the `callj', leaving it for the linker 10698 to resolve. 10699 10700 10701 File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 10702 10703 9.15.4.2 Compare-and-Branch 10704 ........................... 10705 10706 The 960 architectures provide combined Compare-and-Branch instructions 10707 that permit you to store the branch target in the lower 13 bits of the 10708 instruction word itself. However, if you specify a branch target far 10709 enough away that its address won't fit in 13 bits, the assembler can 10710 either issue an error, or convert your Compare-and-Branch instruction 10711 into separate instructions to do the compare and the branch. 10712 10713 Whether `as' gives an error or expands the instruction depends on 10714 two choices you can make: whether you use the `-no-relax' option, and 10715 whether you use a "Compare and Branch" instruction or a "Compare and 10716 Jump" instruction. The "Jump" instructions are _always_ expanded if 10717 necessary; the "Branch" instructions are expanded when necessary 10718 _unless_ you specify `-no-relax'--in which case `as' gives an error 10719 instead. 10720 10721 These are the Compare-and-Branch instructions, their "Jump" variants, 10722 and the instruction pairs they may expand into: 10723 10724 Compare and 10725 Branch Jump Expanded to 10726 ------ ------ ------------ 10727 bbc chkbit; bno 10728 bbs chkbit; bo 10729 cmpibe cmpije cmpi; be 10730 cmpibg cmpijg cmpi; bg 10731 cmpibge cmpijge cmpi; bge 10732 cmpibl cmpijl cmpi; bl 10733 cmpible cmpijle cmpi; ble 10734 cmpibno cmpijno cmpi; bno 10735 cmpibne cmpijne cmpi; bne 10736 cmpibo cmpijo cmpi; bo 10737 cmpobe cmpoje cmpo; be 10738 cmpobg cmpojg cmpo; bg 10739 cmpobge cmpojge cmpo; bge 10740 cmpobl cmpojl cmpo; bl 10741 cmpoble cmpojle cmpo; ble 10742 cmpobne cmpojne cmpo; bne 10743 10744 10745 File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies 10746 10747 9.16 IA-64 Dependent Features 10748 ============================= 10749 10750 * Menu: 10751 10752 * IA-64 Options:: Options 10753 * IA-64 Syntax:: Syntax 10754 * IA-64 Opcodes:: Opcodes 10755 10756 10757 File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 10758 10759 9.16.1 Options 10760 -------------- 10761 10762 `-mconstant-gp' 10763 This option instructs the assembler to mark the resulting object 10764 file as using the "constant GP" model. With this model, it is 10765 assumed that the entire program uses a single global pointer (GP) 10766 value. Note that this option does not in any fashion affect the 10767 machine code emitted by the assembler. All it does is turn on the 10768 EF_IA_64_CONS_GP flag in the ELF file header. 10769 10770 `-mauto-pic' 10771 This option instructs the assembler to mark the resulting object 10772 file as using the "constant GP without function descriptor" data 10773 model. This model is like the "constant GP" model, except that it 10774 additionally does away with function descriptors. What this means 10775 is that the address of a function refers directly to the 10776 function's code entry-point. Normally, such an address would 10777 refer to a function descriptor, which contains both the code 10778 entry-point and the GP-value needed by the function. Note that 10779 this option does not in any fashion affect the machine code 10780 emitted by the assembler. All it does is turn on the 10781 EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. 10782 10783 `-milp32' 10784 `-milp64' 10785 `-mlp64' 10786 `-mp64' 10787 These options select the data model. The assembler defaults to 10788 `-mlp64' (LP64 data model). 10789 10790 `-mle' 10791 `-mbe' 10792 These options select the byte order. The `-mle' option selects 10793 little-endian byte order (default) and `-mbe' selects big-endian 10794 byte order. Note that IA-64 machine code always uses 10795 little-endian byte order. 10796 10797 `-mtune=itanium1' 10798 `-mtune=itanium2' 10799 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 10800 is ITANIUM2. 10801 10802 `-munwind-check=warning' 10803 `-munwind-check=error' 10804 These options control what the assembler will do when performing 10805 consistency checks on unwind directives. `-munwind-check=warning' 10806 will make the assembler issue a warning when an unwind directive 10807 check fails. This is the default. `-munwind-check=error' will 10808 make the assembler issue an error when an unwind directive check 10809 fails. 10810 10811 `-mhint.b=ok' 10812 `-mhint.b=warning' 10813 `-mhint.b=error' 10814 These options control what the assembler will do when the `hint.b' 10815 instruction is used. `-mhint.b=ok' will make the assembler accept 10816 `hint.b'. `-mint.b=warning' will make the assembler issue a 10817 warning when `hint.b' is used. `-mhint.b=error' will make the 10818 assembler treat `hint.b' as an error, which is the default. 10819 10820 `-x' 10821 `-xexplicit' 10822 These options turn on dependency violation checking. 10823 10824 `-xauto' 10825 This option instructs the assembler to automatically insert stop 10826 bits where necessary to remove dependency violations. This is the 10827 default mode. 10828 10829 `-xnone' 10830 This option turns off dependency violation checking. 10831 10832 `-xdebug' 10833 This turns on debug output intended to help tracking down bugs in 10834 the dependency violation checker. 10835 10836 `-xdebugn' 10837 This is a shortcut for -xnone -xdebug. 10838 10839 `-xdebugx' 10840 This is a shortcut for -xexplicit -xdebug. 10841 10842 10843 10844 File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 10845 10846 9.16.2 Syntax 10847 ------------- 10848 10849 The assembler syntax closely follows the IA-64 Assembly Language 10850 Reference Guide. 10851 10852 * Menu: 10853 10854 * IA-64-Chars:: Special Characters 10855 * IA-64-Regs:: Register Names 10856 * IA-64-Bits:: Bit Names 10857 * IA-64-Relocs:: Relocations 10858 10859 10860 File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 10861 10862 9.16.2.1 Special Characters 10863 ........................... 10864 10865 `//' is the line comment token. 10866 10867 `;' can be used instead of a newline to separate statements. 10868 10869 10870 File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 10871 10872 9.16.2.2 Register Names 10873 ....................... 10874 10875 The 128 integer registers are referred to as `rN'. The 128 10876 floating-point registers are referred to as `fN'. The 128 application 10877 registers are referred to as `arN'. The 128 control registers are 10878 referred to as `crN'. The 64 one-bit predicate registers are referred 10879 to as `pN'. The 8 branch registers are referred to as `bN'. In 10880 addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' 10881 (`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), 10882 `ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). 10883 10884 For convenience, the assembler also defines aliases for all named 10885 application and control registers. For example, `ar.bsp' refers to the 10886 register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to 10887 the end-of-interrupt register (`cr67'). 10888 10889 10890 File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 10891 10892 9.16.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 10893 ........................................................ 10894 10895 The assembler defines bit masks for each of the bits in the IA-64 10896 processor status register. For example, `psr.ic' corresponds to a 10897 value of 0x2000. These masks are primarily intended for use with the 10898 `ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere 10899 else where an integer constant is expected. 10900 10901 10902 File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 10903 10904 9.16.2.4 Relocations 10905 .................... 10906 10907 In addition to the standard IA-64 relocations, the following 10908 relocations are implemented by `as': 10909 10910 `@slotcount(V)' 10911 Convert the address offset V into a slot count. This pseudo 10912 function is available only on VMS. The expression V must be known 10913 at assembly time: it can't reference undefined symbols or symbols 10914 in different sections. 10915 10916 10917 File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 10918 10919 9.16.3 Opcodes 10920 -------------- 10921 10922 For detailed information on the IA-64 machine instruction set, see the 10923 IA-64 Architecture Handbook 10924 (http://developer.intel.com/design/itanium/arch_spec.htm). 10925 10926 10927 File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 10928 10929 9.17 IP2K Dependent Features 10930 ============================ 10931 10932 * Menu: 10933 10934 * IP2K-Opts:: IP2K Options 10935 10936 10937 File: as.info, Node: IP2K-Opts, Up: IP2K-Dependent 10938 10939 9.17.1 IP2K Options 10940 ------------------- 10941 10942 The Ubicom IP2K version of `as' has a few machine dependent options: 10943 10944 `-mip2022ext' 10945 `as' can assemble the extended IP2022 instructions, but it will 10946 only do so if this is specifically allowed via this command line 10947 option. 10948 10949 `-mip2022' 10950 This option restores the assembler's default behaviour of not 10951 permitting the extended IP2022 instructions to be assembled. 10952 10953 10954 10955 File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 10956 10957 9.18 LM32 Dependent Features 10958 ============================ 10959 10960 * Menu: 10961 10962 * LM32 Options:: Options 10963 * LM32 Syntax:: Syntax 10964 * LM32 Opcodes:: Opcodes 10965 10966 10967 File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 10968 10969 9.18.1 Options 10970 -------------- 10971 10972 `-mmultiply-enabled' 10973 Enable multiply instructions. 10974 10975 `-mdivide-enabled' 10976 Enable divide instructions. 10977 10978 `-mbarrel-shift-enabled' 10979 Enable barrel-shift instructions. 10980 10981 `-msign-extend-enabled' 10982 Enable sign extend instructions. 10983 10984 `-muser-enabled' 10985 Enable user defined instructions. 10986 10987 `-micache-enabled' 10988 Enable instruction cache related CSRs. 10989 10990 `-mdcache-enabled' 10991 Enable data cache related CSRs. 10992 10993 `-mbreak-enabled' 10994 Enable break instructions. 10995 10996 `-mall-enabled' 10997 Enable all instructions and CSRs. 10998 10999 11000 11001 File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 11002 11003 9.18.2 Syntax 11004 ------------- 11005 11006 * Menu: 11007 11008 * LM32-Regs:: Register Names 11009 * LM32-Modifiers:: Relocatable Expression Modifiers 11010 11011 11012 File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 11013 11014 9.18.2.1 Register Names 11015 ....................... 11016 11017 LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'. 11018 11019 The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp' 11020 - `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'. 11021 11022 LM32 has the following Control and Status Registers (CSRs). 11023 11024 `IE' 11025 Interrupt enable. 11026 11027 `IM' 11028 Interrupt mask. 11029 11030 `IP' 11031 Interrupt pending. 11032 11033 `ICC' 11034 Instruction cache control. 11035 11036 `DCC' 11037 Data cache control. 11038 11039 `CC' 11040 Cycle counter. 11041 11042 `CFG' 11043 Configuration. 11044 11045 `EBA' 11046 Exception base address. 11047 11048 `DC' 11049 Debug control. 11050 11051 `DEBA' 11052 Debug exception base address. 11053 11054 `JTX' 11055 JTAG transmit. 11056 11057 `JRX' 11058 JTAG receive. 11059 11060 `BP0' 11061 Breakpoint 0. 11062 11063 `BP1' 11064 Breakpoint 1. 11065 11066 `BP2' 11067 Breakpoint 2. 11068 11069 `BP3' 11070 Breakpoint 3. 11071 11072 `WP0' 11073 Watchpoint 0. 11074 11075 `WP1' 11076 Watchpoint 1. 11077 11078 `WP2' 11079 Watchpoint 2. 11080 11081 `WP3' 11082 Watchpoint 3. 11083 11084 11085 File: as.info, Node: LM32-Modifiers, Prev: LM32-Regs, Up: LM32 Syntax 11086 11087 9.18.2.2 Relocatable Expression Modifiers 11088 ......................................... 11089 11090 The assembler supports several modifiers when using relocatable 11091 addresses in LM32 instruction operands. The general syntax is the 11092 following: 11093 11094 modifier(relocatable-expression) 11095 11096 `lo' 11097 This modifier allows you to use bits 0 through 15 of an address 11098 expression as 16 bit relocatable expression. 11099 11100 `hi' 11101 This modifier allows you to use bits 16 through 23 of an address 11102 expression as 16 bit relocatable expression. 11103 11104 For example 11105 11106 ori r4, r4, lo(sym+10) 11107 orhi r4, r4, hi(sym+10) 11108 11109 `gp' 11110 This modified creates a 16-bit relocatable expression that is the 11111 offset of the symbol from the global pointer. 11112 11113 mva r4, gp(sym) 11114 11115 `got' 11116 This modifier places a symbol in the GOT and creates a 16-bit 11117 relocatable expression that is the offset into the GOT of this 11118 symbol. 11119 11120 lw r4, (gp+got(sym)) 11121 11122 `gotofflo16' 11123 This modifier allows you to use the bits 0 through 15 of an 11124 address which is an offset from the GOT. 11125 11126 `gotoffhi16' 11127 This modifier allows you to use the bits 16 through 31 of an 11128 address which is an offset from the GOT. 11129 11130 orhi r4, r4, gotoffhi16(lsym) 11131 addi r4, r4, gotofflo16(lsym) 11132 11133 11134 11135 File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 11136 11137 9.18.3 Opcodes 11138 -------------- 11139 11140 For detailed information on the LM32 machine instruction set, see 11141 `http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'. 11142 11143 `as' implements all the standard LM32 opcodes. 11144 11145 11146 File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 11147 11148 9.19 M32C Dependent Features 11149 ============================ 11150 11151 `as' can assemble code for several different members of the Renesas 11152 M32C family. Normally the default is to assemble code for the M16C 11153 microprocessor. The `-m32c' option may be used to change the default 11154 to the M32C microprocessor. 11155 11156 * Menu: 11157 11158 * M32C-Opts:: M32C Options 11159 * M32C-Modifiers:: Symbolic Operand Modifiers 11160 11161 11162 File: as.info, Node: M32C-Opts, Next: M32C-Modifiers, Up: M32C-Dependent 11163 11164 9.19.1 M32C Options 11165 ------------------- 11166 11167 The Renesas M32C version of `as' has these machine-dependent options: 11168 11169 `-m32c' 11170 Assemble M32C instructions. 11171 11172 `-m16c' 11173 Assemble M16C instructions (default). 11174 11175 `-relax' 11176 Enable support for link-time relaxations. 11177 11178 `-h-tick-hex' 11179 Support H'00 style hex constants in addition to 0x00 style. 11180 11181 11182 11183 File: as.info, Node: M32C-Modifiers, Prev: M32C-Opts, Up: M32C-Dependent 11184 11185 9.19.2 Symbolic Operand Modifiers 11186 --------------------------------- 11187 11188 The assembler supports several modifiers when using symbol addresses in 11189 M32C instruction operands. The general syntax is the following: 11190 11191 %modifier(symbol) 11192 11193 `%dsp8' 11194 `%dsp16' 11195 These modifiers override the assembler's assumptions about how big 11196 a symbol's address is. Normally, when it sees an operand like 11197 `sym[a0]' it assumes `sym' may require the widest displacement 11198 field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers 11199 tell it to assume the address will fit in an 8 or 16 bit 11200 (respectively) unsigned displacement. Note that, of course, if it 11201 doesn't actually fit you will get linker errors. Example: 11202 11203 mov.w %dsp8(sym)[a0],r1 11204 mov.b #0,%dsp8(sym)[a0] 11205 11206 `%hi8' 11207 This modifier allows you to load bits 16 through 23 of a 24 bit 11208 address into an 8 bit register. This is useful with, for example, 11209 the M16C `smovf' instruction, which expects a 20 bit address in 11210 `r1h' and `a0'. Example: 11211 11212 mov.b #%hi8(sym),r1h 11213 mov.w #%lo16(sym),a0 11214 smovf.b 11215 11216 `%lo16' 11217 Likewise, this modifier allows you to load bits 0 through 15 of a 11218 24 bit address into a 16 bit register. 11219 11220 `%hi16' 11221 This modifier allows you to load bits 16 through 31 of a 32 bit 11222 address into a 16 bit register. While the M32C family only has 24 11223 bits of address space, it does support addresses in pairs of 16 bit 11224 registers (like `a1a0' for the `lde' instruction). This modifier 11225 is for loading the upper half in such cases. Example: 11226 11227 mov.w #%hi16(sym),a1 11228 mov.w #%lo16(sym),a0 11229 ... 11230 lde.w [a1a0],r1 11231 11232 11233 11234 File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 11235 11236 9.20 M32R Dependent Features 11237 ============================ 11238 11239 * Menu: 11240 11241 * M32R-Opts:: M32R Options 11242 * M32R-Directives:: M32R Directives 11243 * M32R-Warnings:: M32R Warnings 11244 11245 11246 File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 11247 11248 9.20.1 M32R Options 11249 ------------------- 11250 11251 The Renease M32R version of `as' has a few machine dependent options: 11252 11253 `-m32rx' 11254 `as' can assemble code for several different members of the 11255 Renesas M32R family. Normally the default is to assemble code for 11256 the M32R microprocessor. This option may be used to change the 11257 default to the M32RX microprocessor, which adds some more 11258 instructions to the basic M32R instruction set, and some 11259 additional parameters to some of the original instructions. 11260 11261 `-m32r2' 11262 This option changes the target processor to the the M32R2 11263 microprocessor. 11264 11265 `-m32r' 11266 This option can be used to restore the assembler's default 11267 behaviour of assembling for the M32R microprocessor. This can be 11268 useful if the default has been changed by a previous command line 11269 option. 11270 11271 `-little' 11272 This option tells the assembler to produce little-endian code and 11273 data. The default is dependent upon how the toolchain was 11274 configured. 11275 11276 `-EL' 11277 This is a synonym for _-little_. 11278 11279 `-big' 11280 This option tells the assembler to produce big-endian code and 11281 data. 11282 11283 `-EB' 11284 This is a synonum for _-big_. 11285 11286 `-KPIC' 11287 This option specifies that the output of the assembler should be 11288 marked as position-independent code (PIC). 11289 11290 `-parallel' 11291 This option tells the assembler to attempts to combine two 11292 sequential instructions into a single, parallel instruction, where 11293 it is legal to do so. 11294 11295 `-no-parallel' 11296 This option disables a previously enabled _-parallel_ option. 11297 11298 `-no-bitinst' 11299 This option disables the support for the extended bit-field 11300 instructions provided by the M32R2. If this support needs to be 11301 re-enabled the _-bitinst_ switch can be used to restore it. 11302 11303 `-O' 11304 This option tells the assembler to attempt to optimize the 11305 instructions that it produces. This includes filling delay slots 11306 and converting sequential instructions into parallel ones. This 11307 option implies _-parallel_. 11308 11309 `-warn-explicit-parallel-conflicts' 11310 Instructs `as' to produce warning messages when questionable 11311 parallel instructions are encountered. This option is enabled by 11312 default, but `gcc' disables it when it invokes `as' directly. 11313 Questionable instructions are those whose behaviour would be 11314 different if they were executed sequentially. For example the 11315 code fragment `mv r1, r2 || mv r3, r1' produces a different result 11316 from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 11317 and then r2 into r1, whereas the later moves r2 into r1 and r3. 11318 11319 `-Wp' 11320 This is a shorter synonym for the 11321 _-warn-explicit-parallel-conflicts_ option. 11322 11323 `-no-warn-explicit-parallel-conflicts' 11324 Instructs `as' not to produce warning messages when questionable 11325 parallel instructions are encountered. 11326 11327 `-Wnp' 11328 This is a shorter synonym for the 11329 _-no-warn-explicit-parallel-conflicts_ option. 11330 11331 `-ignore-parallel-conflicts' 11332 This option tells the assembler's to stop checking parallel 11333 instructions for constraint violations. This ability is provided 11334 for hardware vendors testing chip designs and should not be used 11335 under normal circumstances. 11336 11337 `-no-ignore-parallel-conflicts' 11338 This option restores the assembler's default behaviour of checking 11339 parallel instructions to detect constraint violations. 11340 11341 `-Ip' 11342 This is a shorter synonym for the _-ignore-parallel-conflicts_ 11343 option. 11344 11345 `-nIp' 11346 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 11347 option. 11348 11349 `-warn-unmatched-high' 11350 This option tells the assembler to produce a warning message if a 11351 `.high' pseudo op is encountered without a matching `.low' pseudo 11352 op. The presence of such an unmatched pseudo op usually indicates 11353 a programming error. 11354 11355 `-no-warn-unmatched-high' 11356 Disables a previously enabled _-warn-unmatched-high_ option. 11357 11358 `-Wuh' 11359 This is a shorter synonym for the _-warn-unmatched-high_ option. 11360 11361 `-Wnuh' 11362 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 11363 11364 11365 11366 File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 11367 11368 9.20.2 M32R Directives 11369 ---------------------- 11370 11371 The Renease M32R version of `as' has a few architecture specific 11372 directives: 11373 11374 `low EXPRESSION' 11375 The `low' directive computes the value of its expression and 11376 places the lower 16-bits of the result into the immediate-field of 11377 the instruction. For example: 11378 11379 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 11380 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 11381 11382 `high EXPRESSION' 11383 The `high' directive computes the value of its expression and 11384 places the upper 16-bits of the result into the immediate-field of 11385 the instruction. For example: 11386 11387 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 11388 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 11389 11390 `shigh EXPRESSION' 11391 The `shigh' directive is very similar to the `high' directive. It 11392 also computes the value of its expression and places the upper 11393 16-bits of the result into the immediate-field of the instruction. 11394 The difference is that `shigh' also checks to see if the lower 11395 16-bits could be interpreted as a signed number, and if so it 11396 assumes that a borrow will occur from the upper-16 bits. To 11397 compensate for this the `shigh' directive pre-biases the upper 16 11398 bit value by adding one to it. For example: 11399 11400 For example: 11401 11402 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 11403 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 11404 11405 In the second example the lower 16-bits are 0x8000. If these are 11406 treated as a signed value and sign extended to 32-bits then the 11407 value becomes 0xffff8000. If this value is then added to 11408 0x00010000 then the result is 0x00008000. 11409 11410 This behaviour is to allow for the different semantics of the 11411 `or3' and `add3' instructions. The `or3' instruction treats its 11412 16-bit immediate argument as unsigned whereas the `add3' treats 11413 its 16-bit immediate as a signed value. So for example: 11414 11415 seth r0, #shigh(0x00008000) 11416 add3 r0, r0, #low(0x00008000) 11417 11418 Produces the correct result in r0, whereas: 11419 11420 seth r0, #shigh(0x00008000) 11421 or3 r0, r0, #low(0x00008000) 11422 11423 Stores 0xffff8000 into r0. 11424 11425 Note - the `shigh' directive does not know where in the assembly 11426 source code the lower 16-bits of the value are going set, so it 11427 cannot check to make sure that an `or3' instruction is being used 11428 rather than an `add3' instruction. It is up to the programmer to 11429 make sure that correct directives are used. 11430 11431 `.m32r' 11432 The directive performs a similar thing as the _-m32r_ command line 11433 option. It tells the assembler to only accept M32R instructions 11434 from now on. An instructions from later M32R architectures are 11435 refused. 11436 11437 `.m32rx' 11438 The directive performs a similar thing as the _-m32rx_ command 11439 line option. It tells the assembler to start accepting the extra 11440 instructions in the M32RX ISA as well as the ordinary M32R ISA. 11441 11442 `.m32r2' 11443 The directive performs a similar thing as the _-m32r2_ command 11444 line option. It tells the assembler to start accepting the extra 11445 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 11446 11447 `.little' 11448 The directive performs a similar thing as the _-little_ command 11449 line option. It tells the assembler to start producing 11450 little-endian code and data. This option should be used with care 11451 as producing mixed-endian binary files is fraught with danger. 11452 11453 `.big' 11454 The directive performs a similar thing as the _-big_ command line 11455 option. It tells the assembler to start producing big-endian code 11456 and data. This option should be used with care as producing 11457 mixed-endian binary files is fraught with danger. 11458 11459 11460 11461 File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 11462 11463 9.20.3 M32R Warnings 11464 -------------------- 11465 11466 There are several warning and error messages that can be produced by 11467 `as' which are specific to the M32R: 11468 11469 `output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 11470 This message is only produced if warnings for explicit parallel 11471 conflicts have been enabled. It indicates that the assembler has 11472 encountered a parallel instruction in which the destination 11473 register of the left hand instruction is used as an input register 11474 in the right hand instruction. For example in this code fragment 11475 `mv r1, r2 || neg r3, r1' register r1 is the destination of the 11476 move instruction and the input to the neg instruction. 11477 11478 `output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 11479 This message is only produced if warnings for explicit parallel 11480 conflicts have been enabled. It indicates that the assembler has 11481 encountered a parallel instruction in which the destination 11482 register of the right hand instruction is used as an input 11483 register in the left hand instruction. For example in this code 11484 fragment `mv r1, r2 || neg r2, r3' register r2 is the destination 11485 of the neg instruction and the input to the move instruction. 11486 11487 `instruction `...' is for the M32RX only' 11488 This message is produced when the assembler encounters an 11489 instruction which is only supported by the M32Rx processor, and 11490 the `-m32rx' command line flag has not been specified to allow 11491 assembly of such instructions. 11492 11493 `unknown instruction `...'' 11494 This message is produced when the assembler encounters an 11495 instruction which it does not recognize. 11496 11497 `only the NOP instruction can be issued in parallel on the m32r' 11498 This message is produced when the assembler encounters a parallel 11499 instruction which does not involve a NOP instruction and the 11500 `-m32rx' command line flag has not been specified. Only the M32Rx 11501 processor is able to execute two instructions in parallel. 11502 11503 `instruction `...' cannot be executed in parallel.' 11504 This message is produced when the assembler encounters a parallel 11505 instruction which is made up of one or two instructions which 11506 cannot be executed in parallel. 11507 11508 `Instructions share the same execution pipeline' 11509 This message is produced when the assembler encounters a parallel 11510 instruction whoes components both use the same execution pipeline. 11511 11512 `Instructions write to the same destination register.' 11513 This message is produced when the assembler encounters a parallel 11514 instruction where both components attempt to modify the same 11515 register. For example these code fragments will produce this 11516 message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, 11517 @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx 11518 r3, r4' (Both write to the condition bit) 11519 11520 11521 11522 File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 11523 11524 9.21 M680x0 Dependent Features 11525 ============================== 11526 11527 * Menu: 11528 11529 * M68K-Opts:: M680x0 Options 11530 * M68K-Syntax:: Syntax 11531 * M68K-Moto-Syntax:: Motorola Syntax 11532 * M68K-Float:: Floating Point 11533 * M68K-Directives:: 680x0 Machine Directives 11534 * M68K-opcodes:: Opcodes 11535 11536 11537 File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 11538 11539 9.21.1 M680x0 Options 11540 --------------------- 11541 11542 The Motorola 680x0 version of `as' has a few machine dependent options: 11543 11544 `-march=ARCHITECTURE' 11545 This option specifies a target architecture. The following 11546 architectures are recognized: `68000', `68010', `68020', `68030', 11547 `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and 11548 `cfv4e'. 11549 11550 `-mcpu=CPU' 11551 This option specifies a target cpu. When used in conjunction with 11552 the `-march' option, the cpu must be within the specified 11553 architecture. Also, the generic features of the architecture are 11554 used for instruction generation, rather than those of the specific 11555 chip. 11556 11557 `-m[no-]68851' 11558 `-m[no-]68881' 11559 `-m[no-]div' 11560 `-m[no-]usp' 11561 `-m[no-]float' 11562 `-m[no-]mac' 11563 `-m[no-]emac' 11564 Enable or disable various architecture specific features. If a 11565 chip or architecture by default supports an option (for instance 11566 `-march=isaaplus' includes the `-mdiv' option), explicitly 11567 disabling the option will override the default. 11568 11569 `-l' 11570 You can use the `-l' option to shorten the size of references to 11571 undefined symbols. If you do not use the `-l' option, references 11572 to undefined symbols are wide enough for a full `long' (32 bits). 11573 (Since `as' cannot know where these symbols end up, `as' can only 11574 allocate space for the linker to fill in later. Since `as' does 11575 not know how far away these symbols are, it allocates as much 11576 space as it can.) If you use this option, the references are only 11577 one word wide (16 bits). This may be useful if you want the 11578 object file to be as small as possible, and you know that the 11579 relevant symbols are always less than 17 bits away. 11580 11581 `--register-prefix-optional' 11582 For some configurations, especially those where the compiler 11583 normally does not prepend an underscore to the names of user 11584 variables, the assembler requires a `%' before any use of a 11585 register name. This is intended to let the assembler distinguish 11586 between C variables and functions named `a0' through `a7', and so 11587 on. The `%' is always accepted, but is not required for certain 11588 configurations, notably `sun3'. The `--register-prefix-optional' 11589 option may be used to permit omitting the `%' even for 11590 configurations for which it is normally required. If this is 11591 done, it will generally be impossible to refer to C variables and 11592 functions with the same names as register names. 11593 11594 `--bitwise-or' 11595 Normally the character `|' is treated as a comment character, which 11596 means that it can not be used in expressions. The `--bitwise-or' 11597 option turns `|' into a normal character. In this mode, you must 11598 either use C style comments, or start comments with a `#' character 11599 at the beginning of a line. 11600 11601 `--base-size-default-16 --base-size-default-32' 11602 If you use an addressing mode with a base register without 11603 specifying the size, `as' will normally use the full 32 bit value. 11604 For example, the addressing mode `%a0@(%d0)' is equivalent to 11605 `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to 11606 tell `as' to default to using the 16 bit value. In this case, 11607 `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the 11608 `--base-size-default-32' option to restore the default behaviour. 11609 11610 `--disp-size-default-16 --disp-size-default-32' 11611 If you use an addressing mode with a displacement, and the value 11612 of the displacement is not known, `as' will normally assume that 11613 the value is 32 bits. For example, if the symbol `disp' has not 11614 been defined, `as' will assemble the addressing mode 11615 `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use 11616 the `--disp-size-default-16' option to tell `as' to instead assume 11617 that the displacement is 16 bits. In this case, `as' will 11618 assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You 11619 may use the `--disp-size-default-32' option to restore the default 11620 behaviour. 11621 11622 `--pcrel' 11623 Always keep branches PC-relative. In the M680x0 architecture all 11624 branches are defined as PC-relative. However, on some processors 11625 they are limited to word displacements maximum. When `as' needs a 11626 long branch that is not available, it normally emits an absolute 11627 jump instead. This option disables this substitution. When this 11628 option is given and no long branches are available, only word 11629 branches will be emitted. An error message will be generated if a 11630 word branch cannot reach its target. This option has no effect on 11631 68020 and other processors that have long branches. *note Branch 11632 Improvement: M68K-Branch. 11633 11634 `-m68000' 11635 `as' can assemble code for several different members of the 11636 Motorola 680x0 family. The default depends upon how `as' was 11637 configured when it was built; normally, the default is to assemble 11638 code for the 68020 microprocessor. The following options may be 11639 used to change the default. These options control which 11640 instructions and addressing modes are permitted. The members of 11641 the 680x0 family are very similar. For detailed information about 11642 the differences, see the Motorola manuals. 11643 11644 `-m68000' 11645 `-m68ec000' 11646 `-m68hc000' 11647 `-m68hc001' 11648 `-m68008' 11649 `-m68302' 11650 `-m68306' 11651 `-m68307' 11652 `-m68322' 11653 `-m68356' 11654 Assemble for the 68000. `-m68008', `-m68302', and so on are 11655 synonyms for `-m68000', since the chips are the same from the 11656 point of view of the assembler. 11657 11658 `-m68010' 11659 Assemble for the 68010. 11660 11661 `-m68020' 11662 `-m68ec020' 11663 Assemble for the 68020. This is normally the default. 11664 11665 `-m68030' 11666 `-m68ec030' 11667 Assemble for the 68030. 11668 11669 `-m68040' 11670 `-m68ec040' 11671 Assemble for the 68040. 11672 11673 `-m68060' 11674 `-m68ec060' 11675 Assemble for the 68060. 11676 11677 `-mcpu32' 11678 `-m68330' 11679 `-m68331' 11680 `-m68332' 11681 `-m68333' 11682 `-m68334' 11683 `-m68336' 11684 `-m68340' 11685 `-m68341' 11686 `-m68349' 11687 `-m68360' 11688 Assemble for the CPU32 family of chips. 11689 11690 `-m5200' 11691 `-m5202' 11692 `-m5204' 11693 `-m5206' 11694 `-m5206e' 11695 `-m521x' 11696 `-m5249' 11697 `-m528x' 11698 `-m5307' 11699 `-m5407' 11700 `-m547x' 11701 `-m548x' 11702 `-mcfv4' 11703 `-mcfv4e' 11704 Assemble for the ColdFire family of chips. 11705 11706 `-m68881' 11707 `-m68882' 11708 Assemble 68881 floating point instructions. This is the 11709 default for the 68020, 68030, and the CPU32. The 68040 and 11710 68060 always support floating point instructions. 11711 11712 `-mno-68881' 11713 Do not assemble 68881 floating point instructions. This is 11714 the default for 68000 and the 68010. The 68040 and 68060 11715 always support floating point instructions, even if this 11716 option is used. 11717 11718 `-m68851' 11719 Assemble 68851 MMU instructions. This is the default for the 11720 68020, 68030, and 68060. The 68040 accepts a somewhat 11721 different set of MMU instructions; `-m68851' and `-m68040' 11722 should not be used together. 11723 11724 `-mno-68851' 11725 Do not assemble 68851 MMU instructions. This is the default 11726 for the 68000, 68010, and the CPU32. The 68040 accepts a 11727 somewhat different set of MMU instructions. 11728 11729 11730 File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 11731 11732 9.21.2 Syntax 11733 ------------- 11734 11735 This syntax for the Motorola 680x0 was developed at MIT. 11736 11737 The 680x0 version of `as' uses instructions names and syntax 11738 compatible with the Sun assembler. Intervening periods are ignored; 11739 for example, `movl' is equivalent to `mov.l'. 11740 11741 In the following table APC stands for any of the address registers 11742 (`%a0' through `%a7'), the program counter (`%pc'), the zero-address 11743 relative to the program counter (`%zpc'), a suppressed address register 11744 (`%za0' through `%za7'), or it may be omitted entirely. The use of 11745 SIZE means one of `w' or `l', and it may be omitted, along with the 11746 leading colon, unless a scale is also specified. The use of SCALE 11747 means one of `1', `2', `4', or `8', and it may always be omitted along 11748 with the leading colon. 11749 11750 The following addressing modes are understood: 11751 "Immediate" 11752 `#NUMBER' 11753 11754 "Data Register" 11755 `%d0' through `%d7' 11756 11757 "Address Register" 11758 `%a0' through `%a7' 11759 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 11760 also known as `%fp', the Frame Pointer. 11761 11762 "Address Register Indirect" 11763 `%a0@' through `%a7@' 11764 11765 "Address Register Postincrement" 11766 `%a0@+' through `%a7@+' 11767 11768 "Address Register Predecrement" 11769 `%a0@-' through `%a7@-' 11770 11771 "Indirect Plus Offset" 11772 `APC@(NUMBER)' 11773 11774 "Index" 11775 `APC@(NUMBER,REGISTER:SIZE:SCALE)' 11776 11777 The NUMBER may be omitted. 11778 11779 "Postindex" 11780 `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 11781 11782 The ONUMBER or the REGISTER, but not both, may be omitted. 11783 11784 "Preindex" 11785 `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 11786 11787 The NUMBER may be omitted. Omitting the REGISTER produces the 11788 Postindex addressing mode. 11789 11790 "Absolute" 11791 `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'. 11792 11793 11794 File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 11795 11796 9.21.3 Motorola Syntax 11797 ---------------------- 11798 11799 The standard Motorola syntax for this chip differs from the syntax 11800 already discussed (*note Syntax: M68K-Syntax.). `as' can accept 11801 Motorola syntax for operands, even if MIT syntax is used for other 11802 operands in the same instruction. The two kinds of syntax are fully 11803 compatible. 11804 11805 In the following table APC stands for any of the address registers 11806 (`%a0' through `%a7'), the program counter (`%pc'), the zero-address 11807 relative to the program counter (`%zpc'), or a suppressed address 11808 register (`%za0' through `%za7'). The use of SIZE means one of `w' or 11809 `l', and it may always be omitted along with the leading dot. The use 11810 of SCALE means one of `1', `2', `4', or `8', and it may always be 11811 omitted along with the leading asterisk. 11812 11813 The following additional addressing modes are understood: 11814 11815 "Address Register Indirect" 11816 `(%a0)' through `(%a7)' 11817 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 11818 also known as `%fp', the Frame Pointer. 11819 11820 "Address Register Postincrement" 11821 `(%a0)+' through `(%a7)+' 11822 11823 "Address Register Predecrement" 11824 `-(%a0)' through `-(%a7)' 11825 11826 "Indirect Plus Offset" 11827 `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. 11828 11829 The NUMBER may also appear within the parentheses, as in 11830 `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 11831 (with an address register, omitting the NUMBER produces Address 11832 Register Indirect mode). 11833 11834 "Index" 11835 `NUMBER(APC,REGISTER.SIZE*SCALE)' 11836 11837 The NUMBER may be omitted, or it may appear within the 11838 parentheses. The APC may be omitted. The REGISTER and the APC 11839 may appear in either order. If both APC and REGISTER are address 11840 registers, and the SIZE and SCALE are omitted, then the first 11841 register is taken as the base register, and the second as the 11842 index register. 11843 11844 "Postindex" 11845 `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 11846 11847 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 11848 NUMBER or the APC may be omitted, but not both. 11849 11850 "Preindex" 11851 `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 11852 11853 The NUMBER, or the APC, or the REGISTER, or any two of them, may 11854 be omitted. The ONUMBER may be omitted. The REGISTER and the APC 11855 may appear in either order. If both APC and REGISTER are address 11856 registers, and the SIZE and SCALE are omitted, then the first 11857 register is taken as the base register, and the second as the 11858 index register. 11859 11860 11861 File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 11862 11863 9.21.4 Floating Point 11864 --------------------- 11865 11866 Packed decimal (P) format floating literals are not supported. Feel 11867 free to add the code! 11868 11869 The floating point formats generated by directives are these. 11870 11871 `.float' 11872 `Single' precision floating point constants. 11873 11874 `.double' 11875 `Double' precision floating point constants. 11876 11877 `.extend' 11878 `.ldouble' 11879 `Extended' precision (`long double') floating point constants. 11880 11881 11882 File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 11883 11884 9.21.5 680x0 Machine Directives 11885 ------------------------------- 11886 11887 In order to be compatible with the Sun assembler the 680x0 assembler 11888 understands the following directives. 11889 11890 `.data1' 11891 This directive is identical to a `.data 1' directive. 11892 11893 `.data2' 11894 This directive is identical to a `.data 2' directive. 11895 11896 `.even' 11897 This directive is a special case of the `.align' directive; it 11898 aligns the output to an even byte boundary. 11899 11900 `.skip' 11901 This directive is identical to a `.space' directive. 11902 11903 `.arch NAME' 11904 Select the target architecture and extension features. Valid 11905 values for NAME are the same as for the `-march' command line 11906 option. This directive cannot be specified after any instructions 11907 have been assembled. If it is given multiple times, or in 11908 conjunction with the `-march' option, all uses must be for the 11909 same architecture and extension set. 11910 11911 `.cpu NAME' 11912 Select the target cpu. Valid valuse for NAME are the same as for 11913 the `-mcpu' command line option. This directive cannot be 11914 specified after any instructions have been assembled. If it is 11915 given multiple times, or in conjunction with the `-mopt' option, 11916 all uses must be for the same cpu. 11917 11918 11919 11920 File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 11921 11922 9.21.6 Opcodes 11923 -------------- 11924 11925 * Menu: 11926 11927 * M68K-Branch:: Branch Improvement 11928 * M68K-Chars:: Special Characters 11929 11930 11931 File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 11932 11933 9.21.6.1 Branch Improvement 11934 ........................... 11935 11936 Certain pseudo opcodes are permitted for branch instructions. They 11937 expand to the shortest branch instruction that reach the target. 11938 Generally these mnemonics are made by substituting `j' for `b' at the 11939 start of a Motorola mnemonic. 11940 11941 The following table summarizes the pseudo-operations. A `*' flags 11942 cases that are more fully described after the table: 11943 11944 Displacement 11945 +------------------------------------------------------------ 11946 | 68020 68000/10, not PC-relative OK 11947 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 11948 +------------------------------------------------------------ 11949 jbsr |bsrs bsrw bsrl jsr 11950 jra |bras braw bral jmp 11951 * jXX |bXXs bXXw bXXl bNXs;jmp 11952 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 11953 fjXX | N/A fbXXw fbXXl N/A 11954 11955 XX: condition 11956 NX: negative of condition XX 11957 `*'--see full description below 11958 `**'--this expansion mode is disallowed by `--pcrel' 11959 11960 `jbsr' 11961 `jra' 11962 These are the simplest jump pseudo-operations; they always map to 11963 one particular machine instruction, depending on the displacement 11964 to the branch target. This instruction will be a byte or word 11965 branch is that is sufficient. Otherwise, a long branch will be 11966 emitted if available. If no long branches are available and the 11967 `--pcrel' option is not given, an absolute long jump will be 11968 emitted instead. If no long branches are available, the `--pcrel' 11969 option is given, and a word branch cannot reach the target, an 11970 error message is generated. 11971 11972 In addition to standard branch operands, `as' allows these 11973 pseudo-operations to have all operands that are allowed for jsr 11974 and jmp, substituting these instructions if the operand given is 11975 not valid for a branch instruction. 11976 11977 `jXX' 11978 Here, `jXX' stands for an entire family of pseudo-operations, 11979 where XX is a conditional branch or condition-code test. The full 11980 list of pseudo-ops in this family is: 11981 jhi jls jcc jcs jne jeq jvc 11982 jvs jpl jmi jge jlt jgt jle 11983 11984 Usually, each of these pseudo-operations expands to a single branch 11985 instruction. However, if a word branch is not sufficient, no long 11986 branches are available, and the `--pcrel' option is not given, `as' 11987 issues a longer code fragment in terms of NX, the opposite 11988 condition to XX. For example, under these conditions: 11989 jXX foo 11990 gives 11991 bNXs oof 11992 jmp foo 11993 oof: 11994 11995 `dbXX' 11996 The full family of pseudo-operations covered here is 11997 dbhi dbls dbcc dbcs dbne dbeq dbvc 11998 dbvs dbpl dbmi dbge dblt dbgt dble 11999 dbf dbra dbt 12000 12001 Motorola `dbXX' instructions allow word displacements only. When 12002 a word displacement is sufficient, each of these pseudo-operations 12003 expands to the corresponding Motorola instruction. When a word 12004 displacement is not sufficient and long branches are available, 12005 when the source reads `dbXX foo', `as' emits 12006 dbXX oo1 12007 bras oo2 12008 oo1:bral foo 12009 oo2: 12010 12011 If, however, long branches are not available and the `--pcrel' 12012 option is not given, `as' emits 12013 dbXX oo1 12014 bras oo2 12015 oo1:jmp foo 12016 oo2: 12017 12018 `fjXX' 12019 This family includes 12020 fjne fjeq fjge fjlt fjgt fjle fjf 12021 fjt fjgl fjgle fjnge fjngl fjngle fjngt 12022 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 12023 fjor fjseq fjsf fjsne fjst fjueq fjuge 12024 fjugt fjule fjult fjun 12025 12026 Each of these pseudo-operations always expands to a single Motorola 12027 coprocessor branch instruction, word or long. All Motorola 12028 coprocessor branch instructions allow both word and long 12029 displacements. 12030 12031 12032 12033 File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 12034 12035 9.21.6.2 Special Characters 12036 ........................... 12037 12038 The immediate character is `#' for Sun compatibility. The line-comment 12039 character is `|' (unless the `--bitwise-or' option is used). If a `#' 12040 appears at the beginning of a line, it is treated as a comment unless 12041 it looks like `# line file', in which case it is treated normally. 12042 12043 12044 File: as.info, Node: M68HC11-Dependent, Next: MicroBlaze-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 12045 12046 9.22 M68HC11 and M68HC12 Dependent Features 12047 =========================================== 12048 12049 * Menu: 12050 12051 * M68HC11-Opts:: M68HC11 and M68HC12 Options 12052 * M68HC11-Syntax:: Syntax 12053 * M68HC11-Modifiers:: Symbolic Operand Modifiers 12054 * M68HC11-Directives:: Assembler Directives 12055 * M68HC11-Float:: Floating Point 12056 * M68HC11-opcodes:: Opcodes 12057 12058 12059 File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 12060 12061 9.22.1 M68HC11 and M68HC12 Options 12062 ---------------------------------- 12063 12064 The Motorola 68HC11 and 68HC12 version of `as' have a few machine 12065 dependent options. 12066 12067 `-m68hc11' 12068 This option switches the assembler in the M68HC11 mode. In this 12069 mode, the assembler only accepts 68HC11 operands and mnemonics. It 12070 produces code for the 68HC11. 12071 12072 `-m68hc12' 12073 This option switches the assembler in the M68HC12 mode. In this 12074 mode, the assembler also accepts 68HC12 operands and mnemonics. It 12075 produces code for the 68HC12. A few 68HC11 instructions are 12076 replaced by some 68HC12 instructions as recommended by Motorola 12077 specifications. 12078 12079 `-m68hcs12' 12080 This option switches the assembler in the M68HCS12 mode. This 12081 mode is similar to `-m68hc12' but specifies to assemble for the 12082 68HCS12 series. The only difference is on the assembling of the 12083 `movb' and `movw' instruction when a PC-relative operand is used. 12084 12085 `-mshort' 12086 This option controls the ABI and indicates to use a 16-bit integer 12087 ABI. It has no effect on the assembled instructions. This is the 12088 default. 12089 12090 `-mlong' 12091 This option controls the ABI and indicates to use a 32-bit integer 12092 ABI. 12093 12094 `-mshort-double' 12095 This option controls the ABI and indicates to use a 32-bit float 12096 ABI. This is the default. 12097 12098 `-mlong-double' 12099 This option controls the ABI and indicates to use a 64-bit float 12100 ABI. 12101 12102 `--strict-direct-mode' 12103 You can use the `--strict-direct-mode' option to disable the 12104 automatic translation of direct page mode addressing into extended 12105 mode when the instruction does not support direct mode. For 12106 example, the `clr' instruction does not support direct page mode 12107 addressing. When it is used with the direct page mode, `as' will 12108 ignore it and generate an absolute addressing. This option 12109 prevents `as' from doing this, and the wrong usage of the direct 12110 page mode will raise an error. 12111 12112 `--short-branches' 12113 The `--short-branches' option turns off the translation of 12114 relative branches into absolute branches when the branch offset is 12115 out of range. By default `as' transforms the relative branch 12116 (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', 12117 `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch 12118 when the offset is out of the -128 .. 127 range. In that case, 12119 the `bsr' instruction is translated into a `jsr', the `bra' 12120 instruction is translated into a `jmp' and the conditional 12121 branches instructions are inverted and followed by a `jmp'. This 12122 option disables these translations and `as' will generate an error 12123 if a relative branch is out of range. This option does not affect 12124 the optimization associated to the `jbra', `jbsr' and `jbXX' 12125 pseudo opcodes. 12126 12127 `--force-long-branches' 12128 The `--force-long-branches' option forces the translation of 12129 relative branches into absolute branches. This option does not 12130 affect the optimization associated to the `jbra', `jbsr' and 12131 `jbXX' pseudo opcodes. 12132 12133 `--print-insn-syntax' 12134 You can use the `--print-insn-syntax' option to obtain the syntax 12135 description of the instruction when an error is detected. 12136 12137 `--print-opcodes' 12138 The `--print-opcodes' option prints the list of all the 12139 instructions with their syntax. The first item of each line 12140 represents the instruction name and the rest of the line indicates 12141 the possible operands for that instruction. The list is printed in 12142 alphabetical order. Once the list is printed `as' exits. 12143 12144 `--generate-example' 12145 The `--generate-example' option is similar to `--print-opcodes' 12146 but it generates an example for each instruction instead. 12147 12148 12149 File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 12150 12151 9.22.2 Syntax 12152 ------------- 12153 12154 In the M68HC11 syntax, the instruction name comes first and it may be 12155 followed by one or several operands (up to three). Operands are 12156 separated by comma (`,'). In the normal mode, `as' will complain if too 12157 many operands are specified for a given instruction. In the MRI mode 12158 (turned on with `-M' option), it will treat them as comments. Example: 12159 12160 inx 12161 lda #23 12162 bset 2,x #4 12163 brclr *bot #8 foo 12164 12165 The following addressing modes are understood for 68HC11 and 68HC12: 12166 "Immediate" 12167 `#NUMBER' 12168 12169 "Address Register" 12170 `NUMBER,X', `NUMBER,Y' 12171 12172 The NUMBER may be omitted in which case 0 is assumed. 12173 12174 "Direct Addressing mode" 12175 `*SYMBOL', or `*DIGITS' 12176 12177 "Absolute" 12178 `SYMBOL', or `DIGITS' 12179 12180 The M68HC12 has other more complex addressing modes. All of them are 12181 supported and they are represented below: 12182 12183 "Constant Offset Indexed Addressing Mode" 12184 `NUMBER,REG' 12185 12186 The NUMBER may be omitted in which case 0 is assumed. The 12187 register can be either `X', `Y', `SP' or `PC'. The assembler will 12188 use the smaller post-byte definition according to the constant 12189 value (5-bit constant offset, 9-bit constant offset or 16-bit 12190 constant offset). If the constant is not known by the assembler 12191 it will use the 16-bit constant offset post-byte and the value 12192 will be resolved at link time. 12193 12194 "Offset Indexed Indirect" 12195 `[NUMBER,REG]' 12196 12197 The register can be either `X', `Y', `SP' or `PC'. 12198 12199 "Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 12200 `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' 12201 12202 The number must be in the range `-8'..`+8' and must not be 0. The 12203 register can be either `X', `Y', `SP' or `PC'. 12204 12205 "Accumulator Offset" 12206 `ACC,REG' 12207 12208 The accumulator register can be either `A', `B' or `D'. The 12209 register can be either `X', `Y', `SP' or `PC'. 12210 12211 "Accumulator D offset indexed-indirect" 12212 `[D,REG]' 12213 12214 The register can be either `X', `Y', `SP' or `PC'. 12215 12216 12217 For example: 12218 12219 ldab 1024,sp 12220 ldd [10,x] 12221 orab 3,+x 12222 stab -2,y- 12223 ldx a,pc 12224 sty [d,sp] 12225 12226 12227 File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 12228 12229 9.22.3 Symbolic Operand Modifiers 12230 --------------------------------- 12231 12232 The assembler supports several modifiers when using symbol addresses in 12233 68HC11 and 68HC12 instruction operands. The general syntax is the 12234 following: 12235 12236 %modifier(symbol) 12237 12238 `%addr' 12239 This modifier indicates to the assembler and linker to use the 12240 16-bit physical address corresponding to the symbol. This is 12241 intended to be used on memory window systems to map a symbol in 12242 the memory bank window. If the symbol is in a memory expansion 12243 part, the physical address corresponds to the symbol address 12244 within the memory bank window. If the symbol is not in a memory 12245 expansion part, this is the symbol address (using or not using the 12246 %addr modifier has no effect in that case). 12247 12248 `%page' 12249 This modifier indicates to use the memory page number corresponding 12250 to the symbol. If the symbol is in a memory expansion part, its 12251 page number is computed by the linker as a number used to map the 12252 page containing the symbol in the memory bank window. If the 12253 symbol is not in a memory expansion part, the page number is 0. 12254 12255 `%hi' 12256 This modifier indicates to use the 8-bit high part of the physical 12257 address of the symbol. 12258 12259 `%lo' 12260 This modifier indicates to use the 8-bit low part of the physical 12261 address of the symbol. 12262 12263 12264 For example a 68HC12 call to a function `foo_example' stored in 12265 memory expansion part could be written as follows: 12266 12267 call %addr(foo_example),%page(foo_example) 12268 12269 and this is equivalent to 12270 12271 call foo_example 12272 12273 And for 68HC11 it could be written as follows: 12274 12275 ldab #%page(foo_example) 12276 stab _page_switch 12277 jsr %addr(foo_example) 12278 12279 12280 File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 12281 12282 9.22.4 Assembler Directives 12283 --------------------------- 12284 12285 The 68HC11 and 68HC12 version of `as' have the following specific 12286 assembler directives: 12287 12288 `.relax' 12289 The relax directive is used by the `GNU Compiler' to emit a 12290 specific relocation to mark a group of instructions for linker 12291 relaxation. The sequence of instructions within the group must be 12292 known to the linker so that relaxation can be performed. 12293 12294 `.mode [mshort|mlong|mshort-double|mlong-double]' 12295 This directive specifies the ABI. It overrides the `-mshort', 12296 `-mlong', `-mshort-double' and `-mlong-double' options. 12297 12298 `.far SYMBOL' 12299 This directive marks the symbol as a `far' symbol meaning that it 12300 uses a `call/rtc' calling convention as opposed to `jsr/rts'. 12301 During a final link, the linker will identify references to the 12302 `far' symbol and will verify the proper calling convention. 12303 12304 `.interrupt SYMBOL' 12305 This directive marks the symbol as an interrupt entry point. This 12306 information is then used by the debugger to correctly unwind the 12307 frame across interrupts. 12308 12309 `.xrefb SYMBOL' 12310 This directive is defined for compatibility with the 12311 `Specification for Motorola 8 and 16-Bit Assembly Language Input 12312 Standard' and is ignored. 12313 12314 12315 12316 File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 12317 12318 9.22.5 Floating Point 12319 --------------------- 12320 12321 Packed decimal (P) format floating literals are not supported. Feel 12322 free to add the code! 12323 12324 The floating point formats generated by directives are these. 12325 12326 `.float' 12327 `Single' precision floating point constants. 12328 12329 `.double' 12330 `Double' precision floating point constants. 12331 12332 `.extend' 12333 `.ldouble' 12334 `Extended' precision (`long double') floating point constants. 12335 12336 12337 File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 12338 12339 9.22.6 Opcodes 12340 -------------- 12341 12342 * Menu: 12343 12344 * M68HC11-Branch:: Branch Improvement 12345 12346 12347 File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 12348 12349 9.22.6.1 Branch Improvement 12350 ........................... 12351 12352 Certain pseudo opcodes are permitted for branch instructions. They 12353 expand to the shortest branch instruction that reach the target. 12354 Generally these mnemonics are made by prepending `j' to the start of 12355 Motorola mnemonic. These pseudo opcodes are not affected by the 12356 `--short-branches' or `--force-long-branches' options. 12357 12358 The following table summarizes the pseudo-operations. 12359 12360 Displacement Width 12361 +-------------------------------------------------------------+ 12362 | Options | 12363 | --short-branches --force-long-branches | 12364 +--------------------------+----------------------------------+ 12365 Op |BYTE WORD | BYTE WORD | 12366 +--------------------------+----------------------------------+ 12367 bsr | bsr <pc-rel> <error> | jsr <abs> | 12368 bra | bra <pc-rel> <error> | jmp <abs> | 12369 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 12370 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 12371 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 12372 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 12373 | jmp <abs> | | 12374 +--------------------------+----------------------------------+ 12375 XX: condition 12376 NX: negative of condition XX 12377 12378 `jbsr' 12379 `jbra' 12380 These are the simplest jump pseudo-operations; they always map to 12381 one particular machine instruction, depending on the displacement 12382 to the branch target. 12383 12384 `jbXX' 12385 Here, `jbXX' stands for an entire family of pseudo-operations, 12386 where XX is a conditional branch or condition-code test. The full 12387 list of pseudo-ops in this family is: 12388 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 12389 jbcs jbne jblt jble jbls jbvc jbmi 12390 12391 For the cases of non-PC relative displacements and long 12392 displacements, `as' issues a longer code fragment in terms of NX, 12393 the opposite condition to XX. For example, for the non-PC 12394 relative case: 12395 jbXX foo 12396 gives 12397 bNXs oof 12398 jmp foo 12399 oof: 12400 12401 12402 12403 File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 12404 12405 9.23 MicroBlaze Dependent Features 12406 ================================== 12407 12408 The Xilinx MicroBlaze processor family includes several variants, 12409 all using the same core instruction set. This chapter covers features 12410 of the GNU assembler that are specific to the MicroBlaze architecture. 12411 For details about the MicroBlaze instruction set, please see the 12412 `MicroBlaze Processor Reference Guide (UG081)' available at 12413 www.xilinx.com. 12414 12415 * Menu: 12416 12417 * MicroBlaze Directives:: Directives for MicroBlaze Processors. 12418 12419 12420 File: as.info, Node: MicroBlaze Directives, Up: MicroBlaze-Dependent 12421 12422 9.23.1 Directives 12423 ----------------- 12424 12425 A number of assembler directives are available for MicroBlaze. 12426 12427 `.data8 EXPRESSION,...' 12428 This directive is an alias for `.byte'. Each expression is 12429 assembled into an eight-bit value. 12430 12431 `.data16 EXPRESSION,...' 12432 This directive is an alias for `.hword'. Each expression is 12433 assembled into an 16-bit value. 12434 12435 `.data32 EXPRESSION,...' 12436 This directive is an alias for `.word'. Each expression is 12437 assembled into an 32-bit value. 12438 12439 `.ent NAME[,LABEL]' 12440 This directive is an alias for `.func' denoting the start of 12441 function NAME at (optional) LABEL. 12442 12443 `.end NAME[,LABEL]' 12444 This directive is an alias for `.endfunc' denoting the end of 12445 function NAME. 12446 12447 `.gpword LABEL,...' 12448 This directive is an alias for `.rva'. The resolved address of 12449 LABEL is stored in the data section. 12450 12451 `.weakext LABEL' 12452 Declare that LABEL is a weak external symbol. 12453 12454 `.rodata' 12455 Switch to .rodata section. Equivalent to `.section .rodata' 12456 12457 `.sdata2' 12458 Switch to .sdata2 section. Equivalent to `.section .sdata2' 12459 12460 `.sdata' 12461 Switch to .sdata section. Equivalent to `.section .sdata' 12462 12463 `.bss' 12464 Switch to .bss section. Equivalent to `.section .bss' 12465 12466 `.sbss' 12467 Switch to .sbss section. Equivalent to `.section .sbss' 12468 12469 12470 File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 12471 12472 9.24 MIPS Dependent Features 12473 ============================ 12474 12475 GNU `as' for MIPS architectures supports several different MIPS 12476 processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 12477 information about the MIPS instruction set, see `MIPS RISC 12478 Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 12479 of MIPS assembly conventions, see "Appendix D: Assembly Language 12480 Programming" in the same work. 12481 12482 * Menu: 12483 12484 * MIPS Opts:: Assembler options 12485 * MIPS Object:: ECOFF object code 12486 * MIPS Stabs:: Directives for debugging information 12487 * MIPS ISA:: Directives to override the ISA level 12488 * MIPS symbol sizes:: Directives to override the size of symbols 12489 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions 12490 * MIPS insn:: Directive to mark data as an instruction 12491 * MIPS option stack:: Directives to save and restore options 12492 * MIPS ASE instruction generation overrides:: Directives to control 12493 generation of MIPS ASE instructions 12494 * MIPS floating-point:: Directives to override floating-point options 12495 12496 12497 File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent 12498 12499 9.24.1 Assembler options 12500 ------------------------ 12501 12502 The MIPS configurations of GNU `as' support these special options: 12503 12504 `-G NUM' 12505 This option sets the largest size of an object that can be 12506 referenced implicitly with the `gp' register. It is only accepted 12507 for targets that use ECOFF format. The default value is 8. 12508 12509 `-EB' 12510 `-EL' 12511 Any MIPS configuration of `as' can select big-endian or 12512 little-endian output at run time (unlike the other GNU development 12513 tools, which must be configured for one or the other). Use `-EB' 12514 to select big-endian output, and `-EL' for little-endian. 12515 12516 `-KPIC' 12517 Generate SVR4-style PIC. This option tells the assembler to 12518 generate SVR4-style position-independent macro expansions. It 12519 also tells the assembler to mark the output file as PIC. 12520 12521 `-mvxworks-pic' 12522 Generate VxWorks PIC. This option tells the assembler to generate 12523 VxWorks-style position-independent macro expansions. 12524 12525 `-mips1' 12526 `-mips2' 12527 `-mips3' 12528 `-mips4' 12529 `-mips5xo' 12530 `-mips32' 12531 `-mips32r2' 12532 `-mips64' 12533 `-mips64r2' 12534 Generate code for a particular MIPS Instruction Set Architecture 12535 level. `-mips1' corresponds to the R2000 and R3000 processors, 12536 `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, 12537 and `-mips4' to the R8000 and R10000 processors. `-mips5', 12538 `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to 12539 generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 12540 RELEASE 2 ISA processors, respectively. You can also switch 12541 instruction sets during the assembly; see *note Directives to 12542 override the ISA level: MIPS ISA. 12543 12544 `-mgp32' 12545 `-mfp32' 12546 Some macros have different expansions for 32-bit and 64-bit 12547 registers. The register sizes are normally inferred from the ISA 12548 and ABI, but these flags force a certain group of registers to be 12549 treated as 32 bits wide at all times. `-mgp32' controls the size 12550 of general-purpose registers and `-mfp32' controls the size of 12551 floating-point registers. 12552 12553 The `.set gp=32' and `.set fp=32' directives allow the size of 12554 registers to be changed for parts of an object. The default value 12555 is restored by `.set gp=default' and `.set fp=default'. 12556 12557 On some MIPS variants there is a 32-bit mode flag; when this flag 12558 is set, 64-bit instructions generate a trap. Also, some 32-bit 12559 OSes only save the 32-bit registers on a context switch, so it is 12560 essential never to use the 64-bit registers. 12561 12562 `-mgp64' 12563 `-mfp64' 12564 Assume that 64-bit registers are available. This is provided in 12565 the interests of symmetry with `-mgp32' and `-mfp32'. 12566 12567 The `.set gp=64' and `.set fp=64' directives allow the size of 12568 registers to be changed for parts of an object. The default value 12569 is restored by `.set gp=default' and `.set fp=default'. 12570 12571 `-mips16' 12572 `-no-mips16' 12573 Generate code for the MIPS 16 processor. This is equivalent to 12574 putting `.set mips16' at the start of the assembly file. 12575 `-no-mips16' turns off this option. 12576 12577 `-msmartmips' 12578 `-mno-smartmips' 12579 Enables the SmartMIPS extensions to the MIPS32 instruction set, 12580 which provides a number of new instructions which target smartcard 12581 and cryptographic applications. This is equivalent to putting 12582 `.set smartmips' at the start of the assembly file. 12583 `-mno-smartmips' turns off this option. 12584 12585 `-mips3d' 12586 `-no-mips3d' 12587 Generate code for the MIPS-3D Application Specific Extension. 12588 This tells the assembler to accept MIPS-3D instructions. 12589 `-no-mips3d' turns off this option. 12590 12591 `-mdmx' 12592 `-no-mdmx' 12593 Generate code for the MDMX Application Specific Extension. This 12594 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 12595 off this option. 12596 12597 `-mdsp' 12598 `-mno-dsp' 12599 Generate code for the DSP Release 1 Application Specific Extension. 12600 This tells the assembler to accept DSP Release 1 instructions. 12601 `-mno-dsp' turns off this option. 12602 12603 `-mdspr2' 12604 `-mno-dspr2' 12605 Generate code for the DSP Release 2 Application Specific Extension. 12606 This option implies -mdsp. This tells the assembler to accept DSP 12607 Release 2 instructions. `-mno-dspr2' turns off this option. 12608 12609 `-mmt' 12610 `-mno-mt' 12611 Generate code for the MT Application Specific Extension. This 12612 tells the assembler to accept MT instructions. `-mno-mt' turns 12613 off this option. 12614 12615 `-mfix7000' 12616 `-mno-fix7000' 12617 Cause nops to be inserted if the read of the destination register 12618 of an mfhi or mflo instruction occurs in the following two 12619 instructions. 12620 12621 `-mfix-loongson2f-jump' 12622 `-mno-fix-loongson2f-jump' 12623 Eliminate instruction fetch from outside 256M region to work 12624 around the Loongson2F `jump' instructions. Without it, under 12625 extreme cases, the kernel may crash. The issue has been solved in 12626 latest processor batches, but this fix has no side effect to them. 12627 12628 `-mfix-loongson2f-nop' 12629 `-mno-fix-loongson2f-nop' 12630 Replace nops by `or at,at,zero' to work around the Loongson2F 12631 `nop' errata. Without it, under extreme cases, cpu might 12632 deadlock. The issue has been solved in latest loongson2f batches, 12633 but this fix has no side effect to them. 12634 12635 `-mfix-vr4120' 12636 `-mno-fix-vr4120' 12637 Insert nops to work around certain VR4120 errata. This option is 12638 intended to be used on GCC-generated code: it is not designed to 12639 catch all problems in hand-written assembler code. 12640 12641 `-mfix-vr4130' 12642 `-mno-fix-vr4130' 12643 Insert nops to work around the VR4130 `mflo'/`mfhi' errata. 12644 12645 `-mfix-24k' 12646 `-no-mfix-24k' 12647 Insert nops to work around the 24K `eret'/`deret' errata. 12648 12649 `-mfix-cn63xxp1' 12650 `-mno-fix-cn63xxp1' 12651 Replace `pref' hints 0 - 4 and 6 - 24 with hint 28 to work around 12652 certain CN63XXP1 errata. 12653 12654 `-m4010' 12655 `-no-m4010' 12656 Generate code for the LSI R4010 chip. This tells the assembler to 12657 accept the R4010 specific instructions (`addciu', `ffc', etc.), 12658 and to not schedule `nop' instructions around accesses to the `HI' 12659 and `LO' registers. `-no-m4010' turns off this option. 12660 12661 `-m4650' 12662 `-no-m4650' 12663 Generate code for the MIPS R4650 chip. This tells the assembler 12664 to accept the `mad' and `madu' instruction, and to not schedule 12665 `nop' instructions around accesses to the `HI' and `LO' registers. 12666 `-no-m4650' turns off this option. 12667 12668 `-m3900' 12669 `-no-m3900' 12670 `-m4100' 12671 `-no-m4100' 12672 For each option `-mNNNN', generate code for the MIPS RNNNN chip. 12673 This tells the assembler to accept instructions specific to that 12674 chip, and to schedule for that chip's hazards. 12675 12676 `-march=CPU' 12677 Generate code for a particular MIPS cpu. It is exactly equivalent 12678 to `-mCPU', except that there are more value of CPU understood. 12679 Valid CPU value are: 12680 12681 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 12682 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 12683 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 12684 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 12685 4kep, 4ksd, m4k, m4kp, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 12686 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc, 12687 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 12688 1004kf1_1, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, 12689 loongson2f, octeon, xlr 12690 12691 For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms 12692 for `Nf1_1'. These values are deprecated. 12693 12694 `-mtune=CPU' 12695 Schedule and tune for a particular MIPS cpu. Valid CPU values are 12696 identical to `-march=CPU'. 12697 12698 `-mabi=ABI' 12699 Record which ABI the source code uses. The recognized arguments 12700 are: `32', `n32', `o64', `64' and `eabi'. 12701 12702 `-msym32' 12703 `-mno-sym32' 12704 Equivalent to adding `.set sym32' or `.set nosym32' to the 12705 beginning of the assembler input. *Note MIPS symbol sizes::. 12706 12707 `-nocpp' 12708 This option is ignored. It is accepted for command-line 12709 compatibility with other assemblers, which use it to turn off C 12710 style preprocessing. With GNU `as', there is no need for 12711 `-nocpp', because the GNU assembler itself never runs the C 12712 preprocessor. 12713 12714 `-msoft-float' 12715 `-mhard-float' 12716 Disable or enable floating-point instructions. Note that by 12717 default floating-point instructions are always allowed even with 12718 CPU targets that don't have support for these instructions. 12719 12720 `-msingle-float' 12721 `-mdouble-float' 12722 Disable or enable double-precision floating-point operations. Note 12723 that by default double-precision floating-point operations are 12724 always allowed even with CPU targets that don't have support for 12725 these operations. 12726 12727 `--construct-floats' 12728 `--no-construct-floats' 12729 The `--no-construct-floats' option disables the construction of 12730 double width floating point constants by loading the two halves of 12731 the value into the two single width floating point registers that 12732 make up the double width register. This feature is useful if the 12733 processor support the FR bit in its status register, and this bit 12734 is known (by the programmer) to be set. This bit prevents the 12735 aliasing of the double width register by the single width 12736 registers. 12737 12738 By default `--construct-floats' is selected, allowing construction 12739 of these floating point constants. 12740 12741 `--trap' 12742 `--no-break' 12743 `as' automatically macro expands certain division and 12744 multiplication instructions to check for overflow and division by 12745 zero. This option causes `as' to generate code to take a trap 12746 exception rather than a break exception when an error is detected. 12747 The trap instructions are only supported at Instruction Set 12748 Architecture level 2 and higher. 12749 12750 `--break' 12751 `--no-trap' 12752 Generate code to take a break exception rather than a trap 12753 exception when an error is detected. This is the default. 12754 12755 `-mpdr' 12756 `-mno-pdr' 12757 Control generation of `.pdr' sections. Off by default on IRIX, on 12758 elsewhere. 12759 12760 `-mshared' 12761 `-mno-shared' 12762 When generating code using the Unix calling conventions (selected 12763 by `-KPIC' or `-mcall_shared'), gas will normally generate code 12764 which can go into a shared library. The `-mno-shared' option 12765 tells gas to generate code which uses the calling convention, but 12766 can not go into a shared library. The resulting code is slightly 12767 more efficient. This option only affects the handling of the 12768 `.cpload' and `.cpsetup' pseudo-ops. 12769 12770 12771 File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent 12772 12773 9.24.2 MIPS ECOFF object code 12774 ----------------------------- 12775 12776 Assembling for a MIPS ECOFF target supports some additional sections 12777 besides the usual `.text', `.data' and `.bss'. The additional sections 12778 are `.rdata', used for read-only data, `.sdata', used for small data, 12779 and `.sbss', used for small common objects. 12780 12781 When assembling for ECOFF, the assembler uses the `$gp' (`$28') 12782 register to form the address of a "small object". Any object in the 12783 `.sdata' or `.sbss' sections is considered "small" in this sense. For 12784 external objects, or for objects in the `.bss' section, you can use the 12785 `gcc' `-G' option to control the size of objects addressed via `$gp'; 12786 the default value is 8, meaning that a reference to any object eight 12787 bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from 12788 using the `$gp' register on the basis of object size (but the assembler 12789 uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of 12790 an object in the `.bss' section is set by the `.comm' or `.lcomm' 12791 directive that defines it. The size of an external object may be set 12792 with the `.extern' directive. For example, `.extern sym,4' declares 12793 that the object at `sym' is 4 bytes in length, whie leaving `sym' 12794 otherwise undefined. 12795 12796 Using small ECOFF objects requires linker support, and assumes that 12797 the `$gp' register is correctly initialized (normally done 12798 automatically by the startup code). MIPS ECOFF assembly code must not 12799 modify the `$gp' register. 12800 12801 12802 File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent 12803 12804 9.24.3 Directives for debugging information 12805 ------------------------------------------- 12806 12807 MIPS ECOFF `as' supports several directives used for generating 12808 debugging information which are not support by traditional MIPS 12809 assemblers. These are `.def', `.endef', `.dim', `.file', `.scl', 12810 `.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'. 12811 The debugging information generated by the three `.stab' directives can 12812 only be read by GDB, not by traditional MIPS debuggers (this 12813 enhancement is required to fully support C++ debugging). These 12814 directives are primarily used by compilers, not assembly language 12815 programmers! 12816 12817 12818 File: as.info, Node: MIPS symbol sizes, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 12819 12820 9.24.4 Directives to override the size of symbols 12821 ------------------------------------------------- 12822 12823 The n64 ABI allows symbols to have any 64-bit value. Although this 12824 provides a great deal of flexibility, it means that some macros have 12825 much longer expansions than their 32-bit counterparts. For example, 12826 the non-PIC expansion of `dla $4,sym' is usually: 12827 12828 lui $4,%highest(sym) 12829 lui $1,%hi(sym) 12830 daddiu $4,$4,%higher(sym) 12831 daddiu $1,$1,%lo(sym) 12832 dsll32 $4,$4,0 12833 daddu $4,$4,$1 12834 12835 whereas the 32-bit expansion is simply: 12836 12837 lui $4,%hi(sym) 12838 daddiu $4,$4,%lo(sym) 12839 12840 n64 code is sometimes constructed in such a way that all symbolic 12841 constants are known to have 32-bit values, and in such cases, it's 12842 preferable to use the 32-bit expansion instead of the 64-bit expansion. 12843 12844 You can use the `.set sym32' directive to tell the assembler that, 12845 from this point on, all expressions of the form `SYMBOL' or `SYMBOL + 12846 OFFSET' have 32-bit values. For example: 12847 12848 .set sym32 12849 dla $4,sym 12850 lw $4,sym+16 12851 sw $4,sym+0x8000($4) 12852 12853 will cause the assembler to treat `sym', `sym+16' and `sym+0x8000' 12854 as 32-bit values. The handling of non-symbolic addresses is not 12855 affected. 12856 12857 The directive `.set nosym32' ends a `.set sym32' block and reverts 12858 to the normal behavior. It is also possible to change the symbol size 12859 using the command-line options `-msym32' and `-mno-sym32'. 12860 12861 These options and directives are always accepted, but at present, 12862 they have no effect for anything other than n64. 12863 12864 12865 File: as.info, Node: MIPS ISA, Next: MIPS symbol sizes, Prev: MIPS Stabs, Up: MIPS-Dependent 12866 12867 9.24.5 Directives to override the ISA level 12868 ------------------------------------------- 12869 12870 GNU `as' supports an additional directive to change the MIPS 12871 Instruction Set Architecture level on the fly: `.set mipsN'. N should 12872 be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other 12873 than 0 make the assembler accept instructions for the corresponding ISA 12874 level, from that point on in the assembly. `.set mipsN' affects not 12875 only which instructions are permitted, but also how certain macros are 12876 expanded. `.set mips0' restores the ISA level to its original level: 12877 either the level you selected with command line options, or the default 12878 for your configuration. You can use this feature to permit specific 12879 MIPS3 instructions while assembling in 32 bit mode. Use this directive 12880 with care! 12881 12882 The `.set arch=CPU' directive provides even finer control. It 12883 changes the effective CPU target and allows the assembler to use 12884 instructions specific to a particular CPU. All CPUs supported by the 12885 `-march' command line option are also selectable by this directive. 12886 The original value is restored by `.set arch=default'. 12887 12888 The directive `.set mips16' puts the assembler into MIPS 16 mode, in 12889 which it will assemble instructions for the MIPS 16 processor. Use 12890 `.set nomips16' to return to normal 32 bit mode. 12891 12892 Traditional MIPS assemblers do not support this directive. 12893 12894 12895 File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS symbol sizes, Up: MIPS-Dependent 12896 12897 9.24.6 Directives for extending MIPS 16 bit instructions 12898 -------------------------------------------------------- 12899 12900 By default, MIPS 16 instructions are automatically extended to 32 bits 12901 when necessary. The directive `.set noautoextend' will turn this off. 12902 When `.set noautoextend' is in effect, any 32 bit instruction must be 12903 explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The 12904 directive `.set autoextend' may be used to once again automatically 12905 extend instructions when necessary. 12906 12907 This directive is only meaningful when in MIPS 16 mode. Traditional 12908 MIPS assemblers do not support this directive. 12909 12910 12911 File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent 12912 12913 9.24.7 Directive to mark data as an instruction 12914 ----------------------------------------------- 12915 12916 The `.insn' directive tells `as' that the following data is actually 12917 instructions. This makes a difference in MIPS 16 mode: when loading 12918 the address of a label which precedes instructions, `as' automatically 12919 adds 1 to the value, so that jumping to the loaded address will do the 12920 right thing. 12921 12922 The `.global' and `.globl' directives supported by `as' will by 12923 default mark the symbol as pointing to a region of data not code. This 12924 means that, for example, any instructions following such a symbol will 12925 not be disassembled by `objdump' as it will regard them as data. To 12926 change this behaviour an optional section name can be placed after the 12927 symbol name in the `.global' directive. If this section exists and is 12928 known to be a code section, then the symbol will be marked as poiting at 12929 code not data. Ie the syntax for the directive is: 12930 12931 `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', 12932 12933 Here is a short example: 12934 12935 .global foo .text, bar, baz .data 12936 foo: 12937 nop 12938 bar: 12939 .word 0x0 12940 baz: 12941 .word 0x1 12942 12943 12944 File: as.info, Node: MIPS option stack, Next: MIPS ASE instruction generation overrides, Prev: MIPS insn, Up: MIPS-Dependent 12945 12946 9.24.8 Directives to save and restore options 12947 --------------------------------------------- 12948 12949 The directives `.set push' and `.set pop' may be used to save and 12950 restore the current settings for all the options which are controlled 12951 by `.set'. The `.set push' directive saves the current settings on a 12952 stack. The `.set pop' directive pops the stack and restores the 12953 settings. 12954 12955 These directives can be useful inside an macro which must change an 12956 option such as the ISA level or instruction reordering but does not want 12957 to change the state of the code which invoked the macro. 12958 12959 Traditional MIPS assemblers do not support these directives. 12960 12961 12962 File: as.info, Node: MIPS ASE instruction generation overrides, Next: MIPS floating-point, Prev: MIPS option stack, Up: MIPS-Dependent 12963 12964 9.24.9 Directives to control generation of MIPS ASE instructions 12965 ---------------------------------------------------------------- 12966 12967 The directive `.set mips3d' makes the assembler accept instructions 12968 from the MIPS-3D Application Specific Extension from that point on in 12969 the assembly. The `.set nomips3d' directive prevents MIPS-3D 12970 instructions from being accepted. 12971 12972 The directive `.set smartmips' makes the assembler accept 12973 instructions from the SmartMIPS Application Specific Extension to the 12974 MIPS32 ISA from that point on in the assembly. The `.set nosmartmips' 12975 directive prevents SmartMIPS instructions from being accepted. 12976 12977 The directive `.set mdmx' makes the assembler accept instructions 12978 from the MDMX Application Specific Extension from that point on in the 12979 assembly. The `.set nomdmx' directive prevents MDMX instructions from 12980 being accepted. 12981 12982 The directive `.set dsp' makes the assembler accept instructions 12983 from the DSP Release 1 Application Specific Extension from that point 12984 on in the assembly. The `.set nodsp' directive prevents DSP Release 1 12985 instructions from being accepted. 12986 12987 The directive `.set dspr2' makes the assembler accept instructions 12988 from the DSP Release 2 Application Specific Extension from that point 12989 on in the assembly. This dirctive implies `.set dsp'. The `.set 12990 nodspr2' directive prevents DSP Release 2 instructions from being 12991 accepted. 12992 12993 The directive `.set mt' makes the assembler accept instructions from 12994 the MT Application Specific Extension from that point on in the 12995 assembly. The `.set nomt' directive prevents MT instructions from 12996 being accepted. 12997 12998 Traditional MIPS assemblers do not support these directives. 12999 13000 13001 File: as.info, Node: MIPS floating-point, Prev: MIPS ASE instruction generation overrides, Up: MIPS-Dependent 13002 13003 9.24.10 Directives to override floating-point options 13004 ----------------------------------------------------- 13005 13006 The directives `.set softfloat' and `.set hardfloat' provide finer 13007 control of disabling and enabling float-point instructions. These 13008 directives always override the default (that hard-float instructions 13009 are accepted) or the command-line options (`-msoft-float' and 13010 `-mhard-float'). 13011 13012 The directives `.set singlefloat' and `.set doublefloat' provide 13013 finer control of disabling and enabling double-precision float-point 13014 operations. These directives always override the default (that 13015 double-precision operations are accepted) or the command-line options 13016 (`-msingle-float' and `-mdouble-float'). 13017 13018 Traditional MIPS assemblers do not support these directives. 13019 13020 13021 File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 13022 13023 9.25 MMIX Dependent Features 13024 ============================ 13025 13026 * Menu: 13027 13028 * MMIX-Opts:: Command-line Options 13029 * MMIX-Expand:: Instruction expansion 13030 * MMIX-Syntax:: Syntax 13031 * MMIX-mmixal:: Differences to `mmixal' syntax and semantics 13032 13033 13034 File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 13035 13036 9.25.1 Command-line Options 13037 --------------------------- 13038 13039 The MMIX version of `as' has some machine-dependent options. 13040 13041 When `--fixed-special-register-names' is specified, only the register 13042 names specified in *note MMIX-Regs:: are recognized in the instructions 13043 `PUT' and `GET'. 13044 13045 You can use the `--globalize-symbols' to make all symbols global. 13046 This option is useful when splitting up a `mmixal' program into several 13047 files. 13048 13049 The `--gnu-syntax' turns off most syntax compatibility with 13050 `mmixal'. Its usability is currently doubtful. 13051 13052 The `--relax' option is not fully supported, but will eventually make 13053 the object file prepared for linker relaxation. 13054 13055 If you want to avoid inadvertently calling a predefined symbol and 13056 would rather get an error, for example when using `as' with a compiler 13057 or other machine-generated code, specify `--no-predefined-syms'. This 13058 turns off built-in predefined definitions of all such symbols, 13059 including rounding-mode symbols, segment symbols, `BIT' symbols, and 13060 `TRAP' symbols used in `mmix' "system calls". It also turns off 13061 predefined special-register names, except when used in `PUT' and `GET' 13062 instructions. 13063 13064 By default, some instructions are expanded to fit the size of the 13065 operand or an external symbol (*note MMIX-Expand::). By passing 13066 `--no-expand', no such expansion will be done, instead causing errors 13067 at link time if the operand does not fit. 13068 13069 The `mmixal' documentation (*note mmixsite::) specifies that global 13070 registers allocated with the `GREG' directive (*note MMIX-greg::) and 13071 initialized to the same non-zero value, will refer to the same global 13072 register. This isn't strictly enforceable in `as' since the final 13073 addresses aren't known until link-time, but it will do an effort unless 13074 the `--no-merge-gregs' option is specified. (Register merging isn't 13075 yet implemented in `ld'.) 13076 13077 `as' will warn every time it expands an instruction to fit an 13078 operand unless the option `-x' is specified. It is believed that this 13079 behaviour is more useful than just mimicking `mmixal''s behaviour, in 13080 which instructions are only expanded if the `-x' option is specified, 13081 and assembly fails otherwise, when an instruction needs to be expanded. 13082 It needs to be kept in mind that `mmixal' is both an assembler and 13083 linker, while `as' will expand instructions that at link stage can be 13084 contracted. (Though linker relaxation isn't yet implemented in `ld'.) 13085 The option `-x' also imples `--linker-allocated-gregs'. 13086 13087 If instruction expansion is enabled, `as' can expand a `PUSHJ' 13088 instruction into a series of instructions. The shortest expansion is 13089 to not expand it, but just mark the call as redirectable to a stub, 13090 which `ld' creates at link-time, but only if the original `PUSHJ' 13091 instruction is found not to reach the target. The stub consists of the 13092 necessary instructions to form a jump to the target. This happens if 13093 `as' can assert that the `PUSHJ' instruction can reach such a stub. 13094 The option `--no-pushj-stubs' disables this shorter expansion, and the 13095 longer series of instructions is then created at assembly-time. The 13096 option `--no-stubs' is a synonym, intended for compatibility with 13097 future releases, where generation of stubs for other instructions may 13098 be implemented. 13099 13100 Usually a two-operand-expression (*note GREG-base::) without a 13101 matching `GREG' directive is treated as an error by `as'. When the 13102 option `--linker-allocated-gregs' is in effect, they are instead passed 13103 through to the linker, which will allocate as many global registers as 13104 is needed. 13105 13106 13107 File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 13108 13109 9.25.2 Instruction expansion 13110 ---------------------------- 13111 13112 When `as' encounters an instruction with an operand that is either not 13113 known or does not fit the operand size of the instruction, `as' (and 13114 `ld') will expand the instruction into a sequence of instructions 13115 semantically equivalent to the operand fitting the instruction. 13116 Expansion will take place for the following instructions: 13117 13118 `GETA' 13119 Expands to a sequence of four instructions: `SETL', `INCML', 13120 `INCMH' and `INCH'. The operand must be a multiple of four. 13121 13122 Conditional branches 13123 A branch instruction is turned into a branch with the complemented 13124 condition and prediction bit over five instructions; four 13125 instructions setting `$255' to the operand value, which like with 13126 `GETA' must be a multiple of four, and a final `GO $255,$255,0'. 13127 13128 `PUSHJ' 13129 Similar to expansion for conditional branches; four instructions 13130 set `$255' to the operand value, followed by a `PUSHGO 13131 $255,$255,0'. 13132 13133 `JMP' 13134 Similar to conditional branches and `PUSHJ'. The final instruction 13135 is `GO $255,$255,0'. 13136 13137 The linker `ld' is expected to shrink these expansions for code 13138 assembled with `--relax' (though not currently implemented). 13139 13140 13141 File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 13142 13143 9.25.3 Syntax 13144 ------------- 13145 13146 The assembly syntax is supposed to be upward compatible with that 13147 described in Sections 1.3 and 1.4 of `The Art of Computer Programming, 13148 Volume 1'. Draft versions of those chapters as well as other MMIX 13149 information is located at 13150 `http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code 13151 examples from the mmixal package located there should work unmodified 13152 when assembled and linked as single files, with a few noteworthy 13153 exceptions (*note MMIX-mmixal::). 13154 13155 Before an instruction is emitted, the current location is aligned to 13156 the next four-byte boundary. If a label is defined at the beginning of 13157 the line, its value will be the aligned value. 13158 13159 In addition to the traditional hex-prefix `0x', a hexadecimal number 13160 can also be specified by the prefix character `#'. 13161 13162 After all operands to an MMIX instruction or directive have been 13163 specified, the rest of the line is ignored, treated as a comment. 13164 13165 * Menu: 13166 13167 * MMIX-Chars:: Special Characters 13168 * MMIX-Symbols:: Symbols 13169 * MMIX-Regs:: Register Names 13170 * MMIX-Pseudos:: Assembler Directives 13171 13172 13173 File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 13174 13175 9.25.3.1 Special Characters 13176 ........................... 13177 13178 The characters `*' and `#' are line comment characters; each start a 13179 comment at the beginning of a line, but only at the beginning of a 13180 line. A `#' prefixes a hexadecimal number if found elsewhere on a line. 13181 13182 Two other characters, `%' and `!', each start a comment anywhere on 13183 the line. Thus you can't use the `modulus' and `not' operators in 13184 expressions normally associated with these two characters. 13185 13186 A `;' is a line separator, treated as a new-line, so separate 13187 instructions can be specified on a single line. 13188 13189 13190 File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 13191 13192 9.25.3.2 Symbols 13193 ................ 13194 13195 The character `:' is permitted in identifiers. There are two 13196 exceptions to it being treated as any other symbol character: if a 13197 symbol begins with `:', it means that the symbol is in the global 13198 namespace and that the current prefix should not be prepended to that 13199 symbol (*note MMIX-prefix::). The `:' is then not considered part of 13200 the symbol. For a symbol in the label position (first on a line), a `:' 13201 at the end of a symbol is silently stripped off. A label is permitted, 13202 but not required, to be followed by a `:', as with many other assembly 13203 formats. 13204 13205 The character `@' in an expression, is a synonym for `.', the 13206 current location. 13207 13208 In addition to the common forward and backward local symbol formats 13209 (*note Symbol Names::), they can be specified with upper-case `B' and 13210 `F', as in `8B' and `9F'. A local label defined for the current 13211 position is written with a `H' appended to the number: 13212 3H LDB $0,$1,2 13213 This and traditional local-label formats cannot be mixed: a label 13214 must be defined and referred to using the same format. 13215 13216 There's a minor caveat: just as for the ordinary local symbols, the 13217 local symbols are translated into ordinary symbols using control 13218 characters are to hide the ordinal number of the symbol. 13219 Unfortunately, these symbols are not translated back in error messages. 13220 Thus you may see confusing error messages when local symbols are used. 13221 Control characters `\003' (control-C) and `\004' (control-D) are used 13222 for the MMIX-specific local-symbol syntax. 13223 13224 The symbol `Main' is handled specially; it is always global. 13225 13226 By defining the symbols `__.MMIX.start..text' and 13227 `__.MMIX.start..data', the address of respectively the `.text' and 13228 `.data' segments of the final program can be defined, though when 13229 linking more than one object file, the code or data in the object file 13230 containing the symbol is not guaranteed to be start at that position; 13231 just the final executable. *Note MMIX-loc::. 13232 13233 13234 File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 13235 13236 9.25.3.3 Register names 13237 ....................... 13238 13239 Local and global registers are specified as `$0' to `$255'. The 13240 recognized special register names are `rJ', `rA', `rB', `rC', `rD', 13241 `rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', 13242 `rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', 13243 `rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special 13244 register names. 13245 13246 Local and global symbols can be equated to register names and used in 13247 place of ordinary registers. 13248 13249 Similarly for special registers, local and global symbols can be 13250 used. Also, symbols equated from numbers and constant expressions are 13251 allowed in place of a special register, except when either of the 13252 options `--no-predefined-syms' and `--fixed-special-register-names' are 13253 specified. Then only the special register names above are allowed for 13254 the instructions having a special register operand; `GET' and `PUT'. 13255 13256 13257 File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 13258 13259 9.25.3.4 Assembler Directives 13260 ............................. 13261 13262 `LOC' 13263 The `LOC' directive sets the current location to the value of the 13264 operand field, which may include changing sections. If the 13265 operand is a constant, the section is set to either `.data' if the 13266 value is `0x2000000000000000' or larger, else it is set to `.text'. 13267 Within a section, the current location may only be changed to 13268 monotonically higher addresses. A LOC expression must be a 13269 previously defined symbol or a "pure" constant. 13270 13271 An example, which sets the label PREV to the current location, and 13272 updates the current location to eight bytes forward: 13273 prev LOC @+8 13274 13275 When a LOC has a constant as its operand, a symbol 13276 `__.MMIX.start..text' or `__.MMIX.start..data' is defined 13277 depending on the address as mentioned above. Each such symbol is 13278 interpreted as special by the linker, locating the section at that 13279 address. Note that if multiple files are linked, the first object 13280 file with that section will be mapped to that address (not 13281 necessarily the file with the LOC definition). 13282 13283 `LOCAL' 13284 Example: 13285 LOCAL external_symbol 13286 LOCAL 42 13287 .local asymbol 13288 13289 This directive-operation generates a link-time assertion that the 13290 operand does not correspond to a global register. The operand is 13291 an expression that at link-time resolves to a register symbol or a 13292 number. A number is treated as the register having that number. 13293 There is one restriction on the use of this directive: the 13294 pseudo-directive must be placed in a section with contents, code 13295 or data. 13296 13297 `IS' 13298 The `IS' directive: 13299 asymbol IS an_expression 13300 sets the symbol `asymbol' to `an_expression'. A symbol may not be 13301 set more than once using this directive. Local labels may be set 13302 using this directive, for example: 13303 5H IS @+4 13304 13305 `GREG' 13306 This directive reserves a global register, gives it an initial 13307 value and optionally gives it a symbolic name. Some examples: 13308 13309 areg GREG 13310 breg GREG data_value 13311 GREG data_buffer 13312 .greg creg, another_data_value 13313 13314 The symbolic register name can be used in place of a (non-special) 13315 register. If a value isn't provided, it defaults to zero. Unless 13316 the option `--no-merge-gregs' is specified, non-zero registers 13317 allocated with this directive may be eliminated by `as'; another 13318 register with the same value used in its place. Any of the 13319 instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', 13320 `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', 13321 `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', 13322 `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can 13323 have a value nearby an initial value in place of its second and 13324 third operands. Here, "nearby" is defined as within the range 13325 0...255 from the initial value of such an allocated register. 13326 13327 buffer1 BYTE 0,0,0,0,0 13328 buffer2 BYTE 0,0,0,0,0 13329 ... 13330 GREG buffer1 13331 LDOU $42,buffer2 13332 In the example above, the `Y' field of the `LDOUI' instruction 13333 (LDOU with a constant Z) will be replaced with the global register 13334 allocated for `buffer1', and the `Z' field will have the value 5, 13335 the offset from `buffer1' to `buffer2'. The result is equivalent 13336 to this code: 13337 buffer1 BYTE 0,0,0,0,0 13338 buffer2 BYTE 0,0,0,0,0 13339 ... 13340 tmpreg GREG buffer1 13341 LDOU $42,tmpreg,(buffer2-buffer1) 13342 13343 Global registers allocated with this directive are allocated in 13344 order higher-to-lower within a file. Other than that, the exact 13345 order of register allocation and elimination is undefined. For 13346 example, the order is undefined when more than one file with such 13347 directives are linked together. With the options `-x' and 13348 `--linker-allocated-gregs', `GREG' directives for two-operand 13349 cases like the one mentioned above can be omitted. Sufficient 13350 global registers will then be allocated by the linker. 13351 13352 `BYTE' 13353 The `BYTE' directive takes a series of operands separated by a 13354 comma. If an operand is a string (*note Strings::), each 13355 character of that string is emitted as a byte. Other operands 13356 must be constant expressions without forward references, in the 13357 range 0...255. If you need operands having expressions with 13358 forward references, use `.byte' (*note Byte::). An operand can be 13359 omitted, defaulting to a zero value. 13360 13361 `WYDE' 13362 `TETRA' 13363 `OCTA' 13364 The directives `WYDE', `TETRA' and `OCTA' emit constants of two, 13365 four and eight bytes size respectively. Before anything else 13366 happens for the directive, the current location is aligned to the 13367 respective constant-size boundary. If a label is defined at the 13368 beginning of the line, its value will be that after the alignment. 13369 A single operand can be omitted, defaulting to a zero value 13370 emitted for the directive. Operands can be expressed as strings 13371 (*note Strings::), in which case each character in the string is 13372 emitted as a separate constant of the size indicated by the 13373 directive. 13374 13375 `PREFIX' 13376 The `PREFIX' directive sets a symbol name prefix to be prepended to 13377 all symbols (except local symbols, *note MMIX-Symbols::), that are 13378 not prefixed with `:', until the next `PREFIX' directive. Such 13379 prefixes accumulate. For example, 13380 PREFIX a 13381 PREFIX b 13382 c IS 0 13383 defines a symbol `abc' with the value 0. 13384 13385 `BSPEC' 13386 `ESPEC' 13387 A pair of `BSPEC' and `ESPEC' directives delimit a section of 13388 special contents (without specified semantics). Example: 13389 BSPEC 42 13390 TETRA 1,2,3 13391 ESPEC 13392 The single operand to `BSPEC' must be number in the range 0...255. 13393 The `BSPEC' number 80 is used by the GNU binutils implementation. 13394 13395 13396 File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 13397 13398 9.25.4 Differences to `mmixal' 13399 ------------------------------ 13400 13401 The binutils `as' and `ld' combination has a few differences in 13402 function compared to `mmixal' (*note mmixsite::). 13403 13404 The replacement of a symbol with a GREG-allocated register (*note 13405 GREG-base::) is not handled the exactly same way in `as' as in 13406 `mmixal'. This is apparent in the `mmixal' example file `inout.mms', 13407 where different registers with different offsets, eventually yielding 13408 the same address, are used in the first instruction. This type of 13409 difference should however not affect the function of any program unless 13410 it has specific assumptions about the allocated register number. 13411 13412 Line numbers (in the `mmo' object format) are currently not 13413 supported. 13414 13415 Expression operator precedence is not that of mmixal: operator 13416 precedence is that of the C programming language. It's recommended to 13417 use parentheses to explicitly specify wanted operator precedence 13418 whenever more than one type of operators are used. 13419 13420 The serialize unary operator `&', the fractional division operator 13421 `//', the logical not operator `!' and the modulus operator `%' are not 13422 available. 13423 13424 Symbols are not global by default, unless the option 13425 `--globalize-symbols' is passed. Use the `.global' directive to 13426 globalize symbols (*note Global::). 13427 13428 Operand syntax is a bit stricter with `as' than `mmixal'. For 13429 example, you can't say `addu 1,2,3', instead you must write `addu 13430 $1,$2,3'. 13431 13432 You can't LOC to a lower address than those already visited (i.e., 13433 "backwards"). 13434 13435 A LOC directive must come before any emitted code. 13436 13437 Predefined symbols are visible as file-local symbols after use. (In 13438 the ELF file, that is--the linked mmo file has no notion of a file-local 13439 symbol.) 13440 13441 Some mapping of constant expressions to sections in LOC expressions 13442 is attempted, but that functionality is easily confused and should be 13443 avoided unless compatibility with `mmixal' is required. A LOC 13444 expression to `0x2000000000000000' or higher, maps to the `.data' 13445 section and lower addresses map to the `.text' section (*note 13446 MMIX-loc::). 13447 13448 The code and data areas are each contiguous. Sparse programs with 13449 far-away LOC directives will take up the same amount of space as a 13450 contiguous program with zeros filled in the gaps between the LOC 13451 directives. If you need sparse programs, you might try and get the 13452 wanted effect with a linker script and splitting up the code parts into 13453 sections (*note Section::). Assembly code for this, to be compatible 13454 with `mmixal', would look something like: 13455 .if 0 13456 LOC away_expression 13457 .else 13458 .section away,"ax" 13459 .fi 13460 `as' will not execute the LOC directive and `mmixal' ignores the 13461 lines with `.'. This construct can be used generally to help 13462 compatibility. 13463 13464 Symbols can't be defined twice-not even to the same value. 13465 13466 Instruction mnemonics are recognized case-insensitive, though the 13467 `IS' and `GREG' pseudo-operations must be specified in upper-case 13468 characters. 13469 13470 There's no unicode support. 13471 13472 The following is a list of programs in `mmix.tar.gz', available at 13473 `http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last 13474 checked with the version dated 2001-08-25 (md5sum 13475 c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do 13476 not assemble with `as': 13477 13478 `silly.mms' 13479 LOC to a previous address. 13480 13481 `sim.mms' 13482 Redefines symbol `Done'. 13483 13484 `test.mms' 13485 Uses the serial operator `&'. 13486 13487 13488 File: as.info, Node: MSP430-Dependent, Next: SH-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 13489 13490 9.26 MSP 430 Dependent Features 13491 =============================== 13492 13493 * Menu: 13494 13495 * MSP430 Options:: Options 13496 * MSP430 Syntax:: Syntax 13497 * MSP430 Floating Point:: Floating Point 13498 * MSP430 Directives:: MSP 430 Machine Directives 13499 * MSP430 Opcodes:: Opcodes 13500 * MSP430 Profiling Capability:: Profiling Capability 13501 13502 13503 File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 13504 13505 9.26.1 Options 13506 -------------- 13507 13508 `-m' 13509 select the mpu arch. Currently has no effect. 13510 13511 `-mP' 13512 enables polymorph instructions handler. 13513 13514 `-mQ' 13515 enables relaxation at assembly time. DANGEROUS! 13516 13517 13518 13519 File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 13520 13521 9.26.2 Syntax 13522 ------------- 13523 13524 * Menu: 13525 13526 * MSP430-Macros:: Macros 13527 * MSP430-Chars:: Special Characters 13528 * MSP430-Regs:: Register Names 13529 * MSP430-Ext:: Assembler Extensions 13530 13531 13532 File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 13533 13534 9.26.2.1 Macros 13535 ............... 13536 13537 The macro syntax used on the MSP 430 is like that described in the MSP 13538 430 Family Assembler Specification. Normal `as' macros should still 13539 work. 13540 13541 Additional built-in macros are: 13542 13543 `llo(exp)' 13544 Extracts least significant word from 32-bit expression 'exp'. 13545 13546 `lhi(exp)' 13547 Extracts most significant word from 32-bit expression 'exp'. 13548 13549 `hlo(exp)' 13550 Extracts 3rd word from 64-bit expression 'exp'. 13551 13552 `hhi(exp)' 13553 Extracts 4rd word from 64-bit expression 'exp'. 13554 13555 13556 They normally being used as an immediate source operand. 13557 mov #llo(1), r10 ; == mov #1, r10 13558 mov #lhi(1), r10 ; == mov #0, r10 13559 13560 13561 File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 13562 13563 9.26.2.2 Special Characters 13564 ........................... 13565 13566 `;' is the line comment character. 13567 13568 The character `$' in jump instructions indicates current location and 13569 implemented only for TI syntax compatibility. 13570 13571 13572 File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 13573 13574 9.26.2.3 Register Names 13575 ....................... 13576 13577 General-purpose registers are represented by predefined symbols of the 13578 form `rN' (for global registers), where N represents a number between 13579 `0' and `15'. The leading letters may be in either upper or lower 13580 case; for example, `r13' and `R7' are both valid register names. 13581 13582 Register names `PC', `SP' and `SR' cannot be used as register names 13583 and will be treated as variables. Use `r0', `r1', and `r2' instead. 13584 13585 13586 File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 13587 13588 9.26.2.4 Assembler Extensions 13589 ............................. 13590 13591 `@rN' 13592 As destination operand being treated as `0(rn)' 13593 13594 `0(rN)' 13595 As source operand being treated as `@rn' 13596 13597 `jCOND +N' 13598 Skips next N bytes followed by jump instruction and equivalent to 13599 `jCOND $+N+2' 13600 13601 13602 Also, there are some instructions, which cannot be found in other 13603 assemblers. These are branch instructions, which has different opcodes 13604 upon jump distance. They all got PC relative addressing mode. 13605 13606 `beq label' 13607 A polymorph instruction which is `jeq label' in case if jump 13608 distance within allowed range for cpu's jump instruction. If not, 13609 this unrolls into a sequence of 13610 jne $+6 13611 br label 13612 13613 `bne label' 13614 A polymorph instruction which is `jne label' or `jeq +4; br label' 13615 13616 `blt label' 13617 A polymorph instruction which is `jl label' or `jge +4; br label' 13618 13619 `bltn label' 13620 A polymorph instruction which is `jn label' or `jn +2; jmp +4; br 13621 label' 13622 13623 `bltu label' 13624 A polymorph instruction which is `jlo label' or `jhs +2; br label' 13625 13626 `bge label' 13627 A polymorph instruction which is `jge label' or `jl +4; br label' 13628 13629 `bgeu label' 13630 A polymorph instruction which is `jhs label' or `jlo +4; br label' 13631 13632 `bgt label' 13633 A polymorph instruction which is `jeq +2; jge label' or `jeq +6; 13634 jl +4; br label' 13635 13636 `bgtu label' 13637 A polymorph instruction which is `jeq +2; jhs label' or `jeq +6; 13638 jlo +4; br label' 13639 13640 `bleu label' 13641 A polymorph instruction which is `jeq label; jlo label' or `jeq 13642 +2; jhs +4; br label' 13643 13644 `ble label' 13645 A polymorph instruction which is `jeq label; jl label' or `jeq 13646 +2; jge +4; br label' 13647 13648 `jump label' 13649 A polymorph instruction which is `jmp label' or `br label' 13650 13651 13652 File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 13653 13654 9.26.3 Floating Point 13655 --------------------- 13656 13657 The MSP 430 family uses IEEE 32-bit floating-point numbers. 13658 13659 13660 File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 13661 13662 9.26.4 MSP 430 Machine Directives 13663 --------------------------------- 13664 13665 `.file' 13666 This directive is ignored; it is accepted for compatibility with 13667 other MSP 430 assemblers. 13668 13669 _Warning:_ in other versions of the GNU assembler, `.file' is 13670 used for the directive called `.app-file' in the MSP 430 13671 support. 13672 13673 `.line' 13674 This directive is ignored; it is accepted for compatibility with 13675 other MSP 430 assemblers. 13676 13677 `.arch' 13678 Currently this directive is ignored; it is accepted for 13679 compatibility with other MSP 430 assemblers. 13680 13681 `.profiler' 13682 This directive instructs assembler to add new profile entry to the 13683 object file. 13684 13685 13686 13687 File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 13688 13689 9.26.5 Opcodes 13690 -------------- 13691 13692 `as' implements all the standard MSP 430 opcodes. No additional 13693 pseudo-instructions are needed on this family. 13694 13695 For information on the 430 machine instruction set, see `MSP430 13696 User's Manual, document slau049d', Texas Instrument, Inc. 13697 13698 13699 File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 13700 13701 9.26.6 Profiling Capability 13702 --------------------------- 13703 13704 It is a performance hit to use gcc's profiling approach for this tiny 13705 target. Even more - jtag hardware facility does not perform any 13706 profiling functions. However we've got gdb's built-in simulator where 13707 we can do anything. 13708 13709 We define new section `.profiler' which holds all profiling 13710 information. We define new pseudo operation `.profiler' which will 13711 instruct assembler to add new profile entry to the object file. Profile 13712 should take place at the present address. 13713 13714 Pseudo operation format: 13715 13716 `.profiler flags,function_to_profile [, cycle_corrector, extra]' 13717 13718 where: 13719 13720 `flags' is a combination of the following characters: 13721 13722 `s' 13723 function entry 13724 13725 `x' 13726 function exit 13727 13728 `i' 13729 function is in init section 13730 13731 `f' 13732 function is in fini section 13733 13734 `l' 13735 library call 13736 13737 `c' 13738 libc standard call 13739 13740 `d' 13741 stack value demand 13742 13743 `I' 13744 interrupt service routine 13745 13746 `P' 13747 prologue start 13748 13749 `p' 13750 prologue end 13751 13752 `E' 13753 epilogue start 13754 13755 `e' 13756 epilogue end 13757 13758 `j' 13759 long jump / sjlj unwind 13760 13761 `a' 13762 an arbitrary code fragment 13763 13764 `t' 13765 extra parameter saved (a constant value like frame size) 13766 13767 `function_to_profile' 13768 a function address 13769 13770 `cycle_corrector' 13771 a value which should be added to the cycle counter, zero if 13772 omitted. 13773 13774 `extra' 13775 any extra parameter, zero if omitted. 13776 13777 13778 For example: 13779 .global fxx 13780 .type fxx,@function 13781 fxx: 13782 .LFrameOffset_fxx=0x08 13783 .profiler "scdP", fxx ; function entry. 13784 ; we also demand stack value to be saved 13785 push r11 13786 push r10 13787 push r9 13788 push r8 13789 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 13790 ; (this is a prologue end) 13791 ; note, that spare var filled with 13792 ; the farme size 13793 mov r15,r8 13794 ... 13795 .profiler cdE,fxx ; check stack 13796 pop r8 13797 pop r9 13798 pop r10 13799 pop r11 13800 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 13801 ret ; cause 'ret' insn takes 3 cycles 13802 13803 13804 File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies 13805 13806 9.27 PDP-11 Dependent Features 13807 ============================== 13808 13809 * Menu: 13810 13811 * PDP-11-Options:: Options 13812 * PDP-11-Pseudos:: Assembler Directives 13813 * PDP-11-Syntax:: DEC Syntax versus BSD Syntax 13814 * PDP-11-Mnemonics:: Instruction Naming 13815 * PDP-11-Synthetic:: Synthetic Instructions 13816 13817 13818 File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 13819 13820 9.27.1 Options 13821 -------------- 13822 13823 The PDP-11 version of `as' has a rich set of machine dependent options. 13824 13825 9.27.1.1 Code Generation Options 13826 ................................ 13827 13828 `-mpic | -mno-pic' 13829 Generate position-independent (or position-dependent) code. 13830 13831 The default is to generate position-independent code. 13832 13833 9.27.1.2 Instruction Set Extension Options 13834 .......................................... 13835 13836 These options enables or disables the use of extensions over the base 13837 line instruction set as introduced by the first PDP-11 CPU: the KA11. 13838 Most options come in two variants: a `-m'EXTENSION that enables 13839 EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. 13840 13841 The default is to enable all extensions. 13842 13843 `-mall | -mall-extensions' 13844 Enable all instruction set extensions. 13845 13846 `-mno-extensions' 13847 Disable all instruction set extensions. 13848 13849 `-mcis | -mno-cis' 13850 Enable (or disable) the use of the commercial instruction set, 13851 which consists of these instructions: `ADDNI', `ADDN', `ADDPI', 13852 `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC', 13853 `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI', 13854 `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL', 13855 `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI', 13856 `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC', 13857 `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI', 13858 `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'. 13859 13860 `-mcsm | -mno-csm' 13861 Enable (or disable) the use of the `CSM' instruction. 13862 13863 `-meis | -mno-eis' 13864 Enable (or disable) the use of the extended instruction set, which 13865 consists of these instructions: `ASHC', `ASH', `DIV', `MARK', 13866 `MUL', `RTT', `SOB' `SXT', and `XOR'. 13867 13868 `-mfis | -mkev11' 13869 `-mno-fis | -mno-kev11' 13870 Enable (or disable) the use of the KEV11 floating-point 13871 instructions: `FADD', `FDIV', `FMUL', and `FSUB'. 13872 13873 `-mfpp | -mfpu | -mfp-11' 13874 `-mno-fpp | -mno-fpu | -mno-fp-11' 13875 Enable (or disable) the use of FP-11 floating-point instructions: 13876 `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF', 13877 `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF', 13878 `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST', 13879 `SUBF', and `TSTF'. 13880 13881 `-mlimited-eis | -mno-limited-eis' 13882 Enable (or disable) the use of the limited extended instruction 13883 set: `MARK', `RTT', `SOB', `SXT', and `XOR'. 13884 13885 The -mno-limited-eis options also implies -mno-eis. 13886 13887 `-mmfpt | -mno-mfpt' 13888 Enable (or disable) the use of the `MFPT' instruction. 13889 13890 `-mmultiproc | -mno-multiproc' 13891 Enable (or disable) the use of multiprocessor instructions: 13892 `TSTSET' and `WRTLCK'. 13893 13894 `-mmxps | -mno-mxps' 13895 Enable (or disable) the use of the `MFPS' and `MTPS' instructions. 13896 13897 `-mspl | -mno-spl' 13898 Enable (or disable) the use of the `SPL' instruction. 13899 13900 Enable (or disable) the use of the microcode instructions: `LDUB', 13901 `MED', and `XFC'. 13902 13903 9.27.1.3 CPU Model Options 13904 .......................... 13905 13906 These options enable the instruction set extensions supported by a 13907 particular CPU, and disables all other extensions. 13908 13909 `-mka11' 13910 KA11 CPU. Base line instruction set only. 13911 13912 `-mkb11' 13913 KB11 CPU. Enable extended instruction set and `SPL'. 13914 13915 `-mkd11a' 13916 KD11-A CPU. Enable limited extended instruction set. 13917 13918 `-mkd11b' 13919 KD11-B CPU. Base line instruction set only. 13920 13921 `-mkd11d' 13922 KD11-D CPU. Base line instruction set only. 13923 13924 `-mkd11e' 13925 KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'. 13926 13927 `-mkd11f | -mkd11h | -mkd11q' 13928 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended 13929 instruction set, `MFPS', and `MTPS'. 13930 13931 `-mkd11k' 13932 KD11-K CPU. Enable extended instruction set, `LDUB', `MED', 13933 `MFPS', `MFPT', `MTPS', and `XFC'. 13934 13935 `-mkd11z' 13936 KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS', 13937 `MFPT', `MTPS', and `SPL'. 13938 13939 `-mf11' 13940 F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and 13941 `MTPS'. 13942 13943 `-mj11' 13944 J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT', 13945 `MTPS', `SPL', `TSTSET', and `WRTLCK'. 13946 13947 `-mt11' 13948 T11 CPU. Enable limited extended instruction set, `MFPS', and 13949 `MTPS'. 13950 13951 9.27.1.4 Machine Model Options 13952 .............................. 13953 13954 These options enable the instruction set extensions supported by a 13955 particular machine model, and disables all other extensions. 13956 13957 `-m11/03' 13958 Same as `-mkd11f'. 13959 13960 `-m11/04' 13961 Same as `-mkd11d'. 13962 13963 `-m11/05 | -m11/10' 13964 Same as `-mkd11b'. 13965 13966 `-m11/15 | -m11/20' 13967 Same as `-mka11'. 13968 13969 `-m11/21' 13970 Same as `-mt11'. 13971 13972 `-m11/23 | -m11/24' 13973 Same as `-mf11'. 13974 13975 `-m11/34' 13976 Same as `-mkd11e'. 13977 13978 `-m11/34a' 13979 Ame as `-mkd11e' `-mfpp'. 13980 13981 `-m11/35 | -m11/40' 13982 Same as `-mkd11a'. 13983 13984 `-m11/44' 13985 Same as `-mkd11z'. 13986 13987 `-m11/45 | -m11/50 | -m11/55 | -m11/70' 13988 Same as `-mkb11'. 13989 13990 `-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 13991 Same as `-mj11'. 13992 13993 `-m11/60' 13994 Same as `-mkd11k'. 13995 13996 13997 File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 13998 13999 9.27.2 Assembler Directives 14000 --------------------------- 14001 14002 The PDP-11 version of `as' has a few machine dependent assembler 14003 directives. 14004 14005 `.bss' 14006 Switch to the `bss' section. 14007 14008 `.even' 14009 Align the location counter to an even number. 14010 14011 14012 File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 14013 14014 9.27.3 PDP-11 Assembly Language Syntax 14015 -------------------------------------- 14016 14017 `as' supports both DEC syntax and BSD syntax. The only difference is 14018 that in DEC syntax, a `#' character is used to denote an immediate 14019 constants, while in BSD syntax the character for this purpose is `$'. 14020 14021 general-purpose registers are named `r0' through `r7'. Mnemonic 14022 alternatives for `r6' and `r7' are `sp' and `pc', respectively. 14023 14024 Floating-point registers are named `ac0' through `ac3', or 14025 alternatively `fr0' through `fr3'. 14026 14027 Comments are started with a `#' or a `/' character, and extend to 14028 the end of the line. (FIXME: clash with immediates?) 14029 14030 14031 File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 14032 14033 9.27.4 Instruction Naming 14034 ------------------------- 14035 14036 Some instructions have alternative names. 14037 14038 `BCC' 14039 `BHIS' 14040 14041 `BCS' 14042 `BLO' 14043 14044 `L2DR' 14045 `L2D' 14046 14047 `L3DR' 14048 `L3D' 14049 14050 `SYS' 14051 `TRAP' 14052 14053 14054 File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 14055 14056 9.27.5 Synthetic Instructions 14057 ----------------------------- 14058 14059 The `JBR' and `J'CC synthetic instructions are not supported yet. 14060 14061 14062 File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 14063 14064 9.28 picoJava Dependent Features 14065 ================================ 14066 14067 * Menu: 14068 14069 * PJ Options:: Options 14070 14071 14072 File: as.info, Node: PJ Options, Up: PJ-Dependent 14073 14074 9.28.1 Options 14075 -------------- 14076 14077 `as' has two additional command-line options for the picoJava 14078 architecture. 14079 `-ml' 14080 This option selects little endian data output. 14081 14082 `-mb' 14083 This option selects big endian data output. 14084 14085 14086 File: as.info, Node: PPC-Dependent, Next: RX-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 14087 14088 9.29 PowerPC Dependent Features 14089 =============================== 14090 14091 * Menu: 14092 14093 * PowerPC-Opts:: Options 14094 * PowerPC-Pseudo:: PowerPC Assembler Directives 14095 14096 14097 File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 14098 14099 9.29.1 Options 14100 -------------- 14101 14102 The PowerPC chip family includes several successive levels, using the 14103 same core instruction set, but including a few additional instructions 14104 at each level. There are exceptions to this however. For details on 14105 what instructions each variant supports, please see the chip's 14106 architecture reference manual. 14107 14108 The following table lists all available PowerPC options. 14109 14110 `-mpwrx | -mpwr2' 14111 Generate code for POWER/2 (RIOS2). 14112 14113 `-mpwr' 14114 Generate code for POWER (RIOS1) 14115 14116 `-m601' 14117 Generate code for PowerPC 601. 14118 14119 `-mppc, -mppc32, -m603, -m604' 14120 Generate code for PowerPC 603/604. 14121 14122 `-m403, -m405' 14123 Generate code for PowerPC 403/405. 14124 14125 `-m440' 14126 Generate code for PowerPC 440. BookE and some 405 instructions. 14127 14128 `-m476' 14129 Generate code for PowerPC 476. 14130 14131 `-m7400, -m7410, -m7450, -m7455' 14132 Generate code for PowerPC 7400/7410/7450/7455. 14133 14134 `-m750cl' 14135 Generate code for PowerPC 750CL. 14136 14137 `-mppc64, -m620' 14138 Generate code for PowerPC 620/625/630. 14139 14140 `-me500, -me500x2' 14141 Generate code for Motorola e500 core complex. 14142 14143 `-mspe' 14144 Generate code for Motorola SPE instructions. 14145 14146 `-mtitan' 14147 Generate code for AppliedMicro Titan core complex. 14148 14149 `-mppc64bridge' 14150 Generate code for PowerPC 64, including bridge insns. 14151 14152 `-mbooke' 14153 Generate code for 32-bit BookE. 14154 14155 `-ma2' 14156 Generate code for A2 architecture. 14157 14158 `-me300' 14159 Generate code for PowerPC e300 family. 14160 14161 `-maltivec' 14162 Generate code for processors with AltiVec instructions. 14163 14164 `-mvsx' 14165 Generate code for processors with Vector-Scalar (VSX) instructions. 14166 14167 `-mpower4' 14168 Generate code for Power4 architecture. 14169 14170 `-mpower5' 14171 Generate code for Power5 architecture. 14172 14173 `-mpower6' 14174 Generate code for Power6 architecture. 14175 14176 `-mpower7' 14177 Generate code for Power7 architecture. 14178 14179 `-mcell' 14180 Generate code for Cell Broadband Engine architecture. 14181 14182 `-mcom' 14183 Generate code Power/PowerPC common instructions. 14184 14185 `-many' 14186 Generate code for any architecture (PWR/PWRX/PPC). 14187 14188 `-mregnames' 14189 Allow symbolic names for registers. 14190 14191 `-mno-regnames' 14192 Do not allow symbolic names for registers. 14193 14194 `-mrelocatable' 14195 Support for GCC's -mrelocatable option. 14196 14197 `-mrelocatable-lib' 14198 Support for GCC's -mrelocatable-lib option. 14199 14200 `-memb' 14201 Set PPC_EMB bit in ELF flags. 14202 14203 `-mlittle, -mlittle-endian' 14204 Generate code for a little endian machine. 14205 14206 `-mbig, -mbig-endian' 14207 Generate code for a big endian machine. 14208 14209 `-msolaris' 14210 Generate code for Solaris. 14211 14212 `-mno-solaris' 14213 Do not generate code for Solaris. 14214 14215 14216 File: as.info, Node: PowerPC-Pseudo, Prev: PowerPC-Opts, Up: PPC-Dependent 14217 14218 9.29.2 PowerPC Assembler Directives 14219 ----------------------------------- 14220 14221 A number of assembler directives are available for PowerPC. The 14222 following table is far from complete. 14223 14224 `.machine "string"' 14225 This directive allows you to change the machine for which code is 14226 generated. `"string"' may be any of the -m cpu selection options 14227 (without the -m) enclosed in double quotes, `"push"', or `"pop"'. 14228 `.machine "push"' saves the currently selected cpu, which may be 14229 restored with `.machine "pop"'. 14230 14231 14232 File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 14233 14234 9.30 RX Dependent Features 14235 ========================== 14236 14237 * Menu: 14238 14239 * RX-Opts:: RX Assembler Command Line Options 14240 * RX-Modifiers:: Symbolic Operand Modifiers 14241 * RX-Directives:: Assembler Directives 14242 * RX-Float:: Floating Point 14243 14244 14245 File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 14246 14247 9.30.1 RX Options 14248 ----------------- 14249 14250 The Renesas RX port of `as' has a few target specfic command line 14251 options: 14252 14253 `-m32bit-doubles' 14254 This option controls the ABI and indicates to use a 32-bit float 14255 ABI. It has no effect on the assembled instructions, but it does 14256 influence the behaviour of the `.double' pseudo-op. This is the 14257 default. 14258 14259 `-m64bit-doubles' 14260 This option controls the ABI and indicates to use a 64-bit float 14261 ABI. It has no effect on the assembled instructions, but it does 14262 influence the behaviour of the `.double' pseudo-op. 14263 14264 `-mbig-endian' 14265 This option controls the ABI and indicates to use a big-endian data 14266 ABI. It has no effect on the assembled instructions, but it does 14267 influence the behaviour of the `.short', `.hword', `.int', 14268 `.word', `.long', `.quad' and `.octa' pseudo-ops. 14269 14270 `-mlittle-endian' 14271 This option controls the ABI and indicates to use a little-endian 14272 data ABI. It has no effect on the assembled instructions, but it 14273 does influence the behaviour of the `.short', `.hword', `.int', 14274 `.word', `.long', `.quad' and `.octa' pseudo-ops. This is the 14275 default. 14276 14277 `-muse-conventional-section-names' 14278 This option controls the default names given to the code (.text), 14279 initialised data (.data) and uninitialised data sections (.bss). 14280 14281 `-muse-renesas-section-names' 14282 This option controls the default names given to the code (.P), 14283 initialised data (.D_1) and uninitialised data sections (.B_1). 14284 This is the default. 14285 14286 `-msmall-data-limit' 14287 This option tells the assembler that the small data limit feature 14288 of the RX port of GCC is being used. This results in the assembler 14289 generating an undefined reference to a symbol called __gp for use 14290 by the relocations that are needed to support the small data limit 14291 feature. This option is not enabled by default as it would 14292 otherwise pollute the symbol table. 14293 14294 14295 14296 File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 14297 14298 9.30.2 Symbolic Operand Modifiers 14299 --------------------------------- 14300 14301 The assembler supports several modifiers when using symbol addresses in 14302 RX instruction operands. The general syntax is the following: 14303 14304 %modifier(symbol) 14305 14306 `%gp' 14307 14308 14309 File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 14310 14311 9.30.3 Assembler Directives 14312 --------------------------- 14313 14314 The RX version of `as' has the following specific assembler directives: 14315 14316 `.3byte' 14317 Inserts a 3-byte value into the output file at the current 14318 location. 14319 14320 14321 14322 File: as.info, Node: RX-Float, Prev: RX-Directives, Up: RX-Dependent 14323 14324 9.30.4 Floating Point 14325 --------------------- 14326 14327 The floating point formats generated by directives are these. 14328 14329 `.float' 14330 `Single' precision (32-bit) floating point constants. 14331 14332 `.double' 14333 If the `-m64bit-doubles' command line option has been specified 14334 then then `double' directive generates `double' precision (64-bit) 14335 floating point constants, otherwise it generates `single' 14336 precision (32-bit) floating point constants. To force the 14337 generation of 64-bit floating point constants used the `dc.d' 14338 directive instead. 14339 14340 14341 14342 File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 14343 14344 9.31 IBM S/390 Dependent Features 14345 ================================= 14346 14347 The s390 version of `as' supports two architectures modes and seven 14348 chip levels. The architecture modes are the Enterprise System 14349 Architecture (ESA) and the newer z/Architecture mode. The chip levels 14350 are g5, g6, z900, z990, z9-109, z9-ec, z10 and z196. 14351 14352 * Menu: 14353 14354 * s390 Options:: Command-line Options. 14355 * s390 Characters:: Special Characters. 14356 * s390 Syntax:: Assembler Instruction syntax. 14357 * s390 Directives:: Assembler Directives. 14358 * s390 Floating Point:: Floating Point. 14359 14360 14361 File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 14362 14363 9.31.1 Options 14364 -------------- 14365 14366 The following table lists all available s390 specific options: 14367 14368 `-m31 | -m64' 14369 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 14370 14371 These options are only available with the ELF object file format, 14372 and require that the necessary BFD support has been included (on a 14373 31-bit platform you must add -enable-64-bit-bfd on the call to the 14374 configure script to enable 64-bit usage and use s390x as target 14375 platform). 14376 14377 `-mesa | -mzarch' 14378 Select the architecture mode, either the Enterprise System 14379 Architecture (esa) mode or the z/Architecture mode (zarch). 14380 14381 The 64-bit instructions are only available with the z/Architecture 14382 mode. The combination of `-m64' and `-mesa' results in a warning 14383 message. 14384 14385 `-march=CPU' 14386 This option specifies the target processor. The following 14387 processor names are recognized: `g5', `g6', `z900', `z990', 14388 `z9-109', `z9-ec', `z10' and `z196'. Assembling an instruction 14389 that is not supported on the target processor results in an error 14390 message. Do not specify `g5' or `g6' with `-mzarch'. 14391 14392 `-mregnames' 14393 Allow symbolic names for registers. 14394 14395 `-mno-regnames' 14396 Do not allow symbolic names for registers. 14397 14398 `-mwarn-areg-zero' 14399 Warn whenever the operand for a base or index register has been 14400 specified but evaluates to zero. This can indicate the misuse of 14401 general purpose register 0 as an address register. 14402 14403 14404 14405 File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 14406 14407 9.31.2 Special Characters 14408 ------------------------- 14409 14410 `#' is the line comment character. 14411 14412 14413 File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 14414 14415 9.31.3 Instruction syntax 14416 ------------------------- 14417 14418 The assembler syntax closely follows the syntax outlined in Enterprise 14419 Systems Architecture/390 Principles of Operation (SA22-7201) and the 14420 z/Architecture Principles of Operation (SA22-7832). 14421 14422 Each instruction has two major parts, the instruction mnemonic and 14423 the instruction operands. The instruction format varies. 14424 14425 * Menu: 14426 14427 * s390 Register:: Register Naming 14428 * s390 Mnemonics:: Instruction Mnemonics 14429 * s390 Operands:: Instruction Operands 14430 * s390 Formats:: Instruction Formats 14431 * s390 Aliases:: Instruction Aliases 14432 * s390 Operand Modifier:: Instruction Operand Modifier 14433 * s390 Instruction Marker:: Instruction Marker 14434 * s390 Literal Pool Entries:: Literal Pool Entries 14435 14436 14437 File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 14438 14439 9.31.3.1 Register naming 14440 ........................ 14441 14442 The `as' recognizes a number of predefined symbols for the various 14443 processor registers. A register specification in one of the instruction 14444 formats is an unsigned integer between 0 and 15. The specific 14445 instruction and the position of the register in the instruction format 14446 denotes the type of the register. The register symbols are prefixed with 14447 `%': 14448 14449 %rN the 16 general purpose registers, 0 <= N <= 15 14450 %fN the 16 floating point registers, 0 <= N <= 15 14451 %aN the 16 access registers, 0 <= N <= 15 14452 %cN the 16 control registers, 0 <= N <= 15 14453 %lit an alias for the general purpose register %r13 14454 %sp an alias for the general purpose register %r15 14455 14456 14457 File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 14458 14459 9.31.3.2 Instruction Mnemonics 14460 .............................. 14461 14462 All instructions documented in the Principles of Operation are supported 14463 with the mnemonic and order of operands as described. The instruction 14464 mnemonic identifies the instruction format (*note s390 Formats::) and 14465 the specific operation code for the instruction. For example, the `lr' 14466 mnemonic denotes the instruction format `RR' with the operation code 14467 `0x18'. 14468 14469 The definition of the various mnemonics follows a scheme, where the 14470 first character usually hint at the type of the instruction: 14471 14472 a add instruction, for example `al' for add logical 32-bit 14473 b branch instruction, for example `bc' for branch on condition 14474 c compare or convert instruction, for example `cr' for compare 14475 register 32-bit 14476 d divide instruction, for example `dlr' devide logical register 14477 64-bit to 32-bit 14478 i insert instruction, for example `ic' insert character 14479 l load instruction, for example `ltr' load and test register 14480 mv move instruction, for example `mvc' move character 14481 m multiply instruction, for example `mh' multiply halfword 14482 n and instruction, for example `ni' and immediate 14483 o or instruction, for example `oc' or character 14484 sla, sll shift left single instruction 14485 sra, srl shift right single instruction 14486 st store instruction, for example `stm' store multiple 14487 s subtract instruction, for example `slr' subtract 14488 logical 32-bit 14489 t test or translate instruction, of example `tm' test under mask 14490 x exclusive or instruction, for example `xc' exclusive or 14491 character 14492 14493 Certain characters at the end of the mnemonic may describe a property 14494 of the instruction: 14495 14496 c the instruction uses a 8-bit character operand 14497 f the instruction extends a 32-bit operand to 64 bit 14498 g the operands are treated as 64-bit values 14499 h the operand uses a 16-bit halfword operand 14500 i the instruction uses an immediate operand 14501 l the instruction uses unsigned, logical operands 14502 m the instruction uses a mask or operates on multiple values 14503 r if r is the last character, the instruction operates on registers 14504 y the instruction uses 20-bit displacements 14505 14506 There are many exceptions to the scheme outlined in the above lists, 14507 in particular for the priviledged instructions. For non-priviledged 14508 instruction it works quite well, for example the instruction `clgfr' c: 14509 compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- 14510 to 64-bit extension, r: register operands. The instruction compares an 14511 64-bit value in a register with the zero extended 32-bit value from a 14512 second register. For a complete list of all mnemonics see appendix B 14513 in the Principles of Operation. 14514 14515 14516 File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 14517 14518 9.31.3.3 Instruction Operands 14519 ............................. 14520 14521 Instruction operands can be grouped into three classes, operands located 14522 in registers, immediate operands, and operands in storage. 14523 14524 A register operand can be located in general, floating-point, access, 14525 or control register. The register is identified by a four-bit field. 14526 The field containing the register operand is called the R field. 14527 14528 Immediate operands are contained within the instruction and can have 14529 8, 16 or 32 bits. The field containing the immediate operand is called 14530 the I field. Dependent on the instruction the I field is either signed 14531 or unsigned. 14532 14533 A storage operand consists of an address and a length. The address 14534 of a storage operands can be specified in any of these ways: 14535 14536 * The content of a single general R 14537 14538 * The sum of the content of a general register called the base 14539 register B plus the content of a displacement field D 14540 14541 * The sum of the contents of two general registers called the index 14542 register X and the base register B plus the content of a 14543 displacement field 14544 14545 * The sum of the current instruction address and a 32-bit signed 14546 immediate field multiplied by two. 14547 14548 The length of a storage operand can be: 14549 14550 * Implied by the instruction 14551 14552 * Specified by a bitmask 14553 14554 * Specified by a four-bit or eight-bit length field L 14555 14556 * Specified by the content of a general register 14557 14558 The notation for storage operand addresses formed from multiple 14559 fields is as follows: 14560 14561 `Dn(Bn)' 14562 the address for operand number n is formed from the content of 14563 general register Bn called the base register and the displacement 14564 field Dn. 14565 14566 `Dn(Xn,Bn)' 14567 the address for operand number n is formed from the content of 14568 general register Xn called the index register, general register Bn 14569 called the base register and the displacement field Dn. 14570 14571 `Dn(Ln,Bn)' 14572 the address for operand number n is formed from the content of 14573 general regiser Bn called the base register and the displacement 14574 field Dn. The length of the operand n is specified by the field 14575 Ln. 14576 14577 The base registers Bn and the index registers Xn of a storage 14578 operand can be skipped. If Bn and Xn are skipped, a zero will be stored 14579 to the operand field. The notation changes as follows: 14580 14581 full notation short notation 14582 ------------------------------------------ 14583 Dn(0,Bn) Dn(Bn) 14584 Dn(0,0) Dn 14585 Dn(0) Dn 14586 Dn(Ln,0) Dn(Ln) 14587 14588 14589 File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 14590 14591 9.31.3.4 Instruction Formats 14592 ............................ 14593 14594 The Principles of Operation manuals lists 26 instruction formats where 14595 some of the formats have multiple variants. For the `.insn' pseudo 14596 directive the assembler recognizes some of the formats. Typically, the 14597 most general variant of the instruction format is used by the `.insn' 14598 directive. 14599 14600 The following table lists the abbreviations used in the table of 14601 instruction formats: 14602 14603 OpCode / OpCd Part of the op code. 14604 Bx Base register number for operand x. 14605 Dx Displacement for operand x. 14606 DLx Displacement lower 12 bits for operand x. 14607 DHx Displacement higher 8-bits for operand x. 14608 Rx Register number for operand x. 14609 Xx Index register number for operand x. 14610 Ix Signed immediate for operand x. 14611 Ux Unsigned immediate for operand x. 14612 14613 An instruction is two, four, or six bytes in length and must be 14614 aligned on a 2 byte boundary. The first two bits of the instruction 14615 specify the length of the instruction, 00 indicates a two byte 14616 instruction, 01 and 10 indicates a four byte instruction, and 11 14617 indicates a six byte instruction. 14618 14619 The following table lists the s390 instruction formats that are 14620 available with the `.insn' pseudo directive: 14621 14622 `E format' 14623 +-------------+ 14624 | OpCode | 14625 +-------------+ 14626 0 15 14627 14628 `RI format: <insn> R1,I2' 14629 +--------+----+----+------------------+ 14630 | OpCode | R1 |OpCd| I2 | 14631 +--------+----+----+------------------+ 14632 0 8 12 16 31 14633 14634 `RIE format: <insn> R1,R3,I2' 14635 +--------+----+----+------------------+--------+--------+ 14636 | OpCode | R1 | R3 | I2 |////////| OpCode | 14637 +--------+----+----+------------------+--------+--------+ 14638 0 8 12 16 32 40 47 14639 14640 `RIL format: <insn> R1,I2' 14641 +--------+----+----+------------------------------------+ 14642 | OpCode | R1 |OpCd| I2 | 14643 +--------+----+----+------------------------------------+ 14644 0 8 12 16 47 14645 14646 `RILU format: <insn> R1,U2' 14647 +--------+----+----+------------------------------------+ 14648 | OpCode | R1 |OpCd| U2 | 14649 +--------+----+----+------------------------------------+ 14650 0 8 12 16 47 14651 14652 `RIS format: <insn> R1,I2,M3,D4(B4)' 14653 +--------+----+----+----+-------------+--------+--------+ 14654 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 14655 +--------+----+----+----+-------------+--------+--------+ 14656 0 8 12 16 20 32 36 47 14657 14658 `RR format: <insn> R1,R2' 14659 +--------+----+----+ 14660 | OpCode | R1 | R2 | 14661 +--------+----+----+ 14662 0 8 12 15 14663 14664 `RRE format: <insn> R1,R2' 14665 +------------------+--------+----+----+ 14666 | OpCode |////////| R1 | R2 | 14667 +------------------+--------+----+----+ 14668 0 16 24 28 31 14669 14670 `RRF format: <insn> R1,R2,R3,M4' 14671 +------------------+----+----+----+----+ 14672 | OpCode | R3 | M4 | R1 | R2 | 14673 +------------------+----+----+----+----+ 14674 0 16 20 24 28 31 14675 14676 `RRS format: <insn> R1,R2,M3,D4(B4)' 14677 +--------+----+----+----+-------------+----+----+--------+ 14678 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 14679 +--------+----+----+----+-------------+----+----+--------+ 14680 0 8 12 16 20 32 36 40 47 14681 14682 `RS format: <insn> R1,R3,D2(B2)' 14683 +--------+----+----+----+-------------+ 14684 | OpCode | R1 | R3 | B2 | D2 | 14685 +--------+----+----+----+-------------+ 14686 0 8 12 16 20 31 14687 14688 `RSE format: <insn> R1,R3,D2(B2)' 14689 +--------+----+----+----+-------------+--------+--------+ 14690 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 14691 +--------+----+----+----+-------------+--------+--------+ 14692 0 8 12 16 20 32 40 47 14693 14694 `RSI format: <insn> R1,R3,I2' 14695 +--------+----+----+------------------------------------+ 14696 | OpCode | R1 | R3 | I2 | 14697 +--------+----+----+------------------------------------+ 14698 0 8 12 16 47 14699 14700 `RSY format: <insn> R1,R3,D2(B2)' 14701 +--------+----+----+----+-------------+--------+--------+ 14702 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 14703 +--------+----+----+----+-------------+--------+--------+ 14704 0 8 12 16 20 32 40 47 14705 14706 `RX format: <insn> R1,D2(X2,B2)' 14707 +--------+----+----+----+-------------+ 14708 | OpCode | R1 | X2 | B2 | D2 | 14709 +--------+----+----+----+-------------+ 14710 0 8 12 16 20 31 14711 14712 `RXE format: <insn> R1,D2(X2,B2)' 14713 +--------+----+----+----+-------------+--------+--------+ 14714 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 14715 +--------+----+----+----+-------------+--------+--------+ 14716 0 8 12 16 20 32 40 47 14717 14718 `RXF format: <insn> R1,R3,D2(X2,B2)' 14719 +--------+----+----+----+-------------+----+---+--------+ 14720 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 14721 +--------+----+----+----+-------------+----+---+--------+ 14722 0 8 12 16 20 32 36 40 47 14723 14724 `RXY format: <insn> R1,D2(X2,B2)' 14725 +--------+----+----+----+-------------+--------+--------+ 14726 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 14727 +--------+----+----+----+-------------+--------+--------+ 14728 0 8 12 16 20 32 36 40 47 14729 14730 `S format: <insn> D2(B2)' 14731 +------------------+----+-------------+ 14732 | OpCode | B2 | D2 | 14733 +------------------+----+-------------+ 14734 0 16 20 31 14735 14736 `SI format: <insn> D1(B1),I2' 14737 +--------+---------+----+-------------+ 14738 | OpCode | I2 | B1 | D1 | 14739 +--------+---------+----+-------------+ 14740 0 8 16 20 31 14741 14742 `SIY format: <insn> D1(B1),U2' 14743 +--------+---------+----+-------------+--------+--------+ 14744 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 14745 +--------+---------+----+-------------+--------+--------+ 14746 0 8 16 20 32 36 40 47 14747 14748 `SIL format: <insn> D1(B1),I2' 14749 +------------------+----+-------------+-----------------+ 14750 | OpCode | B1 | D1 | I2 | 14751 +------------------+----+-------------+-----------------+ 14752 0 16 20 32 47 14753 14754 `SS format: <insn> D1(R1,B1),D2(B3),R3' 14755 +--------+----+----+----+-------------+----+------------+ 14756 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 14757 +--------+----+----+----+-------------+----+------------+ 14758 0 8 12 16 20 32 36 47 14759 14760 `SSE format: <insn> D1(B1),D2(B2)' 14761 +------------------+----+-------------+----+------------+ 14762 | OpCode | B1 | D1 | B2 | D2 | 14763 +------------------+----+-------------+----+------------+ 14764 0 8 12 16 20 32 36 47 14765 14766 `SSF format: <insn> D1(B1),D2(B2),R3' 14767 +--------+----+----+----+-------------+----+------------+ 14768 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 14769 +--------+----+----+----+-------------+----+------------+ 14770 0 8 12 16 20 32 36 47 14771 14772 14773 For the complete list of all instruction format variants see the 14774 Principles of Operation manuals. 14775 14776 14777 File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 14778 14779 9.31.3.5 Instruction Aliases 14780 ............................ 14781 14782 A specific bit pattern can have multiple mnemonics, for example the bit 14783 pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition, 14784 there are a number of mnemonics recognized by `as' that are not present 14785 in the Principles of Operation. These are the short forms of the 14786 branch instructions, where the condition code mask operand is encoded 14787 in the mnemonic. This is relevant for the branch instructions, the 14788 compare and branch instructions, and the compare and trap instructions. 14789 14790 For the branch instructions there are 20 condition code strings that 14791 can be used as part of the mnemonic in place of a mask operand in the 14792 instruction format: 14793 14794 instruction short form 14795 ------------------------------------------ 14796 bcr M1,R2 b<m>r R2 14797 bc M1,D2(X2,B2) b<m> D2(X2,B2) 14798 brc M1,I2 j<m> I2 14799 brcl M1,I2 jg<m> I2 14800 14801 In the mnemonic for a branch instruction the condition code string 14802 <m> can be any of the following: 14803 14804 o jump on overflow / if ones 14805 h jump on A high 14806 p jump on plus 14807 nle jump on not low or equal 14808 l jump on A low 14809 m jump on minus 14810 nhe jump on not high or equal 14811 lh jump on low or high 14812 ne jump on A not equal B 14813 nz jump on not zero / if not zeros 14814 e jump on A equal B 14815 z jump on zero / if zeroes 14816 nlh jump on not low or high 14817 he jump on high or equal 14818 nl jump on A not low 14819 nm jump on not minus / if not mixed 14820 le jump on low or equal 14821 nh jump on A not high 14822 np jump on not plus 14823 no jump on not overflow / if not ones 14824 14825 For the compare and branch, and compare and trap instructions there 14826 are 12 condition code strings that can be used as part of the mnemonic 14827 in place of a mask operand in the instruction format: 14828 14829 instruction short form 14830 -------------------------------------------------------- 14831 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 14832 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 14833 crj R1,R2,M3,I4 crj<m> R1,R2,I4 14834 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 14835 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 14836 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 14837 cij R1,I2,M3,I4 cij<m> R1,I2,I4 14838 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 14839 crt R1,R2,M3 crt<m> R1,R2 14840 cgrt R1,R2,M3 cgrt<m> R1,R2 14841 cit R1,I2,M3 cit<m> R1,I2 14842 cgit R1,I2,M3 cgit<m> R1,I2 14843 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 14844 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 14845 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 14846 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 14847 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 14848 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 14849 clij R1,I2,M3,I4 clij<m> R1,I2,I4 14850 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 14851 clrt R1,R2,M3 clrt<m> R1,R2 14852 clgrt R1,R2,M3 clgrt<m> R1,R2 14853 clfit R1,I2,M3 clfit<m> R1,I2 14854 clgit R1,I2,M3 clgit<m> R1,I2 14855 14856 In the mnemonic for a compare and branch and compare and trap 14857 instruction the condition code string <m> can be any of the following: 14858 14859 h jump on A high 14860 nle jump on not low or equal 14861 l jump on A low 14862 nhe jump on not high or equal 14863 ne jump on A not equal B 14864 lh jump on low or high 14865 e jump on A equal B 14866 nlh jump on not low or high 14867 nl jump on A not low 14868 he jump on high or equal 14869 nh jump on A not high 14870 le jump on low or equal 14871 14872 14873 File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 14874 14875 9.31.3.6 Instruction Operand Modifier 14876 ..................................... 14877 14878 If a symbol modifier is attached to a symbol in an expression for an 14879 instruction operand field, the symbol term is replaced with a reference 14880 to an object in the global offset table (GOT) or the procedure linkage 14881 table (PLT). The following expressions are allowed: `symbol@modifier + 14882 constant', `symbol@modifier + label + constant', and `symbol@modifier - 14883 label + constant'. The term `symbol' is the symbol that will be 14884 entered into the GOT or PLT, `label' is a local label, and `constant' 14885 is an arbitrary expression that the assembler can evaluate to a 14886 constant value. 14887 14888 The term `(symbol + constant1)@modifier +/- label + constant2' is 14889 also accepted but a warning message is printed and the term is 14890 converted to `symbol@modifier +/- label + constant1 + constant2'. 14891 14892 `@got' 14893 `@got12' 14894 The @got modifier can be used for displacement fields, 16-bit 14895 immediate fields and 32-bit pc-relative immediate fields. The 14896 @got12 modifier is synonym to @got. The symbol is added to the 14897 GOT. For displacement fields and 16-bit immediate fields the 14898 symbol term is replaced with the offset from the start of the GOT 14899 to the GOT slot for the symbol. For a 32-bit pc-relative field 14900 the pc-relative offset to the GOT slot from the current 14901 instruction address is used. 14902 14903 `@gotent' 14904 The @gotent modifier can be used for 32-bit pc-relative immediate 14905 fields. The symbol is added to the GOT and the symbol term is 14906 replaced with the pc-relative offset from the current instruction 14907 to the GOT slot for the symbol. 14908 14909 `@gotoff' 14910 The @gotoff modifier can be used for 16-bit immediate fields. The 14911 symbol term is replaced with the offset from the start of the GOT 14912 to the address of the symbol. 14913 14914 `@gotplt' 14915 The @gotplt modifier can be used for displacement fields, 16-bit 14916 immediate fields, and 32-bit pc-relative immediate fields. A 14917 procedure linkage table entry is generated for the symbol and a 14918 jump slot for the symbol is added to the GOT. For displacement 14919 fields and 16-bit immediate fields the symbol term is replaced 14920 with the offset from the start of the GOT to the jump slot for the 14921 symbol. For a 32-bit pc-relative field the pc-relative offset to 14922 the jump slot from the current instruction address is used. 14923 14924 `@plt' 14925 The @plt modifier can be used for 16-bit and 32-bit pc-relative 14926 immediate fields. A procedure linkage table entry is generated for 14927 the symbol. The symbol term is replaced with the relative offset 14928 from the current instruction to the PLT entry for the symbol. 14929 14930 `@pltoff' 14931 The @pltoff modifier can be used for 16-bit immediate fields. The 14932 symbol term is replaced with the offset from the start of the PLT 14933 to the address of the symbol. 14934 14935 `@gotntpoff' 14936 The @gotntpoff modifier can be used for displacement fields. The 14937 symbol is added to the static TLS block and the negated offset to 14938 the symbol in the static TLS block is added to the GOT. The symbol 14939 term is replaced with the offset to the GOT slot from the start of 14940 the GOT. 14941 14942 `@indntpoff' 14943 The @indntpoff modifier can be used for 32-bit pc-relative 14944 immediate fields. The symbol is added to the static TLS block and 14945 the negated offset to the symbol in the static TLS block is added 14946 to the GOT. The symbol term is replaced with the pc-relative 14947 offset to the GOT slot from the current instruction address. 14948 14949 For more information about the thread local storage modifiers 14950 `gotntpoff' and `indntpoff' see the ELF extension documentation `ELF 14951 Handling For Thread-Local Storage'. 14952 14953 14954 File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 14955 14956 9.31.3.7 Instruction Marker 14957 ........................... 14958 14959 The thread local storage instruction markers are used by the linker to 14960 perform code optimization. 14961 14962 `:tls_load' 14963 The :tls_load marker is used to flag the load instruction in the 14964 initial exec TLS model that retrieves the offset from the thread 14965 pointer to a thread local storage variable from the GOT. 14966 14967 `:tls_gdcall' 14968 The :tls_gdcall marker is used to flag the branch-and-save 14969 instruction to the __tls_get_offset function in the global dynamic 14970 TLS model. 14971 14972 `:tls_ldcall' 14973 The :tls_ldcall marker is used to flag the branch-and-save 14974 instruction to the __tls_get_offset function in the local dynamic 14975 TLS model. 14976 14977 For more information about the thread local storage instruction 14978 marker and the linker optimizations see the ELF extension documentation 14979 `ELF Handling For Thread-Local Storage'. 14980 14981 14982 File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 14983 14984 9.31.3.8 Literal Pool Entries 14985 ............................. 14986 14987 A literal pool is a collection of values. To access the values a pointer 14988 to the literal pool is loaded to a register, the literal pool register. 14989 Usually, register %r13 is used as the literal pool register (*note s390 14990 Register::). Literal pool entries are created by adding the suffix 14991 :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 14992 instruction operand. The expression is added to the literal pool and the 14993 operand is replaced with the offset to the literal in the literal pool. 14994 14995 `:lit1' 14996 The literal pool entry is created as an 8-bit value. An operand 14997 modifier must not be used for the original expression. 14998 14999 `:lit2' 15000 The literal pool entry is created as a 16 bit value. The operand 15001 modifier @got may be used in the original expression. The term 15002 `x@got:lit2' will put the got offset for the global symbol x to 15003 the literal pool as 16 bit value. 15004 15005 `:lit4' 15006 The literal pool entry is created as a 32-bit value. The operand 15007 modifier @got and @plt may be used in the original expression. The 15008 term `x@got:lit4' will put the got offset for the global symbol x 15009 to the literal pool as a 32-bit value. The term `x@plt:lit4' will 15010 put the plt offset for the global symbol x to the literal pool as 15011 a 32-bit value. 15012 15013 `:lit8' 15014 The literal pool entry is created as a 64-bit value. The operand 15015 modifier @got and @plt may be used in the original expression. The 15016 term `x@got:lit8' will put the got offset for the global symbol x 15017 to the literal pool as a 64-bit value. The term `x@plt:lit8' will 15018 put the plt offset for the global symbol x to the literal pool as 15019 a 64-bit value. 15020 15021 The assembler directive `.ltorg' is used to emit all literal pool 15022 entries to the current position. 15023 15024 15025 File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 15026 15027 9.31.4 Assembler Directives 15028 --------------------------- 15029 15030 `as' for s390 supports all of the standard ELF assembler directives as 15031 outlined in the main part of this document. Some directives have been 15032 extended and there are some additional directives, which are only 15033 available for the s390 `as'. 15034 15035 `.insn' 15036 This directive permits the numeric representation of an 15037 instructions and makes the assembler insert the operands according 15038 to one of the instructions formats for `.insn' (*note s390 15039 Formats::). For example, the instruction `l %r1,24(%r15)' could 15040 be written as `.insn rx,0x58000000,%r1,24(%r15)'. 15041 15042 `.short' 15043 `.long' 15044 `.quad' 15045 This directive places one or more 16-bit (.short), 32-bit (.long), 15046 or 64-bit (.quad) values into the current section. If an ELF or 15047 TLS modifier is used only the following expressions are allowed: 15048 `symbol@modifier + constant', `symbol@modifier + label + 15049 constant', and `symbol@modifier - label + constant'. The 15050 following modifiers are available: 15051 `@got' 15052 `@got12' 15053 The @got modifier can be used for .short, .long and .quad. 15054 The @got12 modifier is synonym to @got. The symbol is added 15055 to the GOT. The symbol term is replaced with offset from the 15056 start of the GOT to the GOT slot for the symbol. 15057 15058 `@gotoff' 15059 The @gotoff modifier can be used for .short, .long and .quad. 15060 The symbol term is replaced with the offset from the start of 15061 the GOT to the address of the symbol. 15062 15063 `@gotplt' 15064 The @gotplt modifier can be used for .long and .quad. A 15065 procedure linkage table entry is generated for the symbol and 15066 a jump slot for the symbol is added to the GOT. The symbol 15067 term is replaced with the offset from the start of the GOT to 15068 the jump slot for the symbol. 15069 15070 `@plt' 15071 The @plt modifier can be used for .long and .quad. A 15072 procedure linkage table entry us generated for the symbol. 15073 The symbol term is replaced with the address of the PLT entry 15074 for the symbol. 15075 15076 `@pltoff' 15077 The @pltoff modifier can be used for .short, .long and .quad. 15078 The symbol term is replaced with the offset from the start of 15079 the PLT to the address of the symbol. 15080 15081 `@tlsgd' 15082 `@tlsldm' 15083 The @tlsgd and @tlsldm modifier can be used for .long and 15084 .quad. A tls_index structure for the symbol is added to the 15085 GOT. The symbol term is replaced with the offset from the 15086 start of the GOT to the tls_index structure. 15087 15088 `@gotntpoff' 15089 `@indntpoff' 15090 The @gotntpoff and @indntpoff modifier can be used for .long 15091 and .quad. The symbol is added to the static TLS block and 15092 the negated offset to the symbol in the static TLS block is 15093 added to the GOT. For @gotntpoff the symbol term is replaced 15094 with the offset from the start of the GOT to the GOT slot, 15095 for @indntpoff the symbol term is replaced with the address 15096 of the GOT slot. 15097 15098 `@dtpoff' 15099 The @dtpoff modifier can be used for .long and .quad. The 15100 symbol term is replaced with the offset of the symbol 15101 relative to the start of the TLS block it is contained in. 15102 15103 `@ntpoff' 15104 The @ntpoff modifier can be used for .long and .quad. The 15105 symbol term is replaced with the offset of the symbol 15106 relative to the TCB pointer. 15107 15108 For more information about the thread local storage modifiers see 15109 the ELF extension documentation `ELF Handling For Thread-Local 15110 Storage'. 15111 15112 `.ltorg' 15113 This directive causes the current contents of the literal pool to 15114 be dumped to the current location (*note s390 Literal Pool 15115 Entries::). 15116 15117 15118 File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 15119 15120 9.31.5 Floating Point 15121 --------------------- 15122 15123 The assembler recognizes both the IEEE floating-point instruction and 15124 the hexadecimal floating-point instructions. The floating-point 15125 constructors `.float', `.single', and `.double' always emit the IEEE 15126 format. To assemble hexadecimal floating-point constants the `.long' 15127 and `.quad' directives must be used. 15128 15129 15130 File: as.info, Node: SCORE-Dependent, Next: Sparc-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 15131 15132 9.32 SCORE Dependent Features 15133 ============================= 15134 15135 * Menu: 15136 15137 * SCORE-Opts:: Assembler options 15138 * SCORE-Pseudo:: SCORE Assembler Directives 15139 15140 15141 File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 15142 15143 9.32.1 Options 15144 -------------- 15145 15146 The following table lists all available SCORE options. 15147 15148 `-G NUM' 15149 This option sets the largest size of an object that can be 15150 referenced implicitly with the `gp' register. The default value is 15151 8. 15152 15153 `-EB' 15154 Assemble code for a big-endian cpu 15155 15156 `-EL' 15157 Assemble code for a little-endian cpu 15158 15159 `-FIXDD' 15160 Assemble code for fix data dependency 15161 15162 `-NWARN' 15163 Assemble code for no warning message for fix data dependency 15164 15165 `-SCORE5' 15166 Assemble code for target is SCORE5 15167 15168 `-SCORE5U' 15169 Assemble code for target is SCORE5U 15170 15171 `-SCORE7' 15172 Assemble code for target is SCORE7, this is default setting 15173 15174 `-SCORE3' 15175 Assemble code for target is SCORE3 15176 15177 `-march=score7' 15178 Assemble code for target is SCORE7, this is default setting 15179 15180 `-march=score3' 15181 Assemble code for target is SCORE3 15182 15183 `-USE_R1' 15184 Assemble code for no warning message when using temp register r1 15185 15186 `-KPIC' 15187 Generate code for PIC. This option tells the assembler to generate 15188 score position-independent macro expansions. It also tells the 15189 assembler to mark the output file as PIC. 15190 15191 `-O0' 15192 Assembler will not perform any optimizations 15193 15194 `-V' 15195 Sunplus release version 15196 15197 15198 15199 File: as.info, Node: SCORE-Pseudo, Prev: SCORE-Opts, Up: SCORE-Dependent 15200 15201 9.32.2 SCORE Assembler Directives 15202 --------------------------------- 15203 15204 A number of assembler directives are available for SCORE. The 15205 following table is far from complete. 15206 15207 `.set nwarn' 15208 Let the assembler not to generate warnings if the source machine 15209 language instructions happen data dependency. 15210 15211 `.set fixdd' 15212 Let the assembler to insert bubbles (32 bit nop instruction / 16 15213 bit nop! Instruction) if the source machine language instructions 15214 happen data dependency. 15215 15216 `.set nofixdd' 15217 Let the assembler to generate warnings if the source machine 15218 language instructions happen data dependency. (Default) 15219 15220 `.set r1' 15221 Let the assembler not to generate warnings if the source program 15222 uses r1. allow user to use r1 15223 15224 `set nor1' 15225 Let the assembler to generate warnings if the source program uses 15226 r1. (Default) 15227 15228 `.sdata' 15229 Tell the assembler to add subsequent data into the sdata section 15230 15231 `.rdata' 15232 Tell the assembler to add subsequent data into the rdata section 15233 15234 `.frame "frame-register", "offset", "return-pc-register"' 15235 Describe a stack frame. "frame-register" is the frame register, 15236 "offset" is the distance from the frame register to the virtual 15237 frame pointer, "return-pc-register" is the return program register. 15238 You must use ".ent" before ".frame" and only one ".frame" can be 15239 used per ".ent". 15240 15241 `.mask "bitmask", "frameoffset"' 15242 Indicate which of the integer registers are saved in the current 15243 function's stack frame, this is for the debugger to explain the 15244 frame chain. 15245 15246 `.ent "proc-name"' 15247 Set the beginning of the procedure "proc_name". Use this directive 15248 when you want to generate information for the debugger. 15249 15250 `.end proc-name' 15251 Set the end of a procedure. Use this directive to generate 15252 information for the debugger. 15253 15254 `.bss' 15255 Switch the destination of following statements into the bss 15256 section, which is used for data that is uninitialized anywhere. 15257 15258 15259 15260 File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 15261 15262 9.33 Renesas / SuperH SH Dependent Features 15263 =========================================== 15264 15265 * Menu: 15266 15267 * SH Options:: Options 15268 * SH Syntax:: Syntax 15269 * SH Floating Point:: Floating Point 15270 * SH Directives:: SH Machine Directives 15271 * SH Opcodes:: Opcodes 15272 15273 15274 File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 15275 15276 9.33.1 Options 15277 -------------- 15278 15279 `as' has following command-line options for the Renesas (formerly 15280 Hitachi) / SuperH SH family. 15281 15282 `--little' 15283 Generate little endian code. 15284 15285 `--big' 15286 Generate big endian code. 15287 15288 `--relax' 15289 Alter jump instructions for long displacements. 15290 15291 `--small' 15292 Align sections to 4 byte boundaries, not 16. 15293 15294 `--dsp' 15295 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15296 15297 `--renesas' 15298 Disable optimization with section symbol for compatibility with 15299 Renesas assembler. 15300 15301 `--allow-reg-prefix' 15302 Allow '$' as a register name prefix. 15303 15304 `--fdpic' 15305 Generate an FDPIC object file. 15306 15307 `--isa=sh4 | sh4a' 15308 Specify the sh4 or sh4a instruction set. 15309 15310 `--isa=dsp' 15311 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15312 15313 `--isa=fp' 15314 Enable sh2e, sh3e, sh4, and sh4a insn sets. 15315 15316 `--isa=all' 15317 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 15318 15319 `-h-tick-hex' 15320 Support H'00 style hex constants in addition to 0x00 style. 15321 15322 15323 15324 File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 15325 15326 9.33.2 Syntax 15327 ------------- 15328 15329 * Menu: 15330 15331 * SH-Chars:: Special Characters 15332 * SH-Regs:: Register Names 15333 * SH-Addressing:: Addressing Modes 15334 15335 15336 File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 15337 15338 9.33.2.1 Special Characters 15339 ........................... 15340 15341 `!' is the line comment character. 15342 15343 You can use `;' instead of a newline to separate statements. 15344 15345 Since `$' has no special meaning, you may use it in symbol names. 15346 15347 15348 File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 15349 15350 9.33.2.2 Register Names 15351 ....................... 15352 15353 You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', 15354 `r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to 15355 refer to the SH registers. 15356 15357 The SH also has these control registers: 15358 15359 `pr' 15360 procedure register (holds return address) 15361 15362 `pc' 15363 program counter 15364 15365 `mach' 15366 `macl' 15367 high and low multiply accumulator registers 15368 15369 `sr' 15370 status register 15371 15372 `gbr' 15373 global base register 15374 15375 `vbr' 15376 vector base register (for interrupt vectors) 15377 15378 15379 File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 15380 15381 9.33.2.3 Addressing Modes 15382 ......................... 15383 15384 `as' understands the following addressing modes for the SH. `RN' in 15385 the following refers to any of the numbered registers, but _not_ the 15386 control registers. 15387 15388 `RN' 15389 Register direct 15390 15391 `@RN' 15392 Register indirect 15393 15394 `@-RN' 15395 Register indirect with pre-decrement 15396 15397 `@RN+' 15398 Register indirect with post-increment 15399 15400 `@(DISP, RN)' 15401 Register indirect with displacement 15402 15403 `@(R0, RN)' 15404 Register indexed 15405 15406 `@(DISP, GBR)' 15407 `GBR' offset 15408 15409 `@(R0, GBR)' 15410 GBR indexed 15411 15412 `ADDR' 15413 `@(DISP, PC)' 15414 PC relative address (for branch or for addressing memory). The 15415 `as' implementation allows you to use the simpler form ADDR 15416 anywhere a PC relative address is called for; the alternate form 15417 is supported for compatibility with other assemblers. 15418 15419 `#IMM' 15420 Immediate data 15421 15422 15423 File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 15424 15425 9.33.3 Floating Point 15426 --------------------- 15427 15428 SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 15429 SH groups can use `.float' directive to generate IEEE floating-point 15430 numbers. 15431 15432 SH2E and SH3E support single-precision floating point calculations as 15433 well as entirely PCAPI compatible emulation of double-precision 15434 floating point calculations. SH2E and SH3E instructions are a subset of 15435 the floating point calculations conforming to the IEEE754 standard. 15436 15437 In addition to single-precision and double-precision floating-point 15438 operation capability, the on-chip FPU of SH4 has a 128-bit graphic 15439 engine that enables 32-bit floating-point data to be processed 128 bits 15440 at a time. It also supports 4 * 4 array operations and inner product 15441 operations. Also, a superscalar architecture is employed that enables 15442 simultaneous execution of two instructions (including FPU 15443 instructions), providing performance of up to twice that of 15444 conventional architectures at the same frequency. 15445 15446 15447 File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 15448 15449 9.33.4 SH Machine Directives 15450 ---------------------------- 15451 15452 `uaword' 15453 `ualong' 15454 `as' will issue a warning when a misaligned `.word' or `.long' 15455 directive is used. You may use `.uaword' or `.ualong' to indicate 15456 that the value is intentionally misaligned. 15457 15458 15459 File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 15460 15461 9.33.5 Opcodes 15462 -------------- 15463 15464 For detailed information on the SH machine instruction set, see 15465 `SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core 15466 Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH). 15467 15468 `as' implements all the standard SH opcodes. No additional 15469 pseudo-instructions are needed on this family. Note, however, that 15470 because `as' supports a simpler form of PC-relative addressing, you may 15471 simply write (for example) 15472 15473 mov.l bar,r0 15474 15475 where other assemblers might require an explicit displacement to `bar' 15476 from the program counter: 15477 15478 mov.l @(DISP, PC) 15479 15480 Here is a summary of SH opcodes: 15481 15482 Legend: 15483 Rn a numbered register 15484 Rm another numbered register 15485 #imm immediate data 15486 disp displacement 15487 disp8 8-bit displacement 15488 disp12 12-bit displacement 15489 15490 add #imm,Rn lds.l @Rn+,PR 15491 add Rm,Rn mac.w @Rm+,@Rn+ 15492 addc Rm,Rn mov #imm,Rn 15493 addv Rm,Rn mov Rm,Rn 15494 and #imm,R0 mov.b Rm,@(R0,Rn) 15495 and Rm,Rn mov.b Rm,@-Rn 15496 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 15497 bf disp8 mov.b @(disp,Rm),R0 15498 bra disp12 mov.b @(disp,GBR),R0 15499 bsr disp12 mov.b @(R0,Rm),Rn 15500 bt disp8 mov.b @Rm+,Rn 15501 clrmac mov.b @Rm,Rn 15502 clrt mov.b R0,@(disp,Rm) 15503 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 15504 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 15505 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 15506 cmp/gt Rm,Rn mov.l Rm,@-Rn 15507 cmp/hi Rm,Rn mov.l Rm,@Rn 15508 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 15509 cmp/pl Rn mov.l @(disp,GBR),R0 15510 cmp/pz Rn mov.l @(disp,PC),Rn 15511 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 15512 div0s Rm,Rn mov.l @Rm+,Rn 15513 div0u mov.l @Rm,Rn 15514 div1 Rm,Rn mov.l R0,@(disp,GBR) 15515 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 15516 exts.w Rm,Rn mov.w Rm,@-Rn 15517 extu.b Rm,Rn mov.w Rm,@Rn 15518 extu.w Rm,Rn mov.w @(disp,Rm),R0 15519 jmp @Rn mov.w @(disp,GBR),R0 15520 jsr @Rn mov.w @(disp,PC),Rn 15521 ldc Rn,GBR mov.w @(R0,Rm),Rn 15522 ldc Rn,SR mov.w @Rm+,Rn 15523 ldc Rn,VBR mov.w @Rm,Rn 15524 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 15525 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 15526 ldc.l @Rn+,VBR mova @(disp,PC),R0 15527 lds Rn,MACH movt Rn 15528 lds Rn,MACL muls Rm,Rn 15529 lds Rn,PR mulu Rm,Rn 15530 lds.l @Rn+,MACH neg Rm,Rn 15531 lds.l @Rn+,MACL negc Rm,Rn 15532 15533 nop stc VBR,Rn 15534 not Rm,Rn stc.l GBR,@-Rn 15535 or #imm,R0 stc.l SR,@-Rn 15536 or Rm,Rn stc.l VBR,@-Rn 15537 or.b #imm,@(R0,GBR) sts MACH,Rn 15538 rotcl Rn sts MACL,Rn 15539 rotcr Rn sts PR,Rn 15540 rotl Rn sts.l MACH,@-Rn 15541 rotr Rn sts.l MACL,@-Rn 15542 rte sts.l PR,@-Rn 15543 rts sub Rm,Rn 15544 sett subc Rm,Rn 15545 shal Rn subv Rm,Rn 15546 shar Rn swap.b Rm,Rn 15547 shll Rn swap.w Rm,Rn 15548 shll16 Rn tas.b @Rn 15549 shll2 Rn trapa #imm 15550 shll8 Rn tst #imm,R0 15551 shlr Rn tst Rm,Rn 15552 shlr16 Rn tst.b #imm,@(R0,GBR) 15553 shlr2 Rn xor #imm,R0 15554 shlr8 Rn xor Rm,Rn 15555 sleep xor.b #imm,@(R0,GBR) 15556 stc GBR,Rn xtrct Rm,Rn 15557 stc SR,Rn 15558 15559 15560 File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 15561 15562 9.34 SuperH SH64 Dependent Features 15563 =================================== 15564 15565 * Menu: 15566 15567 * SH64 Options:: Options 15568 * SH64 Syntax:: Syntax 15569 * SH64 Directives:: SH64 Machine Directives 15570 * SH64 Opcodes:: Opcodes 15571 15572 15573 File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent 15574 15575 9.34.1 Options 15576 -------------- 15577 15578 `-isa=sh4 | sh4a' 15579 Specify the sh4 or sh4a instruction set. 15580 15581 `-isa=dsp' 15582 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15583 15584 `-isa=fp' 15585 Enable sh2e, sh3e, sh4, and sh4a insn sets. 15586 15587 `-isa=all' 15588 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 15589 15590 `-isa=shmedia | -isa=shcompact' 15591 Specify the default instruction set. `SHmedia' specifies the 15592 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes 15593 compatible with previous SH families. The default depends on the 15594 ABI selected; the default for the 64-bit ABI is SHmedia, and the 15595 default for the 32-bit ABI is SHcompact. If neither the ABI nor 15596 the ISA is specified, the default is 32-bit SHcompact. 15597 15598 Note that the `.mode' pseudo-op is not permitted if the ISA is not 15599 specified on the command line. 15600 15601 `-abi=32 | -abi=64' 15602 Specify the default ABI. If the ISA is specified and the ABI is 15603 not, the default ABI depends on the ISA, with SHmedia defaulting 15604 to 64-bit and SHcompact defaulting to 32-bit. 15605 15606 Note that the `.abi' pseudo-op is not permitted if the ABI is not 15607 specified on the command line. When the ABI is specified on the 15608 command line, any `.abi' pseudo-ops in the source must match it. 15609 15610 `-shcompact-const-crange' 15611 Emit code-range descriptors for constants in SHcompact code 15612 sections. 15613 15614 `-no-mix' 15615 Disallow SHmedia code in the same section as constants and 15616 SHcompact code. 15617 15618 `-no-expand' 15619 Do not expand MOVI, PT, PTA or PTB instructions. 15620 15621 `-expand-pt32' 15622 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. 15623 15624 `-h-tick-hex' 15625 Support H'00 style hex constants in addition to 0x00 style. 15626 15627 15628 15629 File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent 15630 15631 9.34.2 Syntax 15632 ------------- 15633 15634 * Menu: 15635 15636 * SH64-Chars:: Special Characters 15637 * SH64-Regs:: Register Names 15638 * SH64-Addressing:: Addressing Modes 15639 15640 15641 File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax 15642 15643 9.34.2.1 Special Characters 15644 ........................... 15645 15646 `!' is the line comment character. 15647 15648 You can use `;' instead of a newline to separate statements. 15649 15650 Since `$' has no special meaning, you may use it in symbol names. 15651 15652 15653 File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax 15654 15655 9.34.2.2 Register Names 15656 ....................... 15657 15658 You can use the predefined symbols `r0' through `r63' to refer to the 15659 SH64 general registers, `cr0' through `cr63' for control registers, 15660 `tr0' through `tr7' for target address registers, `fr0' through `fr63' 15661 for single-precision floating point registers, `dr0' through `dr62' 15662 (even numbered registers only) for double-precision floating point 15663 registers, `fv0' through `fv60' (multiples of four only) for 15664 single-precision floating point vectors, `fp0' through `fp62' (even 15665 numbered registers only) for single-precision floating point pairs, 15666 `mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of 15667 single-precision floating point registers, `pc' for the program 15668 counter, and `fpscr' for the floating point status and control register. 15669 15670 You can also refer to the control registers by the mnemonics `sr', 15671 `ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc', 15672 `resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'. 15673 15674 15675 File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax 15676 15677 9.34.2.3 Addressing Modes 15678 ......................... 15679 15680 SH64 operands consist of either a register or immediate value. The 15681 immediate value can be a constant or label reference (or portion of a 15682 label reference), as in this example: 15683 15684 movi 4,r2 15685 pt function, tr4 15686 movi (function >> 16) & 65535,r0 15687 shori function & 65535, r0 15688 ld.l r0,4,r0 15689 15690 Instruction label references can reference labels in either SHmedia 15691 or SHcompact. To differentiate between the two, labels in SHmedia 15692 sections will always have the least significant bit set (i.e. they will 15693 be odd), which SHcompact labels will have the least significant bit 15694 reset (i.e. they will be even). If you need to reference the actual 15695 address of a label, you can use the `datalabel' modifier, as in this 15696 example: 15697 15698 .long function 15699 .long datalabel function 15700 15701 In that example, the first longword may or may not have the least 15702 significant bit set depending on whether the label is an SHmedia label 15703 or an SHcompact label. The second longword will be the actual address 15704 of the label, regardless of what type of label it is. 15705 15706 15707 File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent 15708 15709 9.34.3 SH64 Machine Directives 15710 ------------------------------ 15711 15712 In addition to the SH directives, the SH64 provides the following 15713 directives: 15714 15715 `.mode [shmedia|shcompact]' 15716 `.isa [shmedia|shcompact]' 15717 Specify the ISA for the following instructions (the two directives 15718 are equivalent). Note that programs such as `objdump' rely on 15719 symbolic labels to determine when such mode switches occur (by 15720 checking the least significant bit of the label's address), so 15721 such mode/isa changes should always be followed by a label (in 15722 practice, this is true anyway). Note that you cannot use these 15723 directives if you didn't specify an ISA on the command line. 15724 15725 `.abi [32|64]' 15726 Specify the ABI for the following instructions. Note that you 15727 cannot use this directive unless you specified an ABI on the 15728 command line, and the ABIs specified must match. 15729 15730 `.uaquad' 15731 Like .uaword and .ualong, this allows you to specify an 15732 intentionally unaligned quadword (64 bit word). 15733 15734 15735 15736 File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent 15737 15738 9.34.4 Opcodes 15739 -------------- 15740 15741 For detailed information on the SH64 machine instruction set, see 15742 `SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). 15743 15744 `as' implements all the standard SH64 opcodes. In addition, the 15745 following pseudo-opcodes may be expanded into one or more alternate 15746 opcodes: 15747 15748 `movi' 15749 If the value doesn't fit into a standard `movi' opcode, `as' will 15750 replace the `movi' with a sequence of `movi' and `shori' opcodes. 15751 15752 `pt' 15753 This expands to a sequence of `movi' and `shori' opcode, followed 15754 by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on 15755 the label referenced. 15756 15757 15758 15759 File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 15760 15761 9.35 SPARC Dependent Features 15762 ============================= 15763 15764 * Menu: 15765 15766 * Sparc-Opts:: Options 15767 * Sparc-Aligned-Data:: Option to enforce aligned data 15768 * Sparc-Syntax:: Syntax 15769 * Sparc-Float:: Floating Point 15770 * Sparc-Directives:: Sparc Machine Directives 15771 15772 15773 File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 15774 15775 9.35.1 Options 15776 -------------- 15777 15778 The SPARC chip family includes several successive versions, using the 15779 same core instruction set, but including a few additional instructions 15780 at each version. There are exceptions to this however. For details on 15781 what instructions each variant supports, please see the chip's 15782 architecture reference manual. 15783 15784 By default, `as' assumes the core instruction set (SPARC v6), but 15785 "bumps" the architecture level as needed: it switches to successively 15786 higher architectures as it encounters instructions that only exist in 15787 the higher levels. 15788 15789 If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump 15790 past sparclite by default, an option must be passed to enable the v9 15791 instructions. 15792 15793 GAS treats sparclite as being compatible with v8, unless an 15794 architecture is explicitly requested. SPARC v9 is always incompatible 15795 with sparclite. 15796 15797 `-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 15798 `-Av8plus | -Av8plusa | -Av9 | -Av9a' 15799 Use one of the `-A' options to select one of the SPARC 15800 architectures explicitly. If you select an architecture 15801 explicitly, `as' reports a fatal error if it encounters an 15802 instruction or feature requiring an incompatible or higher level. 15803 15804 `-Av8plus' and `-Av8plusa' select a 32 bit environment. 15805 15806 `-Av9' and `-Av9a' select a 64 bit environment and are not 15807 available unless GAS is explicitly configured with 64 bit 15808 environment support. 15809 15810 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 15811 UltraSPARC extensions. 15812 15813 `-xarch=v8plus | -xarch=v8plusa' 15814 For compatibility with the SunOS v9 assembler. These options are 15815 equivalent to -Av8plus and -Av8plusa, respectively. 15816 15817 `-bump' 15818 Warn whenever it is necessary to switch to another level. If an 15819 architecture level is explicitly requested, GAS will not issue 15820 warnings until that level is reached, and will then bump the level 15821 as required (except between incompatible levels). 15822 15823 `-32 | -64' 15824 Select the word size, either 32 bits or 64 bits. These options 15825 are only available with the ELF object file format, and require 15826 that the necessary BFD support has been included. 15827 15828 15829 File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 15830 15831 9.35.2 Enforcing aligned data 15832 ----------------------------- 15833 15834 SPARC GAS normally permits data to be misaligned. For example, it 15835 permits the `.long' pseudo-op to be used on a byte boundary. However, 15836 the native SunOS assemblers issue an error when they see misaligned 15837 data. 15838 15839 You can use the `--enforce-aligned-data' option to make SPARC GAS 15840 also issue an error about misaligned data, just as the SunOS assemblers 15841 do. 15842 15843 The `--enforce-aligned-data' option is not the default because gcc 15844 issues misaligned data pseudo-ops when it initializes certain packed 15845 data structures (structures defined using the `packed' attribute). You 15846 may have to assemble with GAS in order to initialize packed data 15847 structures in your own code. 15848 15849 15850 File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 15851 15852 9.35.3 Sparc Syntax 15853 ------------------- 15854 15855 The assembler syntax closely follows The Sparc Architecture Manual, 15856 versions 8 and 9, as well as most extensions defined by Sun for their 15857 UltraSPARC and Niagara line of processors. 15858 15859 * Menu: 15860 15861 * Sparc-Chars:: Special Characters 15862 * Sparc-Regs:: Register Names 15863 * Sparc-Constants:: Constant Names 15864 * Sparc-Relocs:: Relocations 15865 * Sparc-Size-Translations:: Size Translations 15866 15867 15868 File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 15869 15870 9.35.3.1 Special Characters 15871 ........................... 15872 15873 `#' is the line comment character. 15874 15875 `;' can be used instead of a newline to separate statements. 15876 15877 15878 File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 15879 15880 9.35.3.2 Register Names 15881 ....................... 15882 15883 The Sparc integer register file is broken down into global, outgoing, 15884 local, and incoming. 15885 15886 * The 8 global registers are referred to as `%gN'. 15887 15888 * The 8 outgoing registers are referred to as `%oN'. 15889 15890 * The 8 local registers are referred to as `%lN'. 15891 15892 * The 8 incoming registers are referred to as `%iN'. 15893 15894 * The frame pointer register `%i6' can be referenced using the alias 15895 `%fp'. 15896 15897 * The stack pointer register `%o6' can be referenced using the alias 15898 `%sp'. 15899 15900 Floating point registers are simply referred to as `%fN'. When 15901 assembling for pre-V9, only 32 floating point registers are available. 15902 For V9 and later there are 64, but there are restrictions when 15903 referencing the upper 32 registers. They can only be accessed as 15904 double or quad, and thus only even or quad numbered accesses are 15905 allowed. For example, `%f34' is a legal floating point register, but 15906 `%f35' is not. 15907 15908 Certain V9 instructions allow access to ancillary state registers. 15909 Most simply they can be referred to as `%asrN' where N can be from 16 15910 to 31. However, there are some aliases defined to reference ASR 15911 registers defined for various UltraSPARC processors: 15912 15913 * The tick compare register is referred to as `%tick_cmpr'. 15914 15915 * The system tick register is referred to as `%stick'. An alias, 15916 `%sys_tick', exists but is deprecated and should not be used by 15917 new software. 15918 15919 * The system tick compare register is referred to as `%stick_cmpr'. 15920 An alias, `%sys_tick_cmpr', exists but is deprecated and should 15921 not be used by new software. 15922 15923 * The software interrupt register is referred to as `%softint'. 15924 15925 * The set software interrupt register is referred to as 15926 `%set_softint'. The mnemonic `%softint_set' is provided as an 15927 alias. 15928 15929 * The clear software interrupt register is referred to as 15930 `%clear_softint'. The mnemonic `%softint_clear' is provided as an 15931 alias. 15932 15933 * The performance instrumentation counters register is referred to as 15934 `%pic'. 15935 15936 * The performance control register is referred to as `%pcr'. 15937 15938 * The graphics status register is referred to as `%gsr'. 15939 15940 * The V9 dispatch control register is referred to as `%dcr'. 15941 15942 Various V9 branch and conditional move instructions allow 15943 specification of which set of integer condition codes to test. These 15944 are referred to as `%xcc' and `%icc'. 15945 15946 In V9, there are 4 sets of floating point condition codes which are 15947 referred to as `%fccN'. 15948 15949 Several special privileged and non-privileged registers exist: 15950 15951 * The V9 address space identifier register is referred to as `%asi'. 15952 15953 * The V9 restorable windows register is referred to as `%canrestore'. 15954 15955 * The V9 savable windows register is referred to as `%cansave'. 15956 15957 * The V9 clean windows register is referred to as `%cleanwin'. 15958 15959 * The V9 current window pointer register is referred to as `%cwp'. 15960 15961 * The floating-point queue register is referred to as `%fq'. 15962 15963 * The V8 co-processor queue register is referred to as `%cq'. 15964 15965 * The floating point status register is referred to as `%fsr'. 15966 15967 * The other windows register is referred to as `%otherwin'. 15968 15969 * The V9 program counter register is referred to as `%pc'. 15970 15971 * The V9 next program counter register is referred to as `%npc'. 15972 15973 * The V9 processor interrupt level register is referred to as `%pil'. 15974 15975 * The V9 processor state register is referred to as `%pstate'. 15976 15977 * The trap base address register is referred to as `%tba'. 15978 15979 * The V9 tick register is referred to as `%tick'. 15980 15981 * The V9 trap level is referred to as `%tl'. 15982 15983 * The V9 trap program counter is referred to as `%tpc'. 15984 15985 * The V9 trap next program counter is referred to as `%tnpc'. 15986 15987 * The V9 trap state is referred to as `%tstate'. 15988 15989 * The V9 trap type is referred to as `%tt'. 15990 15991 * The V9 condition codes is referred to as `%ccr'. 15992 15993 * The V9 floating-point registers state is referred to as `%fprs'. 15994 15995 * The V9 version register is referred to as `%ver'. 15996 15997 * The V9 window state register is referred to as `%wstate'. 15998 15999 * The Y register is referred to as `%y'. 16000 16001 * The V8 window invalid mask register is referred to as `%wim'. 16002 16003 * The V8 processor state register is referred to as `%psr'. 16004 16005 * The V9 global register level register is referred to as `%gl'. 16006 16007 Several special register names exist for hypervisor mode code: 16008 16009 * The hyperprivileged processor state register is referred to as 16010 `%hpstate'. 16011 16012 * The hyperprivileged trap state register is referred to as 16013 `%htstate'. 16014 16015 * The hyperprivileged interrupt pending register is referred to as 16016 `%hintp'. 16017 16018 * The hyperprivileged trap base address register is referred to as 16019 `%htba'. 16020 16021 * The hyperprivileged implementation version register is referred to 16022 as `%hver'. 16023 16024 * The hyperprivileged system tick compare register is referred to as 16025 `%hstick_cmpr'. Note that there is no `%hstick' register, the 16026 normal `%stick' is used. 16027 16028 16029 File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 16030 16031 9.35.3.3 Constants 16032 .................. 16033 16034 Several Sparc instructions take an immediate operand field for which 16035 mnemonic names exist. Two such examples are `membar' and `prefetch'. 16036 Another example are the set of V9 memory access instruction that allow 16037 specification of an address space identifier. 16038 16039 The `membar' instruction specifies a memory barrier that is the 16040 defined by the operand which is a bitmask. The supported mask 16041 mnemonics are: 16042 16043 * `#Sync' requests that all operations (including nonmemory 16044 reference operations) appearing prior to the `membar' must have 16045 been performed and the effects of any exceptions become visible 16046 before any instructions after the `membar' may be initiated. This 16047 corresponds to `membar' cmask field bit 2. 16048 16049 * `#MemIssue' requests that all memory reference operations 16050 appearing prior to the `membar' must have been performed before 16051 any memory operation after the `membar' may be initiated. This 16052 corresponds to `membar' cmask field bit 1. 16053 16054 * `#Lookaside' requests that a store appearing prior to the `membar' 16055 must complete before any load following the `membar' referencing 16056 the same address can be initiated. This corresponds to `membar' 16057 cmask field bit 0. 16058 16059 * `#StoreStore' defines that the effects of all stores appearing 16060 prior to the `membar' instruction must be visible to all 16061 processors before the effect of any stores following the `membar'. 16062 Equivalent to the deprecated `stbar' instruction. This 16063 corresponds to `membar' mmask field bit 3. 16064 16065 * `#LoadStore' defines all loads appearing prior to the `membar' 16066 instruction must have been performed before the effect of any 16067 stores following the `membar' is visible to any other processor. 16068 This corresponds to `membar' mmask field bit 2. 16069 16070 * `#StoreLoad' defines that the effects of all stores appearing 16071 prior to the `membar' instruction must be visible to all 16072 processors before loads following the `membar' may be performed. 16073 This corresponds to `membar' mmask field bit 1. 16074 16075 * `#LoadLoad' defines that all loads appearing prior to the `membar' 16076 instruction must have been performed before any loads following 16077 the `membar' may be performed. This corresponds to `membar' mmask 16078 field bit 0. 16079 16080 16081 These values can be ored together, for example: 16082 16083 membar #Sync 16084 membar #StoreLoad | #LoadLoad 16085 membar #StoreLoad | #StoreStore 16086 16087 The `prefetch' and `prefetcha' instructions take a prefetch function 16088 code. The following prefetch function code constant mnemonics are 16089 available: 16090 16091 * `#n_reads' requests a prefetch for several reads, and corresponds 16092 to a prefetch function code of 0. 16093 16094 `#one_read' requests a prefetch for one read, and corresponds to a 16095 prefetch function code of 1. 16096 16097 `#n_writes' requests a prefetch for several writes (and possibly 16098 reads), and corresponds to a prefetch function code of 2. 16099 16100 `#one_write' requests a prefetch for one write, and corresponds to 16101 a prefetch function code of 3. 16102 16103 `#page' requests a prefetch page, and corresponds to a prefetch 16104 function code of 4. 16105 16106 `#invalidate' requests a prefetch invalidate, and corresponds to a 16107 prefetch function code of 16. 16108 16109 `#unified' requests a prefetch to the nearest unified cache, and 16110 corresponds to a prefetch function code of 17. 16111 16112 `#n_reads_strong' requests a strong prefetch for several reads, 16113 and corresponds to a prefetch function code of 20. 16114 16115 `#one_read_strong' requests a strong prefetch for one read, and 16116 corresponds to a prefetch function code of 21. 16117 16118 `#n_writes_strong' requests a strong prefetch for several writes, 16119 and corresponds to a prefetch function code of 22. 16120 16121 `#one_write_strong' requests a strong prefetch for one write, and 16122 corresponds to a prefetch function code of 23. 16123 16124 Onle one prefetch code may be specified. Here are some examples: 16125 16126 prefetch [%l0 + %l2], #one_read 16127 prefetch [%g2 + 8], #n_writes 16128 prefetcha [%g1] 0x8, #unified 16129 prefetcha [%o0 + 0x10] %asi, #n_reads 16130 16131 The actual behavior of a given prefetch function code is processor 16132 specific. If a processor does not implement a given prefetch 16133 function code, it will treat the prefetch instruction as a nop. 16134 16135 For instructions that accept an immediate address space identifier, 16136 `as' provides many mnemonics corresponding to V9 defined as well 16137 as UltraSPARC and Niagara extended values. For example, `#ASI_P' 16138 and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor 16139 specific manuals for details. 16140 16141 16142 16143 File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 16144 16145 9.35.3.4 Relocations 16146 .................... 16147 16148 ELF relocations are available as defined in the 32-bit and 64-bit Sparc 16149 ELF specifications. 16150 16151 `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is 16152 obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix' 16153 and `R_SPARC_LOX10' is obtained using `%lox'. For example: 16154 16155 sethi %hi(symbol), %g1 16156 or %g1, %lo(symbol), %g1 16157 16158 sethi %hix(symbol), %g1 16159 xor %g1, %lox(symbol), %g1 16160 16161 These "high" mnemonics extract bits 31:10 of their operand, and the 16162 "low" mnemonics extract bits 9:0 of their operand. 16163 16164 V9 code model relocations can be requested as follows: 16165 16166 * `R_SPARC_HH22' is requested using `%hh'. It can also be generated 16167 using `%uhi'. 16168 16169 * `R_SPARC_HM10' is requested using `%hm'. It can also be generated 16170 using `%ulo'. 16171 16172 * `R_SPARC_LM22' is requested using `%lm'. 16173 16174 * `R_SPARC_H44' is requested using `%h44'. 16175 16176 * `R_SPARC_M44' is requested using `%m44'. 16177 16178 * `R_SPARC_L44' is requested using `%l44'. 16179 16180 The PC relative relocation `R_SPARC_PC22' can be obtained by 16181 enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10' 16182 relocation can be obtained using `%pc10'. These are mostly used when 16183 assembling PIC code. For example, the standard PIC sequence on Sparc 16184 to get the base of the global offset table, PC relative, into a 16185 register, can be performed as: 16186 16187 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 16188 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 16189 16190 Several relocations exist to allow the link editor to potentially 16191 optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22' 16192 relocation can obtained by enclosing an operand inside of 16193 `%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained 16194 by enclosing an operand inside of `%gdop_lox10'. Likewise, 16195 `R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of 16196 `%gdop'. For example, assuming the GOT base is in register `%l7': 16197 16198 sethi %gdop_hix22(symbol), %l1 16199 xor %l1, %gdop_lox10(symbol), %l1 16200 ld [%l7 + %l1], %l2, %gdop(symbol) 16201 16202 There are many relocations that can be requested for access to 16203 thread local storage variables. All of the Sparc TLS mnemonics are 16204 supported: 16205 16206 * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'. 16207 16208 * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'. 16209 16210 * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'. 16211 16212 * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'. 16213 16214 * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'. 16215 16216 * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'. 16217 16218 * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'. 16219 16220 * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'. 16221 16222 * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'. 16223 16224 * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'. 16225 16226 * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'. 16227 16228 * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'. 16229 16230 * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'. 16231 16232 * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'. 16233 16234 * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'. 16235 16236 * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'. 16237 16238 * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'. 16239 16240 * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'. 16241 16242 Here are some example TLS model sequences. 16243 16244 First, General Dynamic: 16245 16246 sethi %tgd_hi22(symbol), %l1 16247 add %l1, %tgd_lo10(symbol), %l1 16248 add %l7, %l1, %o0, %tgd_add(symbol) 16249 call __tls_get_addr, %tgd_call(symbol) 16250 nop 16251 16252 Local Dynamic: 16253 16254 sethi %tldm_hi22(symbol), %l1 16255 add %l1, %tldm_lo10(symbol), %l1 16256 add %l7, %l1, %o0, %tldm_add(symbol) 16257 call __tls_get_addr, %tldm_call(symbol) 16258 nop 16259 16260 sethi %tldo_hix22(symbol), %l1 16261 xor %l1, %tldo_lox10(symbol), %l1 16262 add %o0, %l1, %l1, %tldo_add(symbol) 16263 16264 Initial Exec: 16265 16266 sethi %tie_hi22(symbol), %l1 16267 add %l1, %tie_lo10(symbol), %l1 16268 ld [%l7 + %l1], %o0, %tie_ld(symbol) 16269 add %g7, %o0, %o0, %tie_add(symbol) 16270 16271 sethi %tie_hi22(symbol), %l1 16272 add %l1, %tie_lo10(symbol), %l1 16273 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 16274 add %g7, %o0, %o0, %tie_add(symbol) 16275 16276 And finally, Local Exec: 16277 16278 sethi %tle_hix22(symbol), %l1 16279 add %l1, %tle_lox10(symbol), %l1 16280 add %g7, %l1, %l1 16281 16282 When assembling for 64-bit, and a secondary constant addend is 16283 specified in an address expression that would normally generate an 16284 `R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10' 16285 instead. 16286 16287 16288 File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 16289 16290 9.35.3.5 Size Translations 16291 .......................... 16292 16293 Often it is desirable to write code in an operand size agnostic manner. 16294 `as' provides support for this via operand size opcode translations. 16295 Translations are supported for loads, stores, shifts, compare-and-swap 16296 atomics, and the `clr' synthetic instruction. 16297 16298 If generating 32-bit code, `as' will generate the 32-bit opcode. 16299 Whereas if 64-bit code is being generated, the 64-bit opcode will be 16300 emitted. For example `ldn' will be transformed into `ld' for 32-bit 16301 code and `ldx' for 64-bit code. 16302 16303 Here is an example meant to demonstrate all the supported opcode 16304 translations: 16305 16306 ldn [%o0], %o1 16307 ldna [%o0] %asi, %o2 16308 stn %o1, [%o0] 16309 stna %o2, [%o0] %asi 16310 slln %o3, 3, %o3 16311 srln %o4, 8, %o4 16312 sran %o5, 12, %o5 16313 casn [%o0], %o1, %o2 16314 casna [%o0] %asi, %o1, %o2 16315 clrn %g1 16316 16317 In 32-bit mode `as' will emit: 16318 16319 ld [%o0], %o1 16320 lda [%o0] %asi, %o2 16321 st %o1, [%o0] 16322 sta %o2, [%o0] %asi 16323 sll %o3, 3, %o3 16324 srl %o4, 8, %o4 16325 sra %o5, 12, %o5 16326 cas [%o0], %o1, %o2 16327 casa [%o0] %asi, %o1, %o2 16328 clr %g1 16329 16330 And in 64-bit mode `as' will emit: 16331 16332 ldx [%o0], %o1 16333 ldxa [%o0] %asi, %o2 16334 stx %o1, [%o0] 16335 stxa %o2, [%o0] %asi 16336 sllx %o3, 3, %o3 16337 srlx %o4, 8, %o4 16338 srax %o5, 12, %o5 16339 casx [%o0], %o1, %o2 16340 casxa [%o0] %asi, %o1, %o2 16341 clrx %g1 16342 16343 Finally, the `.nword' translating directive is supported as well. 16344 It is documented in the section on Sparc machine directives. 16345 16346 16347 File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 16348 16349 9.35.4 Floating Point 16350 --------------------- 16351 16352 The Sparc uses IEEE floating-point numbers. 16353 16354 16355 File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 16356 16357 9.35.5 Sparc Machine Directives 16358 ------------------------------- 16359 16360 The Sparc version of `as' supports the following additional machine 16361 directives: 16362 16363 `.align' 16364 This must be followed by the desired alignment in bytes. 16365 16366 `.common' 16367 This must be followed by a symbol name, a positive number, and 16368 `"bss"'. This behaves somewhat like `.comm', but the syntax is 16369 different. 16370 16371 `.half' 16372 This is functionally identical to `.short'. 16373 16374 `.nword' 16375 On the Sparc, the `.nword' directive produces native word sized 16376 value, ie. if assembling with -32 it is equivalent to `.word', if 16377 assembling with -64 it is equivalent to `.xword'. 16378 16379 `.proc' 16380 This directive is ignored. Any text following it on the same line 16381 is also ignored. 16382 16383 `.register' 16384 This directive declares use of a global application or system 16385 register. It must be followed by a register name %g2, %g3, %g6 or 16386 %g7, comma and the symbol name for that register. If symbol name 16387 is `#scratch', it is a scratch register, if it is `#ignore', it 16388 just suppresses any errors about using undeclared global register, 16389 but does not emit any information about it into the object file. 16390 This can be useful e.g. if you save the register before use and 16391 restore it after. 16392 16393 `.reserve' 16394 This must be followed by a symbol name, a positive number, and 16395 `"bss"'. This behaves somewhat like `.lcomm', but the syntax is 16396 different. 16397 16398 `.seg' 16399 This must be followed by `"text"', `"data"', or `"data1"'. It 16400 behaves like `.text', `.data', or `.data 1'. 16401 16402 `.skip' 16403 This is functionally identical to the `.space' directive. 16404 16405 `.word' 16406 On the Sparc, the `.word' directive produces 32 bit values, 16407 instead of the 16 bit values it produces on many other machines. 16408 16409 `.xword' 16410 On the Sparc V9 processor, the `.xword' directive produces 64 bit 16411 values. 16412 16413 16414 File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 16415 16416 9.36 TIC54X Dependent Features 16417 ============================== 16418 16419 * Menu: 16420 16421 * TIC54X-Opts:: Command-line Options 16422 * TIC54X-Block:: Blocking 16423 * TIC54X-Env:: Environment Settings 16424 * TIC54X-Constants:: Constants Syntax 16425 * TIC54X-Subsyms:: String Substitution 16426 * TIC54X-Locals:: Local Label Syntax 16427 * TIC54X-Builtins:: Builtin Assembler Math Functions 16428 * TIC54X-Ext:: Extended Addressing Support 16429 * TIC54X-Directives:: Directives 16430 * TIC54X-Macros:: Macro Features 16431 * TIC54X-MMRegs:: Memory-mapped Registers 16432 16433 16434 File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 16435 16436 9.36.1 Options 16437 -------------- 16438 16439 The TMS320C54X version of `as' has a few machine-dependent options. 16440 16441 You can use the `-mfar-mode' option to enable extended addressing 16442 mode. All addresses will be assumed to be > 16 bits, and the 16443 appropriate relocation types will be used. This option is equivalent 16444 to using the `.far_mode' directive in the assembly code. If you do not 16445 use the `-mfar-mode' option, all references will be assumed to be 16 16446 bits. This option may be abbreviated to `-mf'. 16447 16448 You can use the `-mcpu' option to specify a particular CPU. This 16449 option is equivalent to using the `.version' directive in the assembly 16450 code. For recognized CPU codes, see *Note `.version': 16451 TIC54X-Directives. The default CPU version is `542'. 16452 16453 You can use the `-merrors-to-file' option to redirect error output 16454 to a file (this provided for those deficient environments which don't 16455 provide adequate output redirection). This option may be abbreviated to 16456 `-me'. 16457 16458 16459 File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 16460 16461 9.36.2 Blocking 16462 --------------- 16463 16464 A blocked section or memory block is guaranteed not to cross the 16465 blocking boundary (usually a page, or 128 words) if it is smaller than 16466 the blocking size, or to start on a page boundary if it is larger than 16467 the blocking size. 16468 16469 16470 File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 16471 16472 9.36.3 Environment Settings 16473 --------------------------- 16474 16475 `C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added 16476 to the list of directories normally searched for source and include 16477 files. `C54XDSP_DIR' will override `A_DIR'. 16478 16479 16480 File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 16481 16482 9.36.4 Constants Syntax 16483 ----------------------- 16484 16485 The TIC54X version of `as' allows the following additional constant 16486 formats, using a suffix to indicate the radix: 16487 16488 Binary `000000B, 011000b' 16489 Octal `10Q, 224q' 16490 Hexadecimal `45h, 0FH' 16491 16492 16493 File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 16494 16495 9.36.5 String Substitution 16496 -------------------------- 16497 16498 A subset of allowable symbols (which we'll call subsyms) may be assigned 16499 arbitrary string values. This is roughly equivalent to C preprocessor 16500 #define macros. When `as' encounters one of these symbols, the symbol 16501 is replaced in the input stream by its string value. Subsym names 16502 *must* begin with a letter. 16503 16504 Subsyms may be defined using the `.asg' and `.eval' directives 16505 (*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives. 16506 16507 Expansion is recursive until a previously encountered symbol is 16508 seen, at which point substitution stops. 16509 16510 In this example, x is replaced with SYM2; SYM2 is replaced with 16511 SYM1, and SYM1 is replaced with x. At this point, x has already been 16512 encountered and the substitution stops. 16513 16514 .asg "x",SYM1 16515 .asg "SYM1",SYM2 16516 .asg "SYM2",x 16517 add x,a ; final code assembled is "add x, a" 16518 16519 Macro parameters are converted to subsyms; a side effect of this is 16520 the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms 16521 defined within a macro will have global scope, unless the `.var' 16522 directive is used to identify the subsym as a local macro variable 16523 *note `.var': TIC54X-Directives. 16524 16525 Substitution may be forced in situations where replacement might be 16526 ambiguous by placing colons on either side of the subsym. The following 16527 code: 16528 16529 .eval "10",x 16530 LAB:X: add #x, a 16531 16532 When assembled becomes: 16533 16534 LAB10 add #10, a 16535 16536 Smaller parts of the string assigned to a subsym may be accessed with 16537 the following syntax: 16538 16539 ``:SYMBOL(CHAR_INDEX):'' 16540 Evaluates to a single-character string, the character at 16541 CHAR_INDEX. 16542 16543 ``:SYMBOL(START,LENGTH):'' 16544 Evaluates to a substring of SYMBOL beginning at START with length 16545 LENGTH. 16546 16547 16548 File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 16549 16550 9.36.6 Local Labels 16551 ------------------- 16552 16553 Local labels may be defined in two ways: 16554 16555 * $N, where N is a decimal number between 0 and 9 16556 16557 * LABEL?, where LABEL is any legal symbol name. 16558 16559 Local labels thus defined may be redefined or automatically 16560 generated. The scope of a local label is based on when it may be 16561 undefined or reset. This happens when one of the following situations 16562 is encountered: 16563 16564 * .newblock directive *note `.newblock': TIC54X-Directives. 16565 16566 * The current section is changed (.sect, .text, or .data) 16567 16568 * Entering or leaving an included file 16569 16570 * The macro scope where the label was defined is exited 16571 16572 16573 File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 16574 16575 9.36.7 Math Builtins 16576 -------------------- 16577 16578 The following built-in functions may be used to generate a 16579 floating-point value. All return a floating-point value except `$cvi', 16580 `$int', and `$sgn', which return an integer value. 16581 16582 ``$acos(EXPR)'' 16583 Returns the floating point arccosine of EXPR. 16584 16585 ``$asin(EXPR)'' 16586 Returns the floating point arcsine of EXPR. 16587 16588 ``$atan(EXPR)'' 16589 Returns the floating point arctangent of EXPR. 16590 16591 ``$atan2(EXPR1,EXPR2)'' 16592 Returns the floating point arctangent of EXPR1 / EXPR2. 16593 16594 ``$ceil(EXPR)'' 16595 Returns the smallest integer not less than EXPR as floating point. 16596 16597 ``$cosh(EXPR)'' 16598 Returns the floating point hyperbolic cosine of EXPR. 16599 16600 ``$cos(EXPR)'' 16601 Returns the floating point cosine of EXPR. 16602 16603 ``$cvf(EXPR)'' 16604 Returns the integer value EXPR converted to floating-point. 16605 16606 ``$cvi(EXPR)'' 16607 Returns the floating point value EXPR converted to integer. 16608 16609 ``$exp(EXPR)'' 16610 Returns the floating point value e ^ EXPR. 16611 16612 ``$fabs(EXPR)'' 16613 Returns the floating point absolute value of EXPR. 16614 16615 ``$floor(EXPR)'' 16616 Returns the largest integer that is not greater than EXPR as 16617 floating point. 16618 16619 ``$fmod(EXPR1,EXPR2)'' 16620 Returns the floating point remainder of EXPR1 / EXPR2. 16621 16622 ``$int(EXPR)'' 16623 Returns 1 if EXPR evaluates to an integer, zero otherwise. 16624 16625 ``$ldexp(EXPR1,EXPR2)'' 16626 Returns the floating point value EXPR1 * 2 ^ EXPR2. 16627 16628 ``$log10(EXPR)'' 16629 Returns the base 10 logarithm of EXPR. 16630 16631 ``$log(EXPR)'' 16632 Returns the natural logarithm of EXPR. 16633 16634 ``$max(EXPR1,EXPR2)'' 16635 Returns the floating point maximum of EXPR1 and EXPR2. 16636 16637 ``$min(EXPR1,EXPR2)'' 16638 Returns the floating point minimum of EXPR1 and EXPR2. 16639 16640 ``$pow(EXPR1,EXPR2)'' 16641 Returns the floating point value EXPR1 ^ EXPR2. 16642 16643 ``$round(EXPR)'' 16644 Returns the nearest integer to EXPR as a floating point number. 16645 16646 ``$sgn(EXPR)'' 16647 Returns -1, 0, or 1 based on the sign of EXPR. 16648 16649 ``$sin(EXPR)'' 16650 Returns the floating point sine of EXPR. 16651 16652 ``$sinh(EXPR)'' 16653 Returns the floating point hyperbolic sine of EXPR. 16654 16655 ``$sqrt(EXPR)'' 16656 Returns the floating point square root of EXPR. 16657 16658 ``$tan(EXPR)'' 16659 Returns the floating point tangent of EXPR. 16660 16661 ``$tanh(EXPR)'' 16662 Returns the floating point hyperbolic tangent of EXPR. 16663 16664 ``$trunc(EXPR)'' 16665 Returns the integer value of EXPR truncated towards zero as 16666 floating point. 16667 16668 16669 16670 File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 16671 16672 9.36.8 Extended Addressing 16673 -------------------------- 16674 16675 The `LDX' pseudo-op is provided for loading the extended addressing bits 16676 of a label or address. For example, if an address `_label' resides in 16677 extended program memory, the value of `_label' may be loaded as follows: 16678 ldx #_label,16,a ; loads extended bits of _label 16679 or #_label,a ; loads lower 16 bits of _label 16680 bacc a ; full address is in accumulator A 16681 16682 16683 File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 16684 16685 9.36.9 Directives 16686 ----------------- 16687 16688 `.align [SIZE]' 16689 `.even' 16690 Align the section program counter on the next boundary, based on 16691 SIZE. SIZE may be any power of 2. `.even' is equivalent to 16692 `.align' with a SIZE of 2. 16693 `1' 16694 Align SPC to word boundary 16695 16696 `2' 16697 Align SPC to longword boundary (same as .even) 16698 16699 `128' 16700 Align SPC to page boundary 16701 16702 `.asg STRING, NAME' 16703 Assign NAME the string STRING. String replacement is performed on 16704 STRING before assignment. 16705 16706 `.eval STRING, NAME' 16707 Evaluate the contents of string STRING and assign the result as a 16708 string to the subsym NAME. String replacement is performed on 16709 STRING before assignment. 16710 16711 `.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 16712 Reserve space for SYMBOL in the .bss section. SIZE is in words. 16713 If present, BLOCKING_FLAG indicates the allocated space should be 16714 aligned on a page boundary if it would otherwise cross a page 16715 boundary. If present, ALIGNMENT_FLAG causes the assembler to 16716 allocate SIZE on a long word boundary. 16717 16718 `.byte VALUE [,...,VALUE_N]' 16719 `.ubyte VALUE [,...,VALUE_N]' 16720 `.char VALUE [,...,VALUE_N]' 16721 `.uchar VALUE [,...,VALUE_N]' 16722 Place one or more bytes into consecutive words of the current 16723 section. The upper 8 bits of each word is zero-filled. If a 16724 label is used, it points to the word allocated for the first byte 16725 encountered. 16726 16727 `.clink ["SECTION_NAME"]' 16728 Set STYP_CLINK flag for this section, which indicates to the 16729 linker that if no symbols from this section are referenced, the 16730 section should not be included in the link. If SECTION_NAME is 16731 omitted, the current section is used. 16732 16733 `.c_mode' 16734 TBD. 16735 16736 `.copy "FILENAME" | FILENAME' 16737 `.include "FILENAME" | FILENAME' 16738 Read source statements from FILENAME. The normal include search 16739 path is used. Normally .copy will cause statements from the 16740 included file to be printed in the assembly listing and .include 16741 will not, but this distinction is not currently implemented. 16742 16743 `.data' 16744 Begin assembling code into the .data section. 16745 16746 `.double VALUE [,...,VALUE_N]' 16747 `.ldouble VALUE [,...,VALUE_N]' 16748 `.float VALUE [,...,VALUE_N]' 16749 `.xfloat VALUE [,...,VALUE_N]' 16750 Place an IEEE single-precision floating-point representation of 16751 one or more floating-point values into the current section. All 16752 but `.xfloat' align the result on a longword boundary. Values are 16753 stored most-significant word first. 16754 16755 `.drlist' 16756 `.drnolist' 16757 Control printing of directives to the listing file. Ignored. 16758 16759 `.emsg STRING' 16760 `.mmsg STRING' 16761 `.wmsg STRING' 16762 Emit a user-defined error, message, or warning, respectively. 16763 16764 `.far_mode' 16765 Use extended addressing when assembling statements. This should 16766 appear only once per file, and is equivalent to the -mfar-mode 16767 option *note `-mfar-mode': TIC54X-Opts. 16768 16769 `.fclist' 16770 `.fcnolist' 16771 Control printing of false conditional blocks to the listing file. 16772 16773 `.field VALUE [,SIZE]' 16774 Initialize a bitfield of SIZE bits in the current section. If 16775 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 16776 bits. If VALUE does not fit into SIZE bits, the value will be 16777 truncated. Successive `.field' directives will pack starting at 16778 the current word, filling the most significant bits first, and 16779 aligning to the start of the next word if the field size does not 16780 fit into the space remaining in the current word. A `.align' 16781 directive with an operand of 1 will force the next `.field' 16782 directive to begin packing into a new word. If a label is used, it 16783 points to the word that contains the specified field. 16784 16785 `.global SYMBOL [,...,SYMBOL_N]' 16786 `.def SYMBOL [,...,SYMBOL_N]' 16787 `.ref SYMBOL [,...,SYMBOL_N]' 16788 `.def' nominally identifies a symbol defined in the current file 16789 and available to other files. `.ref' identifies a symbol used in 16790 the current file but defined elsewhere. Both map to the standard 16791 `.global' directive. 16792 16793 `.half VALUE [,...,VALUE_N]' 16794 `.uhalf VALUE [,...,VALUE_N]' 16795 `.short VALUE [,...,VALUE_N]' 16796 `.ushort VALUE [,...,VALUE_N]' 16797 `.int VALUE [,...,VALUE_N]' 16798 `.uint VALUE [,...,VALUE_N]' 16799 `.word VALUE [,...,VALUE_N]' 16800 `.uword VALUE [,...,VALUE_N]' 16801 Place one or more values into consecutive words of the current 16802 section. If a label is used, it points to the word allocated for 16803 the first value encountered. 16804 16805 `.label SYMBOL' 16806 Define a special SYMBOL to refer to the load time address of the 16807 current section program counter. 16808 16809 `.length' 16810 `.width' 16811 Set the page length and width of the output listing file. Ignored. 16812 16813 `.list' 16814 `.nolist' 16815 Control whether the source listing is printed. Ignored. 16816 16817 `.long VALUE [,...,VALUE_N]' 16818 `.ulong VALUE [,...,VALUE_N]' 16819 `.xlong VALUE [,...,VALUE_N]' 16820 Place one or more 32-bit values into consecutive words in the 16821 current section. The most significant word is stored first. 16822 `.long' and `.ulong' align the result on a longword boundary; 16823 `xlong' does not. 16824 16825 `.loop [COUNT]' 16826 `.break [CONDITION]' 16827 `.endloop' 16828 Repeatedly assemble a block of code. `.loop' begins the block, and 16829 `.endloop' marks its termination. COUNT defaults to 1024, and 16830 indicates the number of times the block should be repeated. 16831 `.break' terminates the loop so that assembly begins after the 16832 `.endloop' directive. The optional CONDITION will cause the loop 16833 to terminate only if it evaluates to zero. 16834 16835 `MACRO_NAME .macro [PARAM1][,...PARAM_N]' 16836 `[.mexit]' 16837 `.endm' 16838 See the section on macros for more explanation (*Note 16839 TIC54X-Macros::. 16840 16841 `.mlib "FILENAME" | FILENAME' 16842 Load the macro library FILENAME. FILENAME must be an archived 16843 library (BFD ar-compatible) of text files, expected to contain 16844 only macro definitions. The standard include search path is used. 16845 16846 `.mlist' 16847 `.mnolist' 16848 Control whether to include macro and loop block expansions in the 16849 listing output. Ignored. 16850 16851 `.mmregs' 16852 Define global symbolic names for the 'c54x registers. Supposedly 16853 equivalent to executing `.set' directives for each register with 16854 its memory-mapped value, but in reality is provided only for 16855 compatibility and does nothing. 16856 16857 `.newblock' 16858 This directive resets any TIC54X local labels currently defined. 16859 Normal `as' local labels are unaffected. 16860 16861 `.option OPTION_LIST' 16862 Set listing options. Ignored. 16863 16864 `.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 16865 Designate SECTION_NAME for blocking. Blocking guarantees that a 16866 section will start on a page boundary (128 words) if it would 16867 otherwise cross a page boundary. Only initialized sections may be 16868 designated with this directive. See also *Note TIC54X-Block::. 16869 16870 `.sect "SECTION_NAME"' 16871 Define a named initialized section and make it the current section. 16872 16873 `SYMBOL .set "VALUE"' 16874 `SYMBOL .equ "VALUE"' 16875 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 16876 table. SYMBOL may not be previously defined. 16877 16878 `.space SIZE_IN_BITS' 16879 `.bes SIZE_IN_BITS' 16880 Reserve the given number of bits in the current section and 16881 zero-fill them. If a label is used with `.space', it points to the 16882 *first* word reserved. With `.bes', the label points to the 16883 *last* word reserved. 16884 16885 `.sslist' 16886 `.ssnolist' 16887 Controls the inclusion of subsym replacement in the listing 16888 output. Ignored. 16889 16890 `.string "STRING" [,...,"STRING_N"]' 16891 `.pstring "STRING" [,...,"STRING_N"]' 16892 Place 8-bit characters from STRING into the current section. 16893 `.string' zero-fills the upper 8 bits of each word, while 16894 `.pstring' puts two characters into each word, filling the 16895 most-significant bits first. Unused space is zero-filled. If a 16896 label is used, it points to the first word initialized. 16897 16898 `[STAG] .struct [OFFSET]' 16899 `[NAME_1] element [COUNT_1]' 16900 `[NAME_2] element [COUNT_2]' 16901 `[TNAME] .tag STAGX [TCOUNT]' 16902 `...' 16903 `[NAME_N] element [COUNT_N]' 16904 `[SSIZE] .endstruct' 16905 `LABEL .tag [STAG]' 16906 Assign symbolic offsets to the elements of a structure. STAG 16907 defines a symbol to use to reference the structure. OFFSET 16908 indicates a starting value to use for the first element 16909 encountered; otherwise it defaults to zero. Each element can have 16910 a named offset, NAME, which is a symbol assigned the value of the 16911 element's offset into the structure. If STAG is missing, these 16912 become global symbols. COUNT adjusts the offset that many times, 16913 as if `element' were an array. `element' may be one of `.byte', 16914 `.word', `.long', `.float', or any equivalent of those, and the 16915 structure offset is adjusted accordingly. `.field' and `.string' 16916 are also allowed; the size of `.field' is one bit, and `.string' 16917 is considered to be one word in size. Only element descriptors, 16918 structure/union tags, `.align' and conditional assembly directives 16919 are allowed within `.struct'/`.endstruct'. `.align' aligns member 16920 offsets to word boundaries only. SSIZE, if provided, will always 16921 be assigned the size of the structure. 16922 16923 The `.tag' directive, in addition to being used to define a 16924 structure/union element within a structure, may be used to apply a 16925 structure to a symbol. Once applied to LABEL, the individual 16926 structure elements may be applied to LABEL to produce the desired 16927 offsets using LABEL as the structure base. 16928 16929 `.tab' 16930 Set the tab size in the output listing. Ignored. 16931 16932 `[UTAG] .union' 16933 `[NAME_1] element [COUNT_1]' 16934 `[NAME_2] element [COUNT_2]' 16935 `[TNAME] .tag UTAGX[,TCOUNT]' 16936 `...' 16937 `[NAME_N] element [COUNT_N]' 16938 `[USIZE] .endstruct' 16939 `LABEL .tag [UTAG]' 16940 Similar to `.struct', but the offset after each element is reset to 16941 zero, and the USIZE is set to the maximum of all defined elements. 16942 Starting offset for the union is always zero. 16943 16944 `[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 16945 Reserve space for variables in a named, uninitialized section 16946 (similar to .bss). `.usect' allows definitions sections 16947 independent of .bss. SYMBOL points to the first location reserved 16948 by this allocation. The symbol may be used as a variable name. 16949 SIZE is the allocated size in words. BLOCKING_FLAG indicates 16950 whether to block this section on a page boundary (128 words) 16951 (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the 16952 section should be longword-aligned. 16953 16954 `.var SYM[,..., SYM_N]' 16955 Define a subsym to be a local variable within a macro. See *Note 16956 TIC54X-Macros::. 16957 16958 `.version VERSION' 16959 Set which processor to build instructions for. Though the 16960 following values are accepted, the op is ignored. 16961 `541' 16962 `542' 16963 `543' 16964 `545' 16965 `545LP' 16966 `546LP' 16967 `548' 16968 `549' 16969 16970 16971 File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 16972 16973 9.36.10 Macros 16974 -------------- 16975 16976 Macros do not require explicit dereferencing of arguments (i.e., \ARG). 16977 16978 During macro expansion, the macro parameters are converted to 16979 subsyms. If the number of arguments passed the macro invocation 16980 exceeds the number of parameters defined, the last parameter is 16981 assigned the string equivalent of all remaining arguments. If fewer 16982 arguments are given than parameters, the missing parameters are 16983 assigned empty strings. To include a comma in an argument, you must 16984 enclose the argument in quotes. 16985 16986 The following built-in subsym functions allow examination of the 16987 string value of subsyms (or ordinary strings). The arguments are 16988 strings unless otherwise indicated (subsyms passed as args will be 16989 replaced by the strings they represent). 16990 ``$symlen(STR)'' 16991 Returns the length of STR. 16992 16993 ``$symcmp(STR1,STR2)'' 16994 Returns 0 if STR1 == STR2, non-zero otherwise. 16995 16996 ``$firstch(STR,CH)'' 16997 Returns index of the first occurrence of character constant CH in 16998 STR. 16999 17000 ``$lastch(STR,CH)'' 17001 Returns index of the last occurrence of character constant CH in 17002 STR. 17003 17004 ``$isdefed(SYMBOL)'' 17005 Returns zero if the symbol SYMBOL is not in the symbol table, 17006 non-zero otherwise. 17007 17008 ``$ismember(SYMBOL,LIST)'' 17009 Assign the first member of comma-separated string LIST to SYMBOL; 17010 LIST is reassigned the remainder of the list. Returns zero if 17011 LIST is a null string. Both arguments must be subsyms. 17012 17013 ``$iscons(EXPR)'' 17014 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 17015 4 if a character, 5 if decimal, and zero if not an integer. 17016 17017 ``$isname(NAME)'' 17018 Returns 1 if NAME is a valid symbol name, zero otherwise. 17019 17020 ``$isreg(REG)'' 17021 Returns 1 if REG is a valid predefined register name (AR0-AR7 17022 only). 17023 17024 ``$structsz(STAG)'' 17025 Returns the size of the structure or union represented by STAG. 17026 17027 ``$structacc(STAG)'' 17028 Returns the reference point of the structure or union represented 17029 by STAG. Always returns zero. 17030 17031 17032 17033 File: as.info, Node: TIC54X-MMRegs, Prev: TIC54X-Macros, Up: TIC54X-Dependent 17034 17035 9.36.11 Memory-mapped Registers 17036 ------------------------------- 17037 17038 The following symbols are recognized as memory-mapped registers: 17039 17040 17041 17042 File: as.info, Node: TIC6X-Dependent, Next: V850-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 17043 17044 9.37 TIC6X Dependent Features 17045 ============================= 17046 17047 * Menu: 17048 17049 * TIC6X Options:: Options 17050 * TIC6X Syntax:: Syntax 17051 * TIC6X Directives:: Directives 17052 17053 17054 File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 17055 17056 9.37.1 TIC6X Options 17057 -------------------- 17058 17059 `-march=ARCH' 17060 Enable (only) instructions from architecture ARCH. By default, 17061 all instructions are permitted. 17062 17063 The following values of ARCH are accepted: `c62x', `c64x', 17064 `c64x+', `c67x', `c67x+', `c674x'. 17065 17066 `-matomic' 17067 `-mno-atomic' 17068 Enable or disable the optional C64x+ atomic operation instructions. 17069 By default, they are enabled if no `-march' option is given, or if 17070 an architecture is specified with `-march' that implies these 17071 instructions are present (currently, there are no such 17072 architectures); they are disabled if an architecture is specified 17073 with `-march' on which the instructions are optional or not 17074 present. This option overrides such a default from the 17075 architecture, independent of the order in which the `-march' or 17076 `-matomic' or `-mno-atomic' options are passed. 17077 17078 `-mdsbt' 17079 `-mno-dsbt' 17080 The `-mdsbt' option causes the assembler to generate the 17081 `Tag_ABI_DSBT' attribute with a value of 1, indicating that the 17082 code is using DSBT addressing. The `-mno-dsbt' option, the 17083 default, causes the tag to have a value of 0, indicating that the 17084 code does not use DSBT addressing. The linker will emit a warning 17085 if objects of different type (DSBT and non-DSBT) are linked 17086 together. 17087 17088 `-mpid=no' 17089 `-mpid=near' 17090 `-mpid=far' 17091 The `-mpid=' option causes the assembler to generate the 17092 `Tag_ABI_PID' attribute with a value indicating the form of data 17093 addressing used by the code. `-mpid=no', the default, indicates 17094 position-dependent data addressing, `-mpid=near' indicates 17095 position-independent addressing with GOT accesses using near DP 17096 addressing, and `-mpid=far' indicates position-independent 17097 addressing with GOT accesses using far DP addressing. The linker 17098 will emit a warning if objects built with different settings of 17099 this option are linked together. 17100 17101 `-mpic' 17102 `-mno-pic' 17103 The `-mpic' option causes the assembler to generate the 17104 `Tag_ABI_PIC' attribute with a value of 1, indicating that the 17105 code is using position-independent code addressing, The 17106 `-mno-pic' option, the default, causes the tag to have a value of 17107 0, indicating position-dependent code addressing. The linker will 17108 emit a warning if objects of different type (position-dependent and 17109 position-independent) are linked together. 17110 17111 `-mbig-endian' 17112 `-mlittle-endian' 17113 Generate code for the specified endianness. The default is 17114 little-endian. 17115 17116 17117 17118 File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 17119 17120 9.37.2 TIC6X Syntax 17121 ------------------- 17122 17123 The presence of a `;' on a line indicates the start of a comment that 17124 extends to the end of the current line. If a `#' or `*' appears as the 17125 first character of a line, the whole line is treated as a comment. 17126 17127 The `@' character can be used instead of a newline to separate 17128 statements. 17129 17130 Instruction, register and functional unit names are case-insensitive. 17131 `as' requires fully-specified functional unit names, such as `.S1', 17132 `.L1X' or `.D1T2', on all instructions using a functional unit. 17133 17134 For some instructions, there may be syntactic ambiguity between 17135 register or functional unit names and the names of labels or other 17136 symbols. To avoid this, enclose the ambiguous symbol name in 17137 parentheses; register and functional unit names may not be enclosed in 17138 parentheses. 17139 17140 17141 File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 17142 17143 9.37.3 TIC6X Directives 17144 ----------------------- 17145 17146 Directives controlling the set of instructions accepted by the 17147 assembler have effect for instructions between the directive and any 17148 subsequent directive overriding it. 17149 17150 `.arch ARCH' 17151 This has the same effect as `-march=ARCH'. 17152 17153 `.atomic' 17154 `.noatomic' 17155 These have the same effects as `-matomic' and `-mno-atomic'. 17156 17157 `.c6xabi_attribute TAG, VALUE' 17158 Set the C6000 EABI build attribute TAG to VALUE. 17159 17160 The TAG is either an attribute number or one of `Tag_ISA', 17161 `Tag_ABI_wchar_t', `Tag_ABI_stack_align_needed', 17162 `Tag_ABI_stack_align_preserved', `Tag_ABI_DSBT', `Tag_ABI_PID', 17163 `Tag_ABI_PIC', `TAG_ABI_array_object_alignment', 17164 `TAG_ABI_array_object_align_expected', `Tag_ABI_compatibility' and 17165 `Tag_ABI_conformance'. The VALUE is either a `number', 17166 `"string"', or `number, "string"' depending on the tag. 17167 17168 `.nocmp' 17169 Disallow use of C64x+ compact instructions in the current text 17170 section. 17171 17172 17173 17174 File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 17175 17176 9.38 Z80 Dependent Features 17177 =========================== 17178 17179 * Menu: 17180 17181 * Z80 Options:: Options 17182 * Z80 Syntax:: Syntax 17183 * Z80 Floating Point:: Floating Point 17184 * Z80 Directives:: Z80 Machine Directives 17185 * Z80 Opcodes:: Opcodes 17186 17187 17188 File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 17189 17190 9.38.1 Options 17191 -------------- 17192 17193 The Zilog Z80 and Ascii R800 version of `as' have a few machine 17194 dependent options. 17195 `-z80' 17196 Produce code for the Z80 processor. There are additional options to 17197 request warnings and error messages for undocumented instructions. 17198 17199 `-ignore-undocumented-instructions' 17200 `-Wnud' 17201 Silently assemble undocumented Z80-instructions that have been 17202 adopted as documented R800-instructions. 17203 17204 `-ignore-unportable-instructions' 17205 `-Wnup' 17206 Silently assemble all undocumented Z80-instructions. 17207 17208 `-warn-undocumented-instructions' 17209 `-Wud' 17210 Issue warnings for undocumented Z80-instructions that work on 17211 R800, do not assemble other undocumented instructions without 17212 warning. 17213 17214 `-warn-unportable-instructions' 17215 `-Wup' 17216 Issue warnings for other undocumented Z80-instructions, do not 17217 treat any undocumented instructions as errors. 17218 17219 `-forbid-undocumented-instructions' 17220 `-Fud' 17221 Treat all undocumented z80-instructions as errors. 17222 17223 `-forbid-unportable-instructions' 17224 `-Fup' 17225 Treat undocumented z80-instructions that do not work on R800 as 17226 errors. 17227 17228 `-r800' 17229 Produce code for the R800 processor. The assembler does not support 17230 undocumented instructions for the R800. In line with common 17231 practice, `as' uses Z80 instruction names for the R800 processor, 17232 as far as they exist. 17233 17234 17235 File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 17236 17237 9.38.2 Syntax 17238 ------------- 17239 17240 The assembler syntax closely follows the 'Z80 family CPU User Manual' by 17241 Zilog. In expressions a single `=' may be used as "is equal to" 17242 comparison operator. 17243 17244 Suffices can be used to indicate the radix of integer constants; `H' 17245 or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o' 17246 for octal, and `B' for binary. 17247 17248 The suffix `b' denotes a backreference to local label. 17249 17250 * Menu: 17251 17252 * Z80-Chars:: Special Characters 17253 * Z80-Regs:: Register Names 17254 * Z80-Case:: Case Sensitivity 17255 17256 17257 File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 17258 17259 9.38.2.1 Special Characters 17260 ........................... 17261 17262 The semicolon `;' is the line comment character; 17263 17264 The dollar sign `$' can be used as a prefix for hexadecimal numbers 17265 and as a symbol denoting the current location counter. 17266 17267 A backslash `\' is an ordinary character for the Z80 assembler. 17268 17269 The single quote `'' must be followed by a closing quote. If there 17270 is one character in between, it is a character constant, otherwise it is 17271 a string constant. 17272 17273 17274 File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 17275 17276 9.38.2.2 Register Names 17277 ....................... 17278 17279 The registers are referred to with the letters assigned to them by 17280 Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and 17281 most significant octet in `ix', and similarly `iyl' and `iyh' as parts 17282 of `iy'. 17283 17284 17285 File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax 17286 17287 9.38.2.3 Case Sensitivity 17288 ......................... 17289 17290 Upper and lower case are equivalent in register names, opcodes, 17291 condition codes and assembler directives. The case of letters is 17292 significant in labels and symbol names. The case is also important to 17293 distinguish the suffix `b' for a backward reference to a local label 17294 from the suffix `B' for a number in binary notation. 17295 17296 17297 File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 17298 17299 9.38.3 Floating Point 17300 --------------------- 17301 17302 Floating-point numbers are not supported. 17303 17304 17305 File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 17306 17307 9.38.4 Z80 Assembler Directives 17308 ------------------------------- 17309 17310 `as' for the Z80 supports some additional directives for compatibility 17311 with other assemblers. 17312 17313 These are the additional directives in `as' for the Z80: 17314 17315 `db EXPRESSION|STRING[,EXPRESSION|STRING...]' 17316 `defb EXPRESSION|STRING[,EXPRESSION|STRING...]' 17317 For each STRING the characters are copied to the object file, for 17318 each other EXPRESSION the value is stored in one byte. A warning 17319 is issued in case of an overflow. 17320 17321 `dw EXPRESSION[,EXPRESSION...]' 17322 `defw EXPRESSION[,EXPRESSION...]' 17323 For each EXPRESSION the value is stored in two bytes, ignoring 17324 overflow. 17325 17326 `d24 EXPRESSION[,EXPRESSION...]' 17327 `def24 EXPRESSION[,EXPRESSION...]' 17328 For each EXPRESSION the value is stored in three bytes, ignoring 17329 overflow. 17330 17331 `d32 EXPRESSION[,EXPRESSION...]' 17332 `def32 EXPRESSION[,EXPRESSION...]' 17333 For each EXPRESSION the value is stored in four bytes, ignoring 17334 overflow. 17335 17336 `ds COUNT[, VALUE]' 17337 `defs COUNT[, VALUE]' 17338 Fill COUNT bytes in the object file with VALUE, if VALUE is 17339 omitted it defaults to zero. 17340 17341 `SYMBOL equ EXPRESSION' 17342 `SYMBOL defl EXPRESSION' 17343 These directives set the value of SYMBOL to EXPRESSION. If `equ' 17344 is used, it is an error if SYMBOL is already defined. Symbols 17345 defined with `equ' are not protected from redefinition. 17346 17347 `set' 17348 This is a normal instruction on Z80, and not an assembler 17349 directive. 17350 17351 `psect NAME' 17352 A synonym for *Note Section::, no second argument should be given. 17353 17354 17355 17356 File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 17357 17358 9.38.5 Opcodes 17359 -------------- 17360 17361 In line with common practice, Z80 mnemonics are used for both the Z80 17362 and the R800. 17363 17364 In many instructions it is possible to use one of the half index 17365 registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general 17366 purpose register. This yields instructions that are documented on the 17367 R800 and undocumented on the Z80. Similarly `in f,(c)' is documented 17368 on the R800 and undocumented on the Z80. 17369 17370 The assembler also supports the following undocumented 17371 Z80-instructions, that have not been adopted in the R800 instruction 17372 set: 17373 `out (c),0' 17374 Sends zero to the port pointed to by register c. 17375 17376 `sli M' 17377 Equivalent to `M = (M<<1)+1', the operand M can be any operand 17378 that is valid for `sla'. One can use `sll' as a synonym for `sli'. 17379 17380 `OP (ix+D), R' 17381 This is equivalent to 17382 17383 ld R, (ix+D) 17384 OPC R 17385 ld (ix+D), R 17386 17387 The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc', 17388 `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R' 17389 may be any of `a', `b', `c', `d', `e', `h' and `l'. 17390 17391 `OPC (iy+D), R' 17392 As above, but with `iy' instead of `ix'. 17393 17394 The web site at `http://www.z80.info' is a good starting place to 17395 find more information on programming the Z80. 17396 17397 17398 File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 17399 17400 9.39 Z8000 Dependent Features 17401 ============================= 17402 17403 The Z8000 as supports both members of the Z8000 family: the 17404 unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 17405 24 bit addresses. 17406 17407 When the assembler is in unsegmented mode (specified with the 17408 `unsegm' directive), an address takes up one word (16 bit) sized 17409 register. When the assembler is in segmented mode (specified with the 17410 `segm' directive), a 24-bit address takes up a long (32 bit) register. 17411 *Note Assembler Directives for the Z8000: Z8000 Directives, for a list 17412 of other Z8000 specific assembler directives. 17413 17414 * Menu: 17415 17416 * Z8000 Options:: Command-line options for the Z8000 17417 * Z8000 Syntax:: Assembler syntax for the Z8000 17418 * Z8000 Directives:: Special directives for the Z8000 17419 * Z8000 Opcodes:: Opcodes 17420 17421 17422 File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 17423 17424 9.39.1 Options 17425 -------------- 17426 17427 `-z8001' 17428 Generate segmented code by default. 17429 17430 `-z8002' 17431 Generate unsegmented code by default. 17432 17433 17434 File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 17435 17436 9.39.2 Syntax 17437 ------------- 17438 17439 * Menu: 17440 17441 * Z8000-Chars:: Special Characters 17442 * Z8000-Regs:: Register Names 17443 * Z8000-Addressing:: Addressing Modes 17444 17445 17446 File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 17447 17448 9.39.2.1 Special Characters 17449 ........................... 17450 17451 `!' is the line comment character. 17452 17453 You can use `;' instead of a newline to separate statements. 17454 17455 17456 File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 17457 17458 9.39.2.2 Register Names 17459 ....................... 17460 17461 The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 17462 to different sized groups of registers by register number, with the 17463 prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for 17464 64 bit registers. You can also refer to the contents of the first 17465 eight (of the sixteen 16 bit registers) by bytes. They are named `rlN' 17466 and `rhN'. 17467 17468 _byte registers_ 17469 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 17470 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 17471 17472 _word registers_ 17473 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 17474 17475 _long word registers_ 17476 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 17477 17478 _quad word registers_ 17479 rq0 rq4 rq8 rq12 17480 17481 17482 File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 17483 17484 9.39.2.3 Addressing Modes 17485 ......................... 17486 17487 as understands the following addressing modes for the Z8000: 17488 17489 `rlN' 17490 `rhN' 17491 `rN' 17492 `rrN' 17493 `rqN' 17494 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 17495 17496 `@rN' 17497 `@rrN' 17498 Indirect register: @rrN in segmented mode, @rN in unsegmented 17499 mode. 17500 17501 `ADDR' 17502 Direct: the 16 bit or 24 bit address (depending on whether the 17503 assembler is in segmented or unsegmented mode) of the operand is 17504 in the instruction. 17505 17506 `address(rN)' 17507 Indexed: the 16 or 24 bit address is added to the 16 bit register 17508 to produce the final address in memory of the operand. 17509 17510 `rN(#IMM)' 17511 `rrN(#IMM)' 17512 Base Address: the 16 or 24 bit register is added to the 16 bit sign 17513 extended immediate displacement to produce the final address in 17514 memory of the operand. 17515 17516 `rN(rM)' 17517 `rrN(rM)' 17518 Base Index: the 16 or 24 bit register rN or rrN is added to the 17519 sign extended 16 bit index register rM to produce the final 17520 address in memory of the operand. 17521 17522 `#XX' 17523 Immediate data XX. 17524 17525 17526 File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 17527 17528 9.39.3 Assembler Directives for the Z8000 17529 ----------------------------------------- 17530 17531 The Z8000 port of as includes additional assembler directives, for 17532 compatibility with other Z8000 assemblers. These do not begin with `.' 17533 (unlike the ordinary as directives). 17534 17535 `segm' 17536 `.z8001' 17537 Generate code for the segmented Z8001. 17538 17539 `unsegm' 17540 `.z8002' 17541 Generate code for the unsegmented Z8002. 17542 17543 `name' 17544 Synonym for `.file' 17545 17546 `global' 17547 Synonym for `.global' 17548 17549 `wval' 17550 Synonym for `.word' 17551 17552 `lval' 17553 Synonym for `.long' 17554 17555 `bval' 17556 Synonym for `.byte' 17557 17558 `sval' 17559 Assemble a string. `sval' expects one string literal, delimited by 17560 single quotes. It assembles each byte of the string into 17561 consecutive addresses. You can use the escape sequence `%XX' 17562 (where XX represents a two-digit hexadecimal number) to represent 17563 the character whose ASCII value is XX. Use this feature to 17564 describe single quote and other characters that may not appear in 17565 string literals as themselves. For example, the C statement 17566 `char *a = "he said \"it's 50% off\"";' is represented in Z8000 17567 assembly language (shown with the assembler output in hex at the 17568 left) as 17569 17570 68652073 sval 'he said %22it%27s 50%25 off%22%00' 17571 61696420 17572 22697427 17573 73203530 17574 25206F66 17575 662200 17576 17577 `rsect' 17578 synonym for `.section' 17579 17580 `block' 17581 synonym for `.space' 17582 17583 `even' 17584 special case of `.align'; aligns output to even byte boundary. 17585 17586 17587 File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 17588 17589 9.39.4 Opcodes 17590 -------------- 17591 17592 For detailed information on the Z8000 machine instruction set, see 17593 `Z8000 Technical Manual'. 17594 17595 The following table summarizes the opcodes and their arguments: 17596 17597 rs 16 bit source register 17598 rd 16 bit destination register 17599 rbs 8 bit source register 17600 rbd 8 bit destination register 17601 rrs 32 bit source register 17602 rrd 32 bit destination register 17603 rqs 64 bit source register 17604 rqd 64 bit destination register 17605 addr 16/24 bit address 17606 imm immediate data 17607 17608 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 17609 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 17610 add rd,@rs clrb rbd dab rbd 17611 add rd,addr com @rd dbjnz rbd,disp7 17612 add rd,addr(rs) com addr dec @rd,imm4m1 17613 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 17614 add rd,rs com rd dec addr,imm4m1 17615 addb rbd,@rs comb @rd dec rd,imm4m1 17616 addb rbd,addr comb addr decb @rd,imm4m1 17617 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 17618 addb rbd,imm8 comb rbd decb addr,imm4m1 17619 addb rbd,rbs comflg flags decb rbd,imm4m1 17620 addl rrd,@rs cp @rd,imm16 di i2 17621 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 17622 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 17623 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 17624 addl rrd,rrs cp rd,addr div rrd,imm16 17625 and rd,@rs cp rd,addr(rs) div rrd,rs 17626 and rd,addr cp rd,imm16 divl rqd,@rs 17627 and rd,addr(rs) cp rd,rs divl rqd,addr 17628 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 17629 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 17630 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 17631 andb rbd,addr cpb rbd,@rs djnz rd,disp7 17632 andb rbd,addr(rs) cpb rbd,addr ei i2 17633 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 17634 andb rbd,rbs cpb rbd,imm8 ex rd,addr 17635 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 17636 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 17637 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 17638 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 17639 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 17640 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 17641 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 17642 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 17643 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 17644 bitb rbd,rs cpl rrd,@rs ext8f imm8 17645 bpt cpl rrd,addr exts rrd 17646 call @rd cpl rrd,addr(rs) extsb rd 17647 call addr cpl rrd,imm32 extsl rqd 17648 call addr(rd) cpl rrd,rrs halt 17649 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 17650 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 17651 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 17652 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 17653 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 17654 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 17655 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 17656 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 17657 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 17658 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 17659 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 17660 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 17661 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 17662 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 17663 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 17664 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 17665 iret ldib @rd,@rs,rr neg addr(rd) 17666 jp cc,@rd ldir @rd,@rs,rr neg rd 17667 jp cc,addr ldirb @rd,@rs,rr negb @rd 17668 jp cc,addr(rd) ldk rd,imm4 negb addr 17669 jr cc,disp8 ldl @rd,rrs negb addr(rd) 17670 ld @rd,imm16 ldl addr(rd),rrs negb rbd 17671 ld @rd,rs ldl addr,rrs nop 17672 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 17673 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 17674 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 17675 ld addr,rs ldl rrd,addr or rd,imm16 17676 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 17677 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 17678 ld rd,@rs ldl rrd,rrs orb rbd,addr 17679 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 17680 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 17681 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 17682 ld rd,rs ldm addr(rd),rs,n out @rd,rs 17683 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 17684 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 17685 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 17686 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 17687 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 17688 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 17689 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 17690 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 17691 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 17692 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 17693 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 17694 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 17695 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 17696 ldb rbd,@rs mbit popl addr,@rs 17697 ldb rbd,addr mreq rd popl rrd,@rs 17698 ldb rbd,addr(rs) mres push @rd,@rs 17699 ldb rbd,imm8 mset push @rd,addr 17700 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 17701 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 17702 push @rd,rs set addr,imm4 subl rrd,imm32 17703 pushl @rd,@rs set rd,imm4 subl rrd,rrs 17704 pushl @rd,addr set rd,rs tcc cc,rd 17705 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 17706 pushl @rd,rrs setb addr(rd),imm4 test @rd 17707 res @rd,imm4 setb addr,imm4 test addr 17708 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 17709 res addr,imm4 setb rbd,rs test rd 17710 res rd,imm4 setflg imm4 testb @rd 17711 res rd,rs sinb rbd,imm16 testb addr 17712 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 17713 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 17714 resb addr,imm4 sindb @rd,@rs,rba testl @rd 17715 resb rbd,imm4 sinib @rd,@rs,ra testl addr 17716 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 17717 resflg imm4 sla rd,imm8 testl rrd 17718 ret cc slab rbd,imm8 trdb @rd,@rs,rba 17719 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 17720 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 17721 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 17722 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 17723 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 17724 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 17725 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 17726 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 17727 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 17728 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 17729 rsvd36 sra rd,imm8 tset rd 17730 rsvd38 srab rbd,imm8 tsetb @rd 17731 rsvd78 sral rrd,imm8 tsetb addr 17732 rsvd7e srl rd,imm8 tsetb addr(rd) 17733 rsvd9d srlb rbd,imm8 tsetb rbd 17734 rsvd9f srll rrd,imm8 xor rd,@rs 17735 rsvdb9 sub rd,@rs xor rd,addr 17736 rsvdbf sub rd,addr xor rd,addr(rs) 17737 sbc rd,rs sub rd,addr(rs) xor rd,imm16 17738 sbcb rbd,rbs sub rd,imm16 xor rd,rs 17739 sc imm8 sub rd,rs xorb rbd,@rs 17740 sda rd,rs subb rbd,@rs xorb rbd,addr 17741 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 17742 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 17743 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 17744 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 17745 sdll rrd,rs subl rrd,@rs 17746 set @rd,imm4 subl rrd,addr 17747 set addr(rd),imm4 subl rrd,addr(rs) 17748 17749 17750 File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies 17751 17752 9.40 VAX Dependent Features 17753 =========================== 17754 17755 * Menu: 17756 17757 * VAX-Opts:: VAX Command-Line Options 17758 * VAX-float:: VAX Floating Point 17759 * VAX-directives:: Vax Machine Directives 17760 * VAX-opcodes:: VAX Opcodes 17761 * VAX-branch:: VAX Branch Improvement 17762 * VAX-operands:: VAX Operands 17763 * VAX-no:: Not Supported on VAX 17764 17765 17766 File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 17767 17768 9.40.1 VAX Command-Line Options 17769 ------------------------------- 17770 17771 The Vax version of `as' accepts any of the following options, gives a 17772 warning message that the option was ignored and proceeds. These 17773 options are for compatibility with scripts designed for other people's 17774 assemblers. 17775 17776 ``-D' (Debug)' 17777 ``-S' (Symbol Table)' 17778 ``-T' (Token Trace)' 17779 These are obsolete options used to debug old assemblers. 17780 17781 ``-d' (Displacement size for JUMPs)' 17782 This option expects a number following the `-d'. Like options 17783 that expect filenames, the number may immediately follow the `-d' 17784 (old standard) or constitute the whole of the command line 17785 argument that follows `-d' (GNU standard). 17786 17787 ``-V' (Virtualize Interpass Temporary File)' 17788 Some other assemblers use a temporary file. This option commanded 17789 them to keep the information in active memory rather than in a 17790 disk file. `as' always does this, so this option is redundant. 17791 17792 ``-J' (JUMPify Longer Branches)' 17793 Many 32-bit computers permit a variety of branch instructions to 17794 do the same job. Some of these instructions are short (and fast) 17795 but have a limited range; others are long (and slow) but can 17796 branch anywhere in virtual memory. Often there are 3 flavors of 17797 branch: short, medium and long. Some other assemblers would emit 17798 short and medium branches, unless told by this option to emit 17799 short and long branches. 17800 17801 ``-t' (Temporary File Directory)' 17802 Some other assemblers may use a temporary file, and this option 17803 takes a filename being the directory to site the temporary file. 17804 Since `as' does not use a temporary disk file, this option makes 17805 no difference. `-t' needs exactly one filename. 17806 17807 The Vax version of the assembler accepts additional options when 17808 compiled for VMS: 17809 17810 `-h N' 17811 External symbol or section (used for global variables) names are 17812 not case sensitive on VAX/VMS and always mapped to upper case. 17813 This is contrary to the C language definition which explicitly 17814 distinguishes upper and lower case. To implement a standard 17815 conforming C compiler, names must be changed (mapped) to preserve 17816 the case information. The default mapping is to convert all lower 17817 case characters to uppercase and adding an underscore followed by 17818 a 6 digit hex value, representing a 24 digit binary value. The 17819 one digits in the binary value represent which characters are 17820 uppercase in the original symbol name. 17821 17822 The `-h N' option determines how we map names. This takes several 17823 values. No `-h' switch at all allows case hacking as described 17824 above. A value of zero (`-h0') implies names should be upper 17825 case, and inhibits the case hack. A value of 2 (`-h2') implies 17826 names should be all lower case, with no case hack. A value of 3 17827 (`-h3') implies that case should be preserved. The value 1 is 17828 unused. The `-H' option directs `as' to display every mapped 17829 symbol during assembly. 17830 17831 Symbols whose names include a dollar sign `$' are exceptions to the 17832 general name mapping. These symbols are normally only used to 17833 reference VMS library names. Such symbols are always mapped to 17834 upper case. 17835 17836 `-+' 17837 The `-+' option causes `as' to truncate any symbol name larger 17838 than 31 characters. The `-+' option also prevents some code 17839 following the `_main' symbol normally added to make the object 17840 file compatible with Vax-11 "C". 17841 17842 `-1' 17843 This option is ignored for backward compatibility with `as' 17844 version 1.x. 17845 17846 `-H' 17847 The `-H' option causes `as' to print every symbol which was 17848 changed by case mapping. 17849 17850 17851 File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 17852 17853 9.40.2 VAX Floating Point 17854 ------------------------- 17855 17856 Conversion of flonums to floating point is correct, and compatible with 17857 previous assemblers. Rounding is towards zero if the remainder is 17858 exactly half the least significant bit. 17859 17860 `D', `F', `G' and `H' floating point formats are understood. 17861 17862 Immediate floating literals (_e.g._ `S`$6.9') are rendered 17863 correctly. Again, rounding is towards zero in the boundary case. 17864 17865 The `.float' directive produces `f' format numbers. The `.double' 17866 directive produces `d' format numbers. 17867 17868 17869 File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 17870 17871 9.40.3 Vax Machine Directives 17872 ----------------------------- 17873 17874 The Vax version of the assembler supports four directives for 17875 generating Vax floating point constants. They are described in the 17876 table below. 17877 17878 `.dfloat' 17879 This expects zero or more flonums, separated by commas, and 17880 assembles Vax `d' format 64-bit floating point constants. 17881 17882 `.ffloat' 17883 This expects zero or more flonums, separated by commas, and 17884 assembles Vax `f' format 32-bit floating point constants. 17885 17886 `.gfloat' 17887 This expects zero or more flonums, separated by commas, and 17888 assembles Vax `g' format 64-bit floating point constants. 17889 17890 `.hfloat' 17891 This expects zero or more flonums, separated by commas, and 17892 assembles Vax `h' format 128-bit floating point constants. 17893 17894 17895 17896 File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 17897 17898 9.40.4 VAX Opcodes 17899 ------------------ 17900 17901 All DEC mnemonics are supported. Beware that `case...' instructions 17902 have exactly 3 operands. The dispatch table that follows the `case...' 17903 instruction should be made with `.word' statements. This is compatible 17904 with all unix assemblers we know of. 17905 17906 17907 File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 17908 17909 9.40.5 VAX Branch Improvement 17910 ----------------------------- 17911 17912 Certain pseudo opcodes are permitted. They are for branch 17913 instructions. They expand to the shortest branch instruction that 17914 reaches the target. Generally these mnemonics are made by substituting 17915 `j' for `b' at the start of a DEC mnemonic. This feature is included 17916 both for compatibility and to help compilers. If you do not need this 17917 feature, avoid these opcodes. Here are the mnemonics, and the code 17918 they can expand into. 17919 17920 `jbsb' 17921 `Jsb' is already an instruction mnemonic, so we chose `jbsb'. 17922 (byte displacement) 17923 `bsbb ...' 17924 17925 (word displacement) 17926 `bsbw ...' 17927 17928 (long displacement) 17929 `jsb ...' 17930 17931 `jbr' 17932 `jr' 17933 Unconditional branch. 17934 (byte displacement) 17935 `brb ...' 17936 17937 (word displacement) 17938 `brw ...' 17939 17940 (long displacement) 17941 `jmp ...' 17942 17943 `jCOND' 17944 COND may be any one of the conditional branches `neq', `nequ', 17945 `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs', 17946 `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests 17947 `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs', 17948 `lbc'. NOTCOND is the opposite condition to COND. 17949 (byte displacement) 17950 `bCOND ...' 17951 17952 (word displacement) 17953 `bNOTCOND foo ; brw ... ; foo:' 17954 17955 (long displacement) 17956 `bNOTCOND foo ; jmp ... ; foo:' 17957 17958 `jacbX' 17959 X may be one of `b d f g h l w'. 17960 (word displacement) 17961 `OPCODE ...' 17962 17963 (long displacement) 17964 OPCODE ..., foo ; 17965 brb bar ; 17966 foo: jmp ... ; 17967 bar: 17968 17969 `jaobYYY' 17970 YYY may be one of `lss leq'. 17971 17972 `jsobZZZ' 17973 ZZZ may be one of `geq gtr'. 17974 (byte displacement) 17975 `OPCODE ...' 17976 17977 (word displacement) 17978 OPCODE ..., foo ; 17979 brb bar ; 17980 foo: brw DESTINATION ; 17981 bar: 17982 17983 (long displacement) 17984 OPCODE ..., foo ; 17985 brb bar ; 17986 foo: jmp DESTINATION ; 17987 bar: 17988 17989 `aobleq' 17990 `aoblss' 17991 `sobgeq' 17992 `sobgtr' 17993 17994 (byte displacement) 17995 `OPCODE ...' 17996 17997 (word displacement) 17998 OPCODE ..., foo ; 17999 brb bar ; 18000 foo: brw DESTINATION ; 18001 bar: 18002 18003 (long displacement) 18004 OPCODE ..., foo ; 18005 brb bar ; 18006 foo: jmp DESTINATION ; 18007 bar: 18008 18009 18010 File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 18011 18012 9.40.6 VAX Operands 18013 ------------------- 18014 18015 The immediate character is `$' for Unix compatibility, not `#' as DEC 18016 writes it. 18017 18018 The indirect character is `*' for Unix compatibility, not `@' as DEC 18019 writes it. 18020 18021 The displacement sizing character is ``' (an accent grave) for Unix 18022 compatibility, not `^' as DEC writes it. The letter preceding ``' may 18023 have either case. `G' is not understood, but all other letters (`b i l 18024 s w') are understood. 18025 18026 Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper 18027 and lower case letters are equivalent. 18028 18029 For instance 18030 tstb *w`$4(r5) 18031 18032 Any expression is permitted in an operand. Operands are comma 18033 separated. 18034 18035 18036 File: as.info, Node: VAX-no, Prev: VAX-operands, Up: Vax-Dependent 18037 18038 9.40.7 Not Supported on VAX 18039 --------------------------- 18040 18041 Vax bit fields can not be assembled with `as'. Someone can add the 18042 required code if they really need it. 18043 18044 18045 File: as.info, Node: V850-Dependent, Next: Xtensa-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 18046 18047 9.41 v850 Dependent Features 18048 ============================ 18049 18050 * Menu: 18051 18052 * V850 Options:: Options 18053 * V850 Syntax:: Syntax 18054 * V850 Floating Point:: Floating Point 18055 * V850 Directives:: V850 Machine Directives 18056 * V850 Opcodes:: Opcodes 18057 18058 18059 File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 18060 18061 9.41.1 Options 18062 -------------- 18063 18064 `as' supports the following additional command-line options for the 18065 V850 processor family: 18066 18067 `-wsigned_overflow' 18068 Causes warnings to be produced when signed immediate values 18069 overflow the space available for then within their opcodes. By 18070 default this option is disabled as it is possible to receive 18071 spurious warnings due to using exact bit patterns as immediate 18072 constants. 18073 18074 `-wunsigned_overflow' 18075 Causes warnings to be produced when unsigned immediate values 18076 overflow the space available for then within their opcodes. By 18077 default this option is disabled as it is possible to receive 18078 spurious warnings due to using exact bit patterns as immediate 18079 constants. 18080 18081 `-mv850' 18082 Specifies that the assembled code should be marked as being 18083 targeted at the V850 processor. This allows the linker to detect 18084 attempts to link such code with code assembled for other 18085 processors. 18086 18087 `-mv850e' 18088 Specifies that the assembled code should be marked as being 18089 targeted at the V850E processor. This allows the linker to detect 18090 attempts to link such code with code assembled for other 18091 processors. 18092 18093 `-mv850e1' 18094 Specifies that the assembled code should be marked as being 18095 targeted at the V850E1 processor. This allows the linker to 18096 detect attempts to link such code with code assembled for other 18097 processors. 18098 18099 `-mv850any' 18100 Specifies that the assembled code should be marked as being 18101 targeted at the V850 processor but support instructions that are 18102 specific to the extended variants of the process. This allows the 18103 production of binaries that contain target specific code, but 18104 which are also intended to be used in a generic fashion. For 18105 example libgcc.a contains generic routines used by the code 18106 produced by GCC for all versions of the v850 architecture, 18107 together with support routines only used by the V850E architecture. 18108 18109 `-mv850e2' 18110 Specifies that the assembled code should be marked as being 18111 targeted at the V850E2 processor. This allows the linker to 18112 detect attempts to link such code with code assembled for other 18113 processors. 18114 18115 `-mv850e2v3' 18116 Specifies that the assembled code should be marked as being 18117 targeted at the V850E2V3 processor. This allows the linker to 18118 detect attempts to link such code with code assembled for other 18119 processors. 18120 18121 `-mrelax' 18122 Enables relaxation. This allows the .longcall and .longjump pseudo 18123 ops to be used in the assembler source code. These ops label 18124 sections of code which are either a long function call or a long 18125 branch. The assembler will then flag these sections of code and 18126 the linker will attempt to relax them. 18127 18128 18129 18130 File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 18131 18132 9.41.2 Syntax 18133 ------------- 18134 18135 * Menu: 18136 18137 * V850-Chars:: Special Characters 18138 * V850-Regs:: Register Names 18139 18140 18141 File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 18142 18143 9.41.2.1 Special Characters 18144 ........................... 18145 18146 `#' is the line comment character. 18147 18148 18149 File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 18150 18151 9.41.2.2 Register Names 18152 ....................... 18153 18154 `as' supports the following names for registers: 18155 `general register 0' 18156 r0, zero 18157 18158 `general register 1' 18159 r1 18160 18161 `general register 2' 18162 r2, hp 18163 18164 `general register 3' 18165 r3, sp 18166 18167 `general register 4' 18168 r4, gp 18169 18170 `general register 5' 18171 r5, tp 18172 18173 `general register 6' 18174 r6 18175 18176 `general register 7' 18177 r7 18178 18179 `general register 8' 18180 r8 18181 18182 `general register 9' 18183 r9 18184 18185 `general register 10' 18186 r10 18187 18188 `general register 11' 18189 r11 18190 18191 `general register 12' 18192 r12 18193 18194 `general register 13' 18195 r13 18196 18197 `general register 14' 18198 r14 18199 18200 `general register 15' 18201 r15 18202 18203 `general register 16' 18204 r16 18205 18206 `general register 17' 18207 r17 18208 18209 `general register 18' 18210 r18 18211 18212 `general register 19' 18213 r19 18214 18215 `general register 20' 18216 r20 18217 18218 `general register 21' 18219 r21 18220 18221 `general register 22' 18222 r22 18223 18224 `general register 23' 18225 r23 18226 18227 `general register 24' 18228 r24 18229 18230 `general register 25' 18231 r25 18232 18233 `general register 26' 18234 r26 18235 18236 `general register 27' 18237 r27 18238 18239 `general register 28' 18240 r28 18241 18242 `general register 29' 18243 r29 18244 18245 `general register 30' 18246 r30, ep 18247 18248 `general register 31' 18249 r31, lp 18250 18251 `system register 0' 18252 eipc 18253 18254 `system register 1' 18255 eipsw 18256 18257 `system register 2' 18258 fepc 18259 18260 `system register 3' 18261 fepsw 18262 18263 `system register 4' 18264 ecr 18265 18266 `system register 5' 18267 psw 18268 18269 `system register 16' 18270 ctpc 18271 18272 `system register 17' 18273 ctpsw 18274 18275 `system register 18' 18276 dbpc 18277 18278 `system register 19' 18279 dbpsw 18280 18281 `system register 20' 18282 ctbp 18283 18284 18285 File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 18286 18287 9.41.3 Floating Point 18288 --------------------- 18289 18290 The V850 family uses IEEE floating-point numbers. 18291 18292 18293 File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 18294 18295 9.41.4 V850 Machine Directives 18296 ------------------------------ 18297 18298 `.offset <EXPRESSION>' 18299 Moves the offset into the current section to the specified amount. 18300 18301 `.section "name", <type>' 18302 This is an extension to the standard .section directive. It sets 18303 the current section to be <type> and creates an alias for this 18304 section called "name". 18305 18306 `.v850' 18307 Specifies that the assembled code should be marked as being 18308 targeted at the V850 processor. This allows the linker to detect 18309 attempts to link such code with code assembled for other 18310 processors. 18311 18312 `.v850e' 18313 Specifies that the assembled code should be marked as being 18314 targeted at the V850E processor. This allows the linker to detect 18315 attempts to link such code with code assembled for other 18316 processors. 18317 18318 `.v850e1' 18319 Specifies that the assembled code should be marked as being 18320 targeted at the V850E1 processor. This allows the linker to 18321 detect attempts to link such code with code assembled for other 18322 processors. 18323 18324 `.v850e2' 18325 Specifies that the assembled code should be marked as being 18326 targeted at the V850E2 processor. This allows the linker to 18327 detect attempts to link such code with code assembled for other 18328 processors. 18329 18330 `.v850e2v3' 18331 Specifies that the assembled code should be marked as being 18332 targeted at the V850E2V3 processor. This allows the linker to 18333 detect attempts to link such code with code assembled for other 18334 processors. 18335 18336 18337 18338 File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 18339 18340 9.41.5 Opcodes 18341 -------------- 18342 18343 `as' implements all the standard V850 opcodes. 18344 18345 `as' also implements the following pseudo ops: 18346 18347 `hi0()' 18348 Computes the higher 16 bits of the given expression and stores it 18349 into the immediate operand field of the given instruction. For 18350 example: 18351 18352 `mulhi hi0(here - there), r5, r6' 18353 18354 computes the difference between the address of labels 'here' and 18355 'there', takes the upper 16 bits of this difference, shifts it 18356 down 16 bits and then multiplies it by the lower 16 bits in 18357 register 5, putting the result into register 6. 18358 18359 `lo()' 18360 Computes the lower 16 bits of the given expression and stores it 18361 into the immediate operand field of the given instruction. For 18362 example: 18363 18364 `addi lo(here - there), r5, r6' 18365 18366 computes the difference between the address of labels 'here' and 18367 'there', takes the lower 16 bits of this difference and adds it to 18368 register 5, putting the result into register 6. 18369 18370 `hi()' 18371 Computes the higher 16 bits of the given expression and then adds 18372 the value of the most significant bit of the lower 16 bits of the 18373 expression and stores the result into the immediate operand field 18374 of the given instruction. For example the following code can be 18375 used to compute the address of the label 'here' and store it into 18376 register 6: 18377 18378 `movhi hi(here), r0, r6' `movea lo(here), r6, r6' 18379 18380 The reason for this special behaviour is that movea performs a sign 18381 extension on its immediate operand. So for example if the address 18382 of 'here' was 0xFFFFFFFF then without the special behaviour of the 18383 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 18384 then the movea instruction would takes its immediate operand, 18385 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it 18386 into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). 18387 With the hi() pseudo op adding in the top bit of the lo() pseudo 18388 op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 18389 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - 18390 the right value. 18391 18392 `hilo()' 18393 Computes the 32 bit value of the given expression and stores it 18394 into the immediate operand field of the given instruction (which 18395 must be a mov instruction). For example: 18396 18397 `mov hilo(here), r6' 18398 18399 computes the absolute address of label 'here' and puts the result 18400 into register 6. 18401 18402 `sdaoff()' 18403 Computes the offset of the named variable from the start of the 18404 Small Data Area (whoes address is held in register 4, the GP 18405 register) and stores the result as a 16 bit signed value in the 18406 immediate operand field of the given instruction. For example: 18407 18408 `ld.w sdaoff(_a_variable)[gp],r6' 18409 18410 loads the contents of the location pointed to by the label 18411 '_a_variable' into register 6, provided that the label is located 18412 somewhere within +/- 32K of the address held in the GP register. 18413 [Note the linker assumes that the GP register contains a fixed 18414 address set to the address of the label called '__gp'. This can 18415 either be set up automatically by the linker, or specifically set 18416 by using the `--defsym __gp=<value>' command line option]. 18417 18418 `tdaoff()' 18419 Computes the offset of the named variable from the start of the 18420 Tiny Data Area (whoes address is held in register 30, the EP 18421 register) and stores the result as a 4,5, 7 or 8 bit unsigned 18422 value in the immediate operand field of the given instruction. 18423 For example: 18424 18425 `sld.w tdaoff(_a_variable)[ep],r6' 18426 18427 loads the contents of the location pointed to by the label 18428 '_a_variable' into register 6, provided that the label is located 18429 somewhere within +256 bytes of the address held in the EP 18430 register. [Note the linker assumes that the EP register contains 18431 a fixed address set to the address of the label called '__ep'. 18432 This can either be set up automatically by the linker, or 18433 specifically set by using the `--defsym __ep=<value>' command line 18434 option]. 18435 18436 `zdaoff()' 18437 Computes the offset of the named variable from address 0 and 18438 stores the result as a 16 bit signed value in the immediate 18439 operand field of the given instruction. For example: 18440 18441 `movea zdaoff(_a_variable),zero,r6' 18442 18443 puts the address of the label '_a_variable' into register 6, 18444 assuming that the label is somewhere within the first 32K of 18445 memory. (Strictly speaking it also possible to access the last 18446 32K of memory as well, as the offsets are signed). 18447 18448 `ctoff()' 18449 Computes the offset of the named variable from the start of the 18450 Call Table Area (whoes address is helg in system register 20, the 18451 CTBP register) and stores the result a 6 or 16 bit unsigned value 18452 in the immediate field of then given instruction or piece of data. 18453 For example: 18454 18455 `callt ctoff(table_func1)' 18456 18457 will put the call the function whoes address is held in the call 18458 table at the location labeled 'table_func1'. 18459 18460 `.longcall `name'' 18461 Indicates that the following sequence of instructions is a long 18462 call to function `name'. The linker will attempt to shorten this 18463 call sequence if `name' is within a 22bit offset of the call. Only 18464 valid if the `-mrelax' command line switch has been enabled. 18465 18466 `.longjump `name'' 18467 Indicates that the following sequence of instructions is a long 18468 jump to label `name'. The linker will attempt to shorten this code 18469 sequence if `name' is within a 22bit offset of the jump. Only 18470 valid if the `-mrelax' command line switch has been enabled. 18471 18472 18473 For information on the V850 instruction set, see `V850 Family 18474 32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 18475 Ltd. 18476 18477 18478 File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 18479 18480 9.42 Xtensa Dependent Features 18481 ============================== 18482 18483 This chapter covers features of the GNU assembler that are specific 18484 to the Xtensa architecture. For details about the Xtensa instruction 18485 set, please consult the `Xtensa Instruction Set Architecture (ISA) 18486 Reference Manual'. 18487 18488 * Menu: 18489 18490 * Xtensa Options:: Command-line Options. 18491 * Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 18492 * Xtensa Optimizations:: Assembler Optimizations. 18493 * Xtensa Relaxation:: Other Automatic Transformations. 18494 * Xtensa Directives:: Directives for Xtensa Processors. 18495 18496 18497 File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 18498 18499 9.42.1 Command Line Options 18500 --------------------------- 18501 18502 The Xtensa version of the GNU assembler supports these special options: 18503 18504 `--text-section-literals | --no-text-section-literals' 18505 Control the treatment of literal pools. The default is 18506 `--no-text-section-literals', which places literals in separate 18507 sections in the output file. This allows the literal pool to be 18508 placed in a data RAM/ROM. With `--text-section-literals', the 18509 literals are interspersed in the text section in order to keep 18510 them as close as possible to their references. This may be 18511 necessary for large assembly files, where the literals would 18512 otherwise be out of range of the `L32R' instructions in the text 18513 section. These options only affect literals referenced via 18514 PC-relative `L32R' instructions; literals for absolute mode `L32R' 18515 instructions are handled separately. *Note literal: Literal 18516 Directive. 18517 18518 `--absolute-literals | --no-absolute-literals' 18519 Indicate to the assembler whether `L32R' instructions use absolute 18520 or PC-relative addressing. If the processor includes the absolute 18521 addressing option, the default is to use absolute `L32R' 18522 relocations. Otherwise, only the PC-relative `L32R' relocations 18523 can be used. 18524 18525 `--target-align | --no-target-align' 18526 Enable or disable automatic alignment to reduce branch penalties 18527 at some expense in code size. *Note Automatic Instruction 18528 Alignment: Xtensa Automatic Alignment. This optimization is 18529 enabled by default. Note that the assembler will always align 18530 instructions like `LOOP' that have fixed alignment requirements. 18531 18532 `--longcalls | --no-longcalls' 18533 Enable or disable transformation of call instructions to allow 18534 calls across a greater range of addresses. *Note Function Call 18535 Relaxation: Xtensa Call Relaxation. This option should be used 18536 when call targets can potentially be out of range. It may degrade 18537 both code size and performance, but the linker can generally 18538 optimize away the unnecessary overhead when a call ends up within 18539 range. The default is `--no-longcalls'. 18540 18541 `--transform | --no-transform' 18542 Enable or disable all assembler transformations of Xtensa 18543 instructions, including both relaxation and optimization. The 18544 default is `--transform'; `--no-transform' should only be used in 18545 the rare cases when the instructions must be exactly as specified 18546 in the assembly source. Using `--no-transform' causes out of range 18547 instruction operands to be errors. 18548 18549 `--rename-section OLDNAME=NEWNAME' 18550 Rename the OLDNAME section to NEWNAME. This option can be used 18551 multiple times to rename multiple sections. 18552 18553 18554 File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 18555 18556 9.42.2 Assembler Syntax 18557 ----------------------- 18558 18559 Block comments are delimited by `/*' and `*/'. End of line comments 18560 may be introduced with either `#' or `//'. 18561 18562 Instructions consist of a leading opcode or macro name followed by 18563 whitespace and an optional comma-separated list of operands: 18564 18565 OPCODE [OPERAND, ...] 18566 18567 Instructions must be separated by a newline or semicolon. 18568 18569 FLIX instructions, which bundle multiple opcodes together in a single 18570 instruction, are specified by enclosing the bundled opcodes inside 18571 braces: 18572 18573 { 18574 [FORMAT] 18575 OPCODE0 [OPERANDS] 18576 OPCODE1 [OPERANDS] 18577 OPCODE2 [OPERANDS] 18578 ... 18579 } 18580 18581 The opcodes in a FLIX instruction are listed in the same order as the 18582 corresponding instruction slots in the TIE format declaration. 18583 Directives and labels are not allowed inside the braces of a FLIX 18584 instruction. A particular TIE format name can optionally be specified 18585 immediately after the opening brace, but this is usually unnecessary. 18586 The assembler will automatically search for a format that can encode the 18587 specified opcodes, so the format name need only be specified in rare 18588 cases where there is more than one applicable format and where it 18589 matters which of those formats is used. A FLIX instruction can also be 18590 specified on a single line by separating the opcodes with semicolons: 18591 18592 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 18593 18594 If an opcode can only be encoded in a FLIX instruction but is not 18595 specified as part of a FLIX bundle, the assembler will choose the 18596 smallest format where the opcode can be encoded and will fill unused 18597 instruction slots with no-ops. 18598 18599 * Menu: 18600 18601 * Xtensa Opcodes:: Opcode Naming Conventions. 18602 * Xtensa Registers:: Register Naming. 18603 18604 18605 File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 18606 18607 9.42.2.1 Opcode Names 18608 ..................... 18609 18610 See the `Xtensa Instruction Set Architecture (ISA) Reference Manual' 18611 for a complete list of opcodes and descriptions of their semantics. 18612 18613 If an opcode name is prefixed with an underscore character (`_'), 18614 `as' will not transform that instruction in any way. The underscore 18615 prefix disables both optimization (*note Xtensa Optimizations: Xtensa 18616 Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 18617 Relaxation.) for that particular instruction. Only use the underscore 18618 prefix when it is essential to select the exact opcode produced by the 18619 assembler. Using this feature unnecessarily makes the code less 18620 efficient by disabling assembler optimization and less flexible by 18621 disabling relaxation. 18622 18623 Note that this special handling of underscore prefixes only applies 18624 to Xtensa opcodes, not to either built-in macros or user-defined macros. 18625 When an underscore prefix is used with a macro (e.g., `_MOV'), it 18626 refers to a different macro. The assembler generally provides built-in 18627 macros both with and without the underscore prefix, where the underscore 18628 versions behave as if the underscore carries through to the instructions 18629 in the macros. For example, `_MOV' may expand to `_MOV.N'. 18630 18631 The underscore prefix only applies to individual instructions, not to 18632 series of instructions. For example, if a series of instructions have 18633 underscore prefixes, the assembler will not transform the individual 18634 instructions, but it may insert other instructions between them (e.g., 18635 to align a `LOOP' instruction). To prevent the assembler from 18636 modifying a series of instructions as a whole, use the `no-transform' 18637 directive. *Note transform: Transform Directive. 18638 18639 18640 File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 18641 18642 9.42.2.2 Register Names 18643 ....................... 18644 18645 The assembly syntax for a register file entry is the "short" name for a 18646 TIE register file followed by the index into that register file. For 18647 example, the general-purpose `AR' register file has a short name of 18648 `a', so these registers are named `a0'...`a15'. As a special feature, 18649 `sp' is also supported as a synonym for `a1'. Additional registers may 18650 be added by processor configuration options and by designer-defined TIE 18651 extensions. An initial `$' character is optional in all register names. 18652 18653 18654 File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 18655 18656 9.42.3 Xtensa Optimizations 18657 --------------------------- 18658 18659 The optimizations currently supported by `as' are generation of density 18660 instructions where appropriate and automatic branch target alignment. 18661 18662 * Menu: 18663 18664 * Density Instructions:: Using Density Instructions. 18665 * Xtensa Automatic Alignment:: Automatic Instruction Alignment. 18666 18667 18668 File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 18669 18670 9.42.3.1 Using Density Instructions 18671 ................................... 18672 18673 The Xtensa instruction set has a code density option that provides 18674 16-bit versions of some of the most commonly used opcodes. Use of these 18675 opcodes can significantly reduce code size. When possible, the 18676 assembler automatically translates instructions from the core Xtensa 18677 instruction set into equivalent instructions from the Xtensa code 18678 density option. This translation can be disabled by using underscore 18679 prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 18680 `--no-transform' command-line option (*note Command Line Options: 18681 Xtensa Options.), or by using the `no-transform' directive (*note 18682 transform: Transform Directive.). 18683 18684 It is a good idea _not_ to use the density instructions directly. 18685 The assembler will automatically select dense instructions where 18686 possible. If you later need to use an Xtensa processor without the code 18687 density option, the same assembly code will then work without 18688 modification. 18689 18690 18691 File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 18692 18693 9.42.3.2 Automatic Instruction Alignment 18694 ........................................ 18695 18696 The Xtensa assembler will automatically align certain instructions, both 18697 to optimize performance and to satisfy architectural requirements. 18698 18699 As an optimization to improve performance, the assembler attempts to 18700 align branch targets so they do not cross instruction fetch boundaries. 18701 (Xtensa processors can be configured with either 32-bit or 64-bit 18702 instruction fetch widths.) An instruction immediately following a call 18703 is treated as a branch target in this context, because it will be the 18704 target of a return from the call. This alignment has the potential to 18705 reduce branch penalties at some expense in code size. This 18706 optimization is enabled by default. You can disable it with the 18707 `--no-target-align' command-line option (*note Command Line Options: 18708 Xtensa Options.). 18709 18710 The target alignment optimization is done without adding instructions 18711 that could increase the execution time of the program. If there are 18712 density instructions in the code preceding a target, the assembler can 18713 change the target alignment by widening some of those instructions to 18714 the equivalent 24-bit instructions. Extra bytes of padding can be 18715 inserted immediately following unconditional jump and return 18716 instructions. This approach is usually successful in aligning many, 18717 but not all, branch targets. 18718 18719 The `LOOP' family of instructions must be aligned such that the 18720 first instruction in the loop body does not cross an instruction fetch 18721 boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be 18722 on either a 1 or 2 mod 4 byte boundary). The assembler knows about 18723 this restriction and inserts the minimal number of 2 or 3 byte no-op 18724 instructions to satisfy it. When no-op instructions are added, any 18725 label immediately preceding the original loop will be moved in order to 18726 refer to the loop instruction, not the newly generated no-op 18727 instruction. To preserve binary compatibility across processors with 18728 different fetch widths, the assembler conservatively assumes a 32-bit 18729 fetch width when aligning `LOOP' instructions (except if the first 18730 instruction in the loop is a 64-bit instruction). 18731 18732 Previous versions of the assembler automatically aligned `ENTRY' 18733 instructions to 4-byte boundaries, but that alignment is now the 18734 programmer's responsibility. 18735 18736 18737 File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 18738 18739 9.42.4 Xtensa Relaxation 18740 ------------------------ 18741 18742 When an instruction operand is outside the range allowed for that 18743 particular instruction field, `as' can transform the code to use a 18744 functionally-equivalent instruction or sequence of instructions. This 18745 process is known as "relaxation". This is typically done for branch 18746 instructions because the distance of the branch targets is not known 18747 until assembly-time. The Xtensa assembler offers branch relaxation and 18748 also extends this concept to function calls, `MOVI' instructions and 18749 other instructions with immediate fields. 18750 18751 * Menu: 18752 18753 * Xtensa Branch Relaxation:: Relaxation of Branches. 18754 * Xtensa Call Relaxation:: Relaxation of Function Calls. 18755 * Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 18756 18757 18758 File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 18759 18760 9.42.4.1 Conditional Branch Relaxation 18761 ...................................... 18762 18763 When the target of a branch is too far away from the branch itself, 18764 i.e., when the offset from the branch to the target is too large to fit 18765 in the immediate field of the branch instruction, it may be necessary to 18766 replace the branch with a branch around a jump. For example, 18767 18768 beqz a2, L 18769 18770 may result in: 18771 18772 bnez.n a2, M 18773 j L 18774 M: 18775 18776 (The `BNEZ.N' instruction would be used in this example only if the 18777 density option is available. Otherwise, `BNEZ' would be used.) 18778 18779 This relaxation works well because the unconditional jump instruction 18780 has a much larger offset range than the various conditional branches. 18781 However, an error will occur if a branch target is beyond the range of a 18782 jump instruction. `as' cannot relax unconditional jumps. Similarly, 18783 an error will occur if the original input contains an unconditional 18784 jump to a target that is out of range. 18785 18786 Branch relaxation is enabled by default. It can be disabled by using 18787 underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 18788 `--no-transform' command-line option (*note Command Line Options: 18789 Xtensa Options.), or the `no-transform' directive (*note transform: 18790 Transform Directive.). 18791 18792 18793 File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 18794 18795 9.42.4.2 Function Call Relaxation 18796 ................................. 18797 18798 Function calls may require relaxation because the Xtensa immediate call 18799 instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a 18800 PC-relative offset of only 512 Kbytes in either direction. For larger 18801 programs, it may be necessary to use indirect calls (`CALLX0', 18802 `CALLX4', `CALLX8' and `CALLX12') where the target address is specified 18803 in a register. The Xtensa assembler can automatically relax immediate 18804 call instructions into indirect call instructions. This relaxation is 18805 done by loading the address of the called function into the callee's 18806 return address register and then using a `CALLX' instruction. So, for 18807 example: 18808 18809 call8 func 18810 18811 might be relaxed to: 18812 18813 .literal .L1, func 18814 l32r a8, .L1 18815 callx8 a8 18816 18817 Because the addresses of targets of function calls are not generally 18818 known until link-time, the assembler must assume the worst and relax all 18819 the calls to functions in other source files, not just those that really 18820 will be out of range. The linker can recognize calls that were 18821 unnecessarily relaxed, and it will remove the overhead introduced by the 18822 assembler for those cases where direct calls are sufficient. 18823 18824 Call relaxation is disabled by default because it can have a negative 18825 effect on both code size and performance, although the linker can 18826 usually eliminate the unnecessary overhead. If a program is too large 18827 and some of the calls are out of range, function call relaxation can be 18828 enabled using the `--longcalls' command-line option or the `longcalls' 18829 directive (*note longcalls: Longcalls Directive.). 18830 18831 18832 File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 18833 18834 9.42.4.3 Other Immediate Field Relaxation 18835 ......................................... 18836 18837 The assembler normally performs the following other relaxations. They 18838 can be disabled by using underscore prefixes (*note Opcode Names: 18839 Xtensa Opcodes.), the `--no-transform' command-line option (*note 18840 Command Line Options: Xtensa Options.), or the `no-transform' directive 18841 (*note transform: Transform Directive.). 18842 18843 The `MOVI' machine instruction can only materialize values in the 18844 range from -2048 to 2047. Values outside this range are best 18845 materialized with `L32R' instructions. Thus: 18846 18847 movi a0, 100000 18848 18849 is assembled into the following machine code: 18850 18851 .literal .L1, 100000 18852 l32r a0, .L1 18853 18854 The `L8UI' machine instruction can only be used with immediate 18855 offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine 18856 instructions can only be used with offsets from 0 to 510. The `L32I' 18857 machine instruction can only be used with offsets from 0 to 1020. A 18858 load offset outside these ranges can be materialized with an `L32R' 18859 instruction if the destination register of the load is different than 18860 the source address register. For example: 18861 18862 l32i a1, a0, 2040 18863 18864 is translated to: 18865 18866 .literal .L1, 2040 18867 l32r a1, .L1 18868 add a1, a0, a1 18869 l32i a1, a1, 0 18870 18871 If the load destination and source address register are the same, an 18872 out-of-range offset causes an error. 18873 18874 The Xtensa `ADDI' instruction only allows immediate operands in the 18875 range from -128 to 127. There are a number of alternate instruction 18876 sequences for the `ADDI' operation. First, if the immediate is 0, the 18877 `ADDI' will be turned into a `MOV.N' instruction (or the equivalent 18878 `OR' instruction if the code density option is not available). If the 18879 `ADDI' immediate is outside of the range -128 to 127, but inside the 18880 range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI' 18881 sequence will be used. Finally, if the immediate is outside of this 18882 range and a free register is available, an `L32R'/`ADD' sequence will 18883 be used with a literal allocated from the literal pool. 18884 18885 For example: 18886 18887 addi a5, a6, 0 18888 addi a5, a6, 512 18889 addi a5, a6, 513 18890 addi a5, a6, 50000 18891 18892 is assembled into the following: 18893 18894 .literal .L1, 50000 18895 mov.n a5, a6 18896 addmi a5, a6, 0x200 18897 addmi a5, a6, 0x200 18898 addi a5, a5, 1 18899 l32r a5, .L1 18900 add a5, a6, a5 18901 18902 18903 File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 18904 18905 9.42.5 Directives 18906 ----------------- 18907 18908 The Xtensa assembler supports a region-based directive syntax: 18909 18910 .begin DIRECTIVE [OPTIONS] 18911 ... 18912 .end DIRECTIVE 18913 18914 All the Xtensa-specific directives that apply to a region of code use 18915 this syntax. 18916 18917 The directive applies to code between the `.begin' and the `.end'. 18918 The state of the option after the `.end' reverts to what it was before 18919 the `.begin'. A nested `.begin'/`.end' region can further change the 18920 state of the directive without having to be aware of its outer state. 18921 For example, consider: 18922 18923 .begin no-transform 18924 L: add a0, a1, a2 18925 .begin transform 18926 M: add a0, a1, a2 18927 .end transform 18928 N: add a0, a1, a2 18929 .end no-transform 18930 18931 The `ADD' opcodes at `L' and `N' in the outer `no-transform' region 18932 both result in `ADD' machine instructions, but the assembler selects an 18933 `ADD.N' instruction for the `ADD' at `M' in the inner `transform' 18934 region. 18935 18936 The advantage of this style is that it works well inside macros 18937 which can preserve the context of their callers. 18938 18939 The following directives are available: 18940 18941 * Menu: 18942 18943 * Schedule Directive:: Enable instruction scheduling. 18944 * Longcalls Directive:: Use Indirect Calls for Greater Range. 18945 * Transform Directive:: Disable All Assembler Transformations. 18946 * Literal Directive:: Intermix Literals with Instructions. 18947 * Literal Position Directive:: Specify Inline Literal Pool Locations. 18948 * Literal Prefix Directive:: Specify Literal Section Name Prefix. 18949 * Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 18950 18951 18952 File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 18953 18954 9.42.5.1 schedule 18955 ................. 18956 18957 The `schedule' directive is recognized only for compatibility with 18958 Tensilica's assembler. 18959 18960 .begin [no-]schedule 18961 .end [no-]schedule 18962 18963 This directive is ignored and has no effect on `as'. 18964 18965 18966 File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 18967 18968 9.42.5.2 longcalls 18969 .................. 18970 18971 The `longcalls' directive enables or disables function call relaxation. 18972 *Note Function Call Relaxation: Xtensa Call Relaxation. 18973 18974 .begin [no-]longcalls 18975 .end [no-]longcalls 18976 18977 Call relaxation is disabled by default unless the `--longcalls' 18978 command-line option is specified. The `longcalls' directive overrides 18979 the default determined by the command-line options. 18980 18981 18982 File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 18983 18984 9.42.5.3 transform 18985 .................. 18986 18987 This directive enables or disables all assembler transformation, 18988 including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 18989 optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 18990 18991 .begin [no-]transform 18992 .end [no-]transform 18993 18994 Transformations are enabled by default unless the `--no-transform' 18995 option is used. The `transform' directive overrides the default 18996 determined by the command-line options. An underscore opcode prefix, 18997 disabling transformation of that opcode, always takes precedence over 18998 both directives and command-line flags. 18999 19000 19001 File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 19002 19003 9.42.5.4 literal 19004 ................ 19005 19006 The `.literal' directive is used to define literal pool data, i.e., 19007 read-only 32-bit data accessed via `L32R' instructions. 19008 19009 .literal LABEL, VALUE[, VALUE...] 19010 19011 This directive is similar to the standard `.word' directive, except 19012 that the actual location of the literal data is determined by the 19013 assembler and linker, not by the position of the `.literal' directive. 19014 Using this directive gives the assembler freedom to locate the literal 19015 data in the most appropriate place and possibly to combine identical 19016 literals. For example, the code: 19017 19018 entry sp, 40 19019 .literal .L1, sym 19020 l32r a4, .L1 19021 19022 can be used to load a pointer to the symbol `sym' into register 19023 `a4'. The value of `sym' will not be placed between the `ENTRY' and 19024 `L32R' instructions; instead, the assembler puts the data in a literal 19025 pool. 19026 19027 Literal pools are placed by default in separate literal sections; 19028 however, when using the `--text-section-literals' option (*note Command 19029 Line Options: Xtensa Options.), the literal pools for PC-relative mode 19030 `L32R' instructions are placed in the current section.(1) These text 19031 section literal pools are created automatically before `ENTRY' 19032 instructions and manually after `.literal_position' directives (*note 19033 literal_position: Literal Position Directive.). If there are no 19034 preceding `ENTRY' instructions, explicit `.literal_position' directives 19035 must be used to place the text section literal pools; otherwise, `as' 19036 will report an error. 19037 19038 When literals are placed in separate sections, the literal section 19039 names are derived from the names of the sections where the literals are 19040 defined. The base literal section names are `.literal' for PC-relative 19041 mode `L32R' instructions and `.lit4' for absolute mode `L32R' 19042 instructions (*note absolute-literals: Absolute Literals Directive.). 19043 These base names are used for literals defined in the default `.text' 19044 section. For literals defined in other sections or within the scope of 19045 a `literal_prefix' directive (*note literal_prefix: Literal Prefix 19046 Directive.), the following rules determine the literal section name: 19047 19048 1. If the current section is a member of a section group, the literal 19049 section name includes the group name as a suffix to the base 19050 `.literal' or `.lit4' name, with a period to separate the base 19051 name and group name. The literal section is also made a member of 19052 the group. 19053 19054 2. If the current section name (or `literal_prefix' value) begins with 19055 "`.gnu.linkonce.KIND.'", the literal section name is formed by 19056 replacing "`.KIND'" with the base `.literal' or `.lit4' name. For 19057 example, for literals defined in a section named 19058 `.gnu.linkonce.t.func', the literal section will be 19059 `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'. 19060 19061 3. If the current section name (or `literal_prefix' value) ends with 19062 `.text', the literal section name is formed by replacing that 19063 suffix with the base `.literal' or `.lit4' name. For example, for 19064 literals defined in a section named `.iram0.text', the literal 19065 section will be `.iram0.literal' or `.iram0.lit4'. 19066 19067 4. If none of the preceding conditions apply, the literal section 19068 name is formed by adding the base `.literal' or `.lit4' name as a 19069 suffix to the current section name (or `literal_prefix' value). 19070 19071 ---------- Footnotes ---------- 19072 19073 (1) Literals for the `.init' and `.fini' sections are always placed 19074 in separate sections, even when `--text-section-literals' is enabled. 19075 19076 19077 File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 19078 19079 9.42.5.5 literal_position 19080 ......................... 19081 19082 When using `--text-section-literals' to place literals inline in the 19083 section being assembled, the `.literal_position' directive can be used 19084 to mark a potential location for a literal pool. 19085 19086 .literal_position 19087 19088 The `.literal_position' directive is ignored when the 19089 `--text-section-literals' option is not used or when `L32R' 19090 instructions use the absolute addressing mode. 19091 19092 The assembler will automatically place text section literal pools 19093 before `ENTRY' instructions, so the `.literal_position' directive is 19094 only needed to specify some other location for a literal pool. You may 19095 need to add an explicit jump instruction to skip over an inline literal 19096 pool. 19097 19098 For example, an interrupt vector does not begin with an `ENTRY' 19099 instruction so the assembler will be unable to automatically find a good 19100 place to put a literal pool. Moreover, the code for the interrupt 19101 vector must be at a specific starting address, so the literal pool 19102 cannot come before the start of the code. The literal pool for the 19103 vector must be explicitly positioned in the middle of the vector (before 19104 any uses of the literals, due to the negative offsets used by 19105 PC-relative `L32R' instructions). The `.literal_position' directive 19106 can be used to do this. In the following code, the literal for `M' 19107 will automatically be aligned correctly and is placed after the 19108 unconditional jump. 19109 19110 .global M 19111 code_start: 19112 j continue 19113 .literal_position 19114 .align 4 19115 continue: 19116 movi a4, M 19117 19118 19119 File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 19120 19121 9.42.5.6 literal_prefix 19122 ....................... 19123 19124 The `literal_prefix' directive allows you to override the default 19125 literal section names, which are derived from the names of the sections 19126 where the literals are defined. 19127 19128 .begin literal_prefix [NAME] 19129 .end literal_prefix 19130 19131 For literals defined within the delimited region, the literal section 19132 names are derived from the NAME argument instead of the name of the 19133 current section. The rules used to derive the literal section names do 19134 not change. *Note literal: Literal Directive. If the NAME argument is 19135 omitted, the literal sections revert to the defaults. This directive 19136 has no effect when using the `--text-section-literals' option (*note 19137 Command Line Options: Xtensa Options.). 19138 19139 19140 File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 19141 19142 9.42.5.7 absolute-literals 19143 .......................... 19144 19145 The `absolute-literals' and `no-absolute-literals' directives control 19146 the absolute vs. PC-relative mode for `L32R' instructions. These are 19147 relevant only for Xtensa configurations that include the absolute 19148 addressing option for `L32R' instructions. 19149 19150 .begin [no-]absolute-literals 19151 .end [no-]absolute-literals 19152 19153 These directives do not change the `L32R' mode--they only cause the 19154 assembler to emit the appropriate kind of relocation for `L32R' 19155 instructions and to place the literal values in the appropriate section. 19156 To change the `L32R' mode, the program must write the `LITBASE' special 19157 register. It is the programmer's responsibility to keep track of the 19158 mode and indicate to the assembler which mode is used in each region of 19159 code. 19160 19161 If the Xtensa configuration includes the absolute `L32R' addressing 19162 option, the default is to assume absolute `L32R' addressing unless the 19163 `--no-absolute-literals' command-line option is specified. Otherwise, 19164 the default is to assume PC-relative `L32R' addressing. The 19165 `absolute-literals' directive can then be used to override the default 19166 determined by the command-line options. 19167 19168 19169 File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 19170 19171 10 Reporting Bugs 19172 ***************** 19173 19174 Your bug reports play an essential role in making `as' reliable. 19175 19176 Reporting a bug may help you by bringing a solution to your problem, 19177 or it may not. But in any case the principal function of a bug report 19178 is to help the entire community by making the next version of `as' work 19179 better. Bug reports are your contribution to the maintenance of `as'. 19180 19181 In order for a bug report to serve its purpose, you must include the 19182 information that enables us to fix the bug. 19183 19184 * Menu: 19185 19186 * Bug Criteria:: Have you found a bug? 19187 * Bug Reporting:: How to report bugs 19188 19189 19190 File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 19191 19192 10.1 Have You Found a Bug? 19193 ========================== 19194 19195 If you are not sure whether you have found a bug, here are some 19196 guidelines: 19197 19198 * If the assembler gets a fatal signal, for any input whatever, that 19199 is a `as' bug. Reliable assemblers never crash. 19200 19201 * If `as' produces an error message for valid input, that is a bug. 19202 19203 * If `as' does not produce an error message for invalid input, that 19204 is a bug. However, you should note that your idea of "invalid 19205 input" might be our idea of "an extension" or "support for 19206 traditional practice". 19207 19208 * If you are an experienced user of assemblers, your suggestions for 19209 improvement of `as' are welcome in any case. 19210 19211 19212 File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 19213 19214 10.2 How to Report Bugs 19215 ======================= 19216 19217 A number of companies and individuals offer support for GNU products. 19218 If you obtained `as' from a support organization, we recommend you 19219 contact that organization first. 19220 19221 You can find contact information for many support companies and 19222 individuals in the file `etc/SERVICE' in the GNU Emacs distribution. 19223 19224 In any event, we also recommend that you send bug reports for `as' 19225 to `http://www.sourceware.org/bugzilla/'. 19226 19227 The fundamental principle of reporting bugs usefully is this: 19228 *report all the facts*. If you are not sure whether to state a fact or 19229 leave it out, state it! 19230 19231 Often people omit facts because they think they know what causes the 19232 problem and assume that some details do not matter. Thus, you might 19233 assume that the name of a symbol you use in an example does not matter. 19234 Well, probably it does not, but one cannot be sure. Perhaps the bug is 19235 a stray memory reference which happens to fetch from the location where 19236 that name is stored in memory; perhaps, if the name were different, the 19237 contents of that location would fool the assembler into doing the right 19238 thing despite the bug. Play it safe and give a specific, complete 19239 example. That is the easiest thing for you to do, and the most helpful. 19240 19241 Keep in mind that the purpose of a bug report is to enable us to fix 19242 the bug if it is new to us. Therefore, always write your bug reports 19243 on the assumption that the bug has not been reported previously. 19244 19245 Sometimes people give a few sketchy facts and ask, "Does this ring a 19246 bell?" This cannot help us fix a bug, so it is basically useless. We 19247 respond by asking for enough details to enable us to investigate. You 19248 might as well expedite matters by sending them to begin with. 19249 19250 To enable us to fix the bug, you should include all these things: 19251 19252 * The version of `as'. `as' announces it if you start it with the 19253 `--version' argument. 19254 19255 Without this, we will not know whether there is any point in 19256 looking for the bug in the current version of `as'. 19257 19258 * Any patches you may have applied to the `as' source. 19259 19260 * The type of machine you are using, and the operating system name 19261 and version number. 19262 19263 * What compiler (and its version) was used to compile `as'--e.g. 19264 "`gcc-2.7'". 19265 19266 * The command arguments you gave the assembler to assemble your 19267 example and observe the bug. To guarantee you will not omit 19268 something important, list them all. A copy of the Makefile (or 19269 the output from make) is sufficient. 19270 19271 If we were to try to guess the arguments, we would probably guess 19272 wrong and then we might not encounter the bug. 19273 19274 * A complete input file that will reproduce the bug. If the bug is 19275 observed when the assembler is invoked via a compiler, send the 19276 assembler source, not the high level language source. Most 19277 compilers will produce the assembler source when run with the `-S' 19278 option. If you are using `gcc', use the options `-v 19279 --save-temps'; this will save the assembler source in a file with 19280 an extension of `.s', and also show you exactly how `as' is being 19281 run. 19282 19283 * A description of what behavior you observe that you believe is 19284 incorrect. For example, "It gets a fatal signal." 19285 19286 Of course, if the bug is that `as' gets a fatal signal, then we 19287 will certainly notice it. But if the bug is incorrect output, we 19288 might not notice unless it is glaringly wrong. You might as well 19289 not give us a chance to make a mistake. 19290 19291 Even if the problem you experience is a fatal signal, you should 19292 still say so explicitly. Suppose something strange is going on, 19293 such as, your copy of `as' is out of sync, or you have encountered 19294 a bug in the C library on your system. (This has happened!) Your 19295 copy might crash and ours would not. If you told us to expect a 19296 crash, then when ours fails to crash, we would know that the bug 19297 was not happening for us. If you had not told us to expect a 19298 crash, then we would not be able to draw any conclusion from our 19299 observations. 19300 19301 * If you wish to suggest changes to the `as' source, send us context 19302 diffs, as generated by `diff' with the `-u', `-c', or `-p' option. 19303 Always send diffs from the old file to the new file. If you even 19304 discuss something in the `as' source, refer to it by context, not 19305 by line number. 19306 19307 The line numbers in our development sources will not match those 19308 in your sources. Your line numbers would convey no useful 19309 information to us. 19310 19311 Here are some things that are not necessary: 19312 19313 * A description of the envelope of the bug. 19314 19315 Often people who encounter a bug spend a lot of time investigating 19316 which changes to the input file will make the bug go away and which 19317 changes will not affect it. 19318 19319 This is often time consuming and not very useful, because the way 19320 we will find the bug is by running a single example under the 19321 debugger with breakpoints, not by pure deduction from a series of 19322 examples. We recommend that you save your time for something else. 19323 19324 Of course, if you can find a simpler example to report _instead_ 19325 of the original one, that is a convenience for us. Errors in the 19326 output will be easier to spot, running under the debugger will take 19327 less time, and so on. 19328 19329 However, simplification is not vital; if you do not want to do 19330 this, report the bug anyway and send us the entire test case you 19331 used. 19332 19333 * A patch for the bug. 19334 19335 A patch for the bug does help us if it is a good one. But do not 19336 omit the necessary information, such as the test case, on the 19337 assumption that a patch is all we need. We might see problems 19338 with your patch and decide to fix the problem another way, or we 19339 might not understand it at all. 19340 19341 Sometimes with a program as complicated as `as' it is very hard to 19342 construct an example that will make the program follow a certain 19343 path through the code. If you do not send us the example, we will 19344 not be able to construct one, so we will not be able to verify 19345 that the bug is fixed. 19346 19347 And if we cannot understand what bug you are trying to fix, or why 19348 your patch should be an improvement, we will not install it. A 19349 test case will help us to understand. 19350 19351 * A guess about what the bug is or what it depends on. 19352 19353 Such guesses are usually wrong. Even we cannot guess right about 19354 such things without first using the debugger to find the facts. 19355 19356 19357 File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 19358 19359 11 Acknowledgements 19360 ******************* 19361 19362 If you have contributed to GAS and your name isn't listed here, it is 19363 not meant as a slight. We just don't know about it. Send mail to the 19364 maintainer, and we'll correct the situation. Currently the maintainer 19365 is Ken Raeburn (email address `raeburn (a] cygnus.com'). 19366 19367 Dean Elsner wrote the original GNU assembler for the VAX.(1) 19368 19369 Jay Fenlason maintained GAS for a while, adding support for 19370 GDB-specific debug information and the 68k series machines, most of the 19371 preprocessing pass, and extensive changes in `messages.c', 19372 `input-file.c', `write.c'. 19373 19374 K. Richard Pixley maintained GAS for a while, adding various 19375 enhancements and many bug fixes, including merging support for several 19376 processors, breaking GAS up to handle multiple object file format back 19377 ends (including heavy rewrite, testing, an integration of the coff and 19378 b.out back ends), adding configuration including heavy testing and 19379 verification of cross assemblers and file splits and renaming, 19380 converted GAS to strictly ANSI C including full prototypes, added 19381 support for m680[34]0 and cpu32, did considerable work on i960 19382 including a COFF port (including considerable amounts of reverse 19383 engineering), a SPARC opcode file rewrite, DECstation, rs6000, and 19384 hp300hpux host ports, updated "know" assertions and made them work, 19385 much other reorganization, cleanup, and lint. 19386 19387 Ken Raeburn wrote the high-level BFD interface code to replace most 19388 of the code in format-specific I/O modules. 19389 19390 The original VMS support was contributed by David L. Kashtan. Eric 19391 Youngdale has done much work with it since. 19392 19393 The Intel 80386 machine description was written by Eliot Dresselhaus. 19394 19395 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 19396 19397 The Motorola 88k machine description was contributed by Devon Bowen 19398 of Buffalo University and Torbjorn Granlund of the Swedish Institute of 19399 Computer Science. 19400 19401 Keith Knowles at the Open Software Foundation wrote the original 19402 MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format 19403 support (which hasn't been merged in yet). Ralph Campbell worked with 19404 the MIPS code to support a.out format. 19405 19406 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 19407 tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 19408 Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 19409 end to use BFD for some low-level operations, for use with the H8/300 19410 and AMD 29k targets. 19411 19412 John Gilmore built the AMD 29000 support, added `.include' support, 19413 and simplified the configuration of which versions accept which 19414 directives. He updated the 68k machine description so that Motorola's 19415 opcodes always produced fixed-size instructions (e.g., `jsr'), while 19416 synthetic instructions remained shrinkable (`jbsr'). John fixed many 19417 bugs, including true tested cross-compilation support, and one bug in 19418 relaxation that took a week and required the proverbial one-bit fix. 19419 19420 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT 19421 syntax for the 68k, completed support for some COFF targets (68k, i386 19422 SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, 19423 wrote the initial RS/6000 and PowerPC assembler, and made a few other 19424 minor patches. 19425 19426 Steve Chamberlain made GAS able to generate listings. 19427 19428 Hewlett-Packard contributed support for the HP9000/300. 19429 19430 Jeff Law wrote GAS and BFD support for the native HPPA object format 19431 (SOM) along with a fairly extensive HPPA testsuite (for both SOM and 19432 ELF object formats). This work was supported by both the Center for 19433 Software Science at the University of Utah and Cygnus Support. 19434 19435 Support for ELF format files has been worked on by Mark Eichin of 19436 Cygnus Support (original, incomplete implementation for SPARC), Pete 19437 Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), 19438 Michael Meissner of the Open Software Foundation (i386 mainly), and Ken 19439 Raeburn of Cygnus Support (sparc, and some initial 64-bit support). 19440 19441 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 19442 architecture. 19443 19444 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 19445 GAS and BFD support for openVMS/Alpha. 19446 19447 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 19448 various tic* flavors. 19449 19450 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 19451 Tensilica, Inc. added support for Xtensa processors. 19452 19453 Several engineers at Cygnus Support have also provided many small 19454 bug fixes and configuration enhancements. 19455 19456 Jon Beniston added support for the Lattice Mico32 architecture. 19457 19458 Many others have contributed large or small bugfixes and 19459 enhancements. If you have contributed significant work and are not 19460 mentioned on this list, and want to be, let us know. Some of the 19461 history has been lost; we are not intentionally leaving anyone out. 19462 19463 ---------- Footnotes ---------- 19464 19465 (1) Any more details? 19466 19467 19468 File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 19469 19470 Appendix A GNU Free Documentation License 19471 ***************************************** 19472 19473 Version 1.3, 3 November 2008 19474 19475 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 19476 `http://fsf.org/' 19477 19478 Everyone is permitted to copy and distribute verbatim copies 19479 of this license document, but changing it is not allowed. 19480 19481 0. PREAMBLE 19482 19483 The purpose of this License is to make a manual, textbook, or other 19484 functional and useful document "free" in the sense of freedom: to 19485 assure everyone the effective freedom to copy and redistribute it, 19486 with or without modifying it, either commercially or 19487 noncommercially. Secondarily, this License preserves for the 19488 author and publisher a way to get credit for their work, while not 19489 being considered responsible for modifications made by others. 19490 19491 This License is a kind of "copyleft", which means that derivative 19492 works of the document must themselves be free in the same sense. 19493 It complements the GNU General Public License, which is a copyleft 19494 license designed for free software. 19495 19496 We have designed this License in order to use it for manuals for 19497 free software, because free software needs free documentation: a 19498 free program should come with manuals providing the same freedoms 19499 that the software does. But this License is not limited to 19500 software manuals; it can be used for any textual work, regardless 19501 of subject matter or whether it is published as a printed book. 19502 We recommend this License principally for works whose purpose is 19503 instruction or reference. 19504 19505 1. APPLICABILITY AND DEFINITIONS 19506 19507 This License applies to any manual or other work, in any medium, 19508 that contains a notice placed by the copyright holder saying it 19509 can be distributed under the terms of this License. Such a notice 19510 grants a world-wide, royalty-free license, unlimited in duration, 19511 to use that work under the conditions stated herein. The 19512 "Document", below, refers to any such manual or work. Any member 19513 of the public is a licensee, and is addressed as "you". You 19514 accept the license if you copy, modify or distribute the work in a 19515 way requiring permission under copyright law. 19516 19517 A "Modified Version" of the Document means any work containing the 19518 Document or a portion of it, either copied verbatim, or with 19519 modifications and/or translated into another language. 19520 19521 A "Secondary Section" is a named appendix or a front-matter section 19522 of the Document that deals exclusively with the relationship of the 19523 publishers or authors of the Document to the Document's overall 19524 subject (or to related matters) and contains nothing that could 19525 fall directly within that overall subject. (Thus, if the Document 19526 is in part a textbook of mathematics, a Secondary Section may not 19527 explain any mathematics.) The relationship could be a matter of 19528 historical connection with the subject or with related matters, or 19529 of legal, commercial, philosophical, ethical or political position 19530 regarding them. 19531 19532 The "Invariant Sections" are certain Secondary Sections whose 19533 titles are designated, as being those of Invariant Sections, in 19534 the notice that says that the Document is released under this 19535 License. If a section does not fit the above definition of 19536 Secondary then it is not allowed to be designated as Invariant. 19537 The Document may contain zero Invariant Sections. If the Document 19538 does not identify any Invariant Sections then there are none. 19539 19540 The "Cover Texts" are certain short passages of text that are 19541 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 19542 that says that the Document is released under this License. A 19543 Front-Cover Text may be at most 5 words, and a Back-Cover Text may 19544 be at most 25 words. 19545 19546 A "Transparent" copy of the Document means a machine-readable copy, 19547 represented in a format whose specification is available to the 19548 general public, that is suitable for revising the document 19549 straightforwardly with generic text editors or (for images 19550 composed of pixels) generic paint programs or (for drawings) some 19551 widely available drawing editor, and that is suitable for input to 19552 text formatters or for automatic translation to a variety of 19553 formats suitable for input to text formatters. A copy made in an 19554 otherwise Transparent file format whose markup, or absence of 19555 markup, has been arranged to thwart or discourage subsequent 19556 modification by readers is not Transparent. An image format is 19557 not Transparent if used for any substantial amount of text. A 19558 copy that is not "Transparent" is called "Opaque". 19559 19560 Examples of suitable formats for Transparent copies include plain 19561 ASCII without markup, Texinfo input format, LaTeX input format, 19562 SGML or XML using a publicly available DTD, and 19563 standard-conforming simple HTML, PostScript or PDF designed for 19564 human modification. Examples of transparent image formats include 19565 PNG, XCF and JPG. Opaque formats include proprietary formats that 19566 can be read and edited only by proprietary word processors, SGML or 19567 XML for which the DTD and/or processing tools are not generally 19568 available, and the machine-generated HTML, PostScript or PDF 19569 produced by some word processors for output purposes only. 19570 19571 The "Title Page" means, for a printed book, the title page itself, 19572 plus such following pages as are needed to hold, legibly, the 19573 material this License requires to appear in the title page. For 19574 works in formats which do not have any title page as such, "Title 19575 Page" means the text near the most prominent appearance of the 19576 work's title, preceding the beginning of the body of the text. 19577 19578 The "publisher" means any person or entity that distributes copies 19579 of the Document to the public. 19580 19581 A section "Entitled XYZ" means a named subunit of the Document 19582 whose title either is precisely XYZ or contains XYZ in parentheses 19583 following text that translates XYZ in another language. (Here XYZ 19584 stands for a specific section name mentioned below, such as 19585 "Acknowledgements", "Dedications", "Endorsements", or "History".) 19586 To "Preserve the Title" of such a section when you modify the 19587 Document means that it remains a section "Entitled XYZ" according 19588 to this definition. 19589 19590 The Document may include Warranty Disclaimers next to the notice 19591 which states that this License applies to the Document. These 19592 Warranty Disclaimers are considered to be included by reference in 19593 this License, but only as regards disclaiming warranties: any other 19594 implication that these Warranty Disclaimers may have is void and 19595 has no effect on the meaning of this License. 19596 19597 2. VERBATIM COPYING 19598 19599 You may copy and distribute the Document in any medium, either 19600 commercially or noncommercially, provided that this License, the 19601 copyright notices, and the license notice saying this License 19602 applies to the Document are reproduced in all copies, and that you 19603 add no other conditions whatsoever to those of this License. You 19604 may not use technical measures to obstruct or control the reading 19605 or further copying of the copies you make or distribute. However, 19606 you may accept compensation in exchange for copies. If you 19607 distribute a large enough number of copies you must also follow 19608 the conditions in section 3. 19609 19610 You may also lend copies, under the same conditions stated above, 19611 and you may publicly display copies. 19612 19613 3. COPYING IN QUANTITY 19614 19615 If you publish printed copies (or copies in media that commonly 19616 have printed covers) of the Document, numbering more than 100, and 19617 the Document's license notice requires Cover Texts, you must 19618 enclose the copies in covers that carry, clearly and legibly, all 19619 these Cover Texts: Front-Cover Texts on the front cover, and 19620 Back-Cover Texts on the back cover. Both covers must also clearly 19621 and legibly identify you as the publisher of these copies. The 19622 front cover must present the full title with all words of the 19623 title equally prominent and visible. You may add other material 19624 on the covers in addition. Copying with changes limited to the 19625 covers, as long as they preserve the title of the Document and 19626 satisfy these conditions, can be treated as verbatim copying in 19627 other respects. 19628 19629 If the required texts for either cover are too voluminous to fit 19630 legibly, you should put the first ones listed (as many as fit 19631 reasonably) on the actual cover, and continue the rest onto 19632 adjacent pages. 19633 19634 If you publish or distribute Opaque copies of the Document 19635 numbering more than 100, you must either include a 19636 machine-readable Transparent copy along with each Opaque copy, or 19637 state in or with each Opaque copy a computer-network location from 19638 which the general network-using public has access to download 19639 using public-standard network protocols a complete Transparent 19640 copy of the Document, free of added material. If you use the 19641 latter option, you must take reasonably prudent steps, when you 19642 begin distribution of Opaque copies in quantity, to ensure that 19643 this Transparent copy will remain thus accessible at the stated 19644 location until at least one year after the last time you 19645 distribute an Opaque copy (directly or through your agents or 19646 retailers) of that edition to the public. 19647 19648 It is requested, but not required, that you contact the authors of 19649 the Document well before redistributing any large number of 19650 copies, to give them a chance to provide you with an updated 19651 version of the Document. 19652 19653 4. MODIFICATIONS 19654 19655 You may copy and distribute a Modified Version of the Document 19656 under the conditions of sections 2 and 3 above, provided that you 19657 release the Modified Version under precisely this License, with 19658 the Modified Version filling the role of the Document, thus 19659 licensing distribution and modification of the Modified Version to 19660 whoever possesses a copy of it. In addition, you must do these 19661 things in the Modified Version: 19662 19663 A. Use in the Title Page (and on the covers, if any) a title 19664 distinct from that of the Document, and from those of 19665 previous versions (which should, if there were any, be listed 19666 in the History section of the Document). You may use the 19667 same title as a previous version if the original publisher of 19668 that version gives permission. 19669 19670 B. List on the Title Page, as authors, one or more persons or 19671 entities responsible for authorship of the modifications in 19672 the Modified Version, together with at least five of the 19673 principal authors of the Document (all of its principal 19674 authors, if it has fewer than five), unless they release you 19675 from this requirement. 19676 19677 C. State on the Title page the name of the publisher of the 19678 Modified Version, as the publisher. 19679 19680 D. Preserve all the copyright notices of the Document. 19681 19682 E. Add an appropriate copyright notice for your modifications 19683 adjacent to the other copyright notices. 19684 19685 F. Include, immediately after the copyright notices, a license 19686 notice giving the public permission to use the Modified 19687 Version under the terms of this License, in the form shown in 19688 the Addendum below. 19689 19690 G. Preserve in that license notice the full lists of Invariant 19691 Sections and required Cover Texts given in the Document's 19692 license notice. 19693 19694 H. Include an unaltered copy of this License. 19695 19696 I. Preserve the section Entitled "History", Preserve its Title, 19697 and add to it an item stating at least the title, year, new 19698 authors, and publisher of the Modified Version as given on 19699 the Title Page. If there is no section Entitled "History" in 19700 the Document, create one stating the title, year, authors, 19701 and publisher of the Document as given on its Title Page, 19702 then add an item describing the Modified Version as stated in 19703 the previous sentence. 19704 19705 J. Preserve the network location, if any, given in the Document 19706 for public access to a Transparent copy of the Document, and 19707 likewise the network locations given in the Document for 19708 previous versions it was based on. These may be placed in 19709 the "History" section. You may omit a network location for a 19710 work that was published at least four years before the 19711 Document itself, or if the original publisher of the version 19712 it refers to gives permission. 19713 19714 K. For any section Entitled "Acknowledgements" or "Dedications", 19715 Preserve the Title of the section, and preserve in the 19716 section all the substance and tone of each of the contributor 19717 acknowledgements and/or dedications given therein. 19718 19719 L. Preserve all the Invariant Sections of the Document, 19720 unaltered in their text and in their titles. Section numbers 19721 or the equivalent are not considered part of the section 19722 titles. 19723 19724 M. Delete any section Entitled "Endorsements". Such a section 19725 may not be included in the Modified Version. 19726 19727 N. Do not retitle any existing section to be Entitled 19728 "Endorsements" or to conflict in title with any Invariant 19729 Section. 19730 19731 O. Preserve any Warranty Disclaimers. 19732 19733 If the Modified Version includes new front-matter sections or 19734 appendices that qualify as Secondary Sections and contain no 19735 material copied from the Document, you may at your option 19736 designate some or all of these sections as invariant. To do this, 19737 add their titles to the list of Invariant Sections in the Modified 19738 Version's license notice. These titles must be distinct from any 19739 other section titles. 19740 19741 You may add a section Entitled "Endorsements", provided it contains 19742 nothing but endorsements of your Modified Version by various 19743 parties--for example, statements of peer review or that the text 19744 has been approved by an organization as the authoritative 19745 definition of a standard. 19746 19747 You may add a passage of up to five words as a Front-Cover Text, 19748 and a passage of up to 25 words as a Back-Cover Text, to the end 19749 of the list of Cover Texts in the Modified Version. Only one 19750 passage of Front-Cover Text and one of Back-Cover Text may be 19751 added by (or through arrangements made by) any one entity. If the 19752 Document already includes a cover text for the same cover, 19753 previously added by you or by arrangement made by the same entity 19754 you are acting on behalf of, you may not add another; but you may 19755 replace the old one, on explicit permission from the previous 19756 publisher that added the old one. 19757 19758 The author(s) and publisher(s) of the Document do not by this 19759 License give permission to use their names for publicity for or to 19760 assert or imply endorsement of any Modified Version. 19761 19762 5. COMBINING DOCUMENTS 19763 19764 You may combine the Document with other documents released under 19765 this License, under the terms defined in section 4 above for 19766 modified versions, provided that you include in the combination 19767 all of the Invariant Sections of all of the original documents, 19768 unmodified, and list them all as Invariant Sections of your 19769 combined work in its license notice, and that you preserve all 19770 their Warranty Disclaimers. 19771 19772 The combined work need only contain one copy of this License, and 19773 multiple identical Invariant Sections may be replaced with a single 19774 copy. If there are multiple Invariant Sections with the same name 19775 but different contents, make the title of each such section unique 19776 by adding at the end of it, in parentheses, the name of the 19777 original author or publisher of that section if known, or else a 19778 unique number. Make the same adjustment to the section titles in 19779 the list of Invariant Sections in the license notice of the 19780 combined work. 19781 19782 In the combination, you must combine any sections Entitled 19783 "History" in the various original documents, forming one section 19784 Entitled "History"; likewise combine any sections Entitled 19785 "Acknowledgements", and any sections Entitled "Dedications". You 19786 must delete all sections Entitled "Endorsements." 19787 19788 6. COLLECTIONS OF DOCUMENTS 19789 19790 You may make a collection consisting of the Document and other 19791 documents released under this License, and replace the individual 19792 copies of this License in the various documents with a single copy 19793 that is included in the collection, provided that you follow the 19794 rules of this License for verbatim copying of each of the 19795 documents in all other respects. 19796 19797 You may extract a single document from such a collection, and 19798 distribute it individually under this License, provided you insert 19799 a copy of this License into the extracted document, and follow 19800 this License in all other respects regarding verbatim copying of 19801 that document. 19802 19803 7. AGGREGATION WITH INDEPENDENT WORKS 19804 19805 A compilation of the Document or its derivatives with other 19806 separate and independent documents or works, in or on a volume of 19807 a storage or distribution medium, is called an "aggregate" if the 19808 copyright resulting from the compilation is not used to limit the 19809 legal rights of the compilation's users beyond what the individual 19810 works permit. When the Document is included in an aggregate, this 19811 License does not apply to the other works in the aggregate which 19812 are not themselves derivative works of the Document. 19813 19814 If the Cover Text requirement of section 3 is applicable to these 19815 copies of the Document, then if the Document is less than one half 19816 of the entire aggregate, the Document's Cover Texts may be placed 19817 on covers that bracket the Document within the aggregate, or the 19818 electronic equivalent of covers if the Document is in electronic 19819 form. Otherwise they must appear on printed covers that bracket 19820 the whole aggregate. 19821 19822 8. TRANSLATION 19823 19824 Translation is considered a kind of modification, so you may 19825 distribute translations of the Document under the terms of section 19826 4. Replacing Invariant Sections with translations requires special 19827 permission from their copyright holders, but you may include 19828 translations of some or all Invariant Sections in addition to the 19829 original versions of these Invariant Sections. You may include a 19830 translation of this License, and all the license notices in the 19831 Document, and any Warranty Disclaimers, provided that you also 19832 include the original English version of this License and the 19833 original versions of those notices and disclaimers. In case of a 19834 disagreement between the translation and the original version of 19835 this License or a notice or disclaimer, the original version will 19836 prevail. 19837 19838 If a section in the Document is Entitled "Acknowledgements", 19839 "Dedications", or "History", the requirement (section 4) to 19840 Preserve its Title (section 1) will typically require changing the 19841 actual title. 19842 19843 9. TERMINATION 19844 19845 You may not copy, modify, sublicense, or distribute the Document 19846 except as expressly provided under this License. Any attempt 19847 otherwise to copy, modify, sublicense, or distribute it is void, 19848 and will automatically terminate your rights under this License. 19849 19850 However, if you cease all violation of this License, then your 19851 license from a particular copyright holder is reinstated (a) 19852 provisionally, unless and until the copyright holder explicitly 19853 and finally terminates your license, and (b) permanently, if the 19854 copyright holder fails to notify you of the violation by some 19855 reasonable means prior to 60 days after the cessation. 19856 19857 Moreover, your license from a particular copyright holder is 19858 reinstated permanently if the copyright holder notifies you of the 19859 violation by some reasonable means, this is the first time you have 19860 received notice of violation of this License (for any work) from 19861 that copyright holder, and you cure the violation prior to 30 days 19862 after your receipt of the notice. 19863 19864 Termination of your rights under this section does not terminate 19865 the licenses of parties who have received copies or rights from 19866 you under this License. If your rights have been terminated and 19867 not permanently reinstated, receipt of a copy of some or all of 19868 the same material does not give you any rights to use it. 19869 19870 10. FUTURE REVISIONS OF THIS LICENSE 19871 19872 The Free Software Foundation may publish new, revised versions of 19873 the GNU Free Documentation License from time to time. Such new 19874 versions will be similar in spirit to the present version, but may 19875 differ in detail to address new problems or concerns. See 19876 `http://www.gnu.org/copyleft/'. 19877 19878 Each version of the License is given a distinguishing version 19879 number. If the Document specifies that a particular numbered 19880 version of this License "or any later version" applies to it, you 19881 have the option of following the terms and conditions either of 19882 that specified version or of any later version that has been 19883 published (not as a draft) by the Free Software Foundation. If 19884 the Document does not specify a version number of this License, 19885 you may choose any version ever published (not as a draft) by the 19886 Free Software Foundation. If the Document specifies that a proxy 19887 can decide which future versions of this License can be used, that 19888 proxy's public statement of acceptance of a version permanently 19889 authorizes you to choose that version for the Document. 19890 19891 11. RELICENSING 19892 19893 "Massive Multiauthor Collaboration Site" (or "MMC Site") means any 19894 World Wide Web server that publishes copyrightable works and also 19895 provides prominent facilities for anybody to edit those works. A 19896 public wiki that anybody can edit is an example of such a server. 19897 A "Massive Multiauthor Collaboration" (or "MMC") contained in the 19898 site means any set of copyrightable works thus published on the MMC 19899 site. 19900 19901 "CC-BY-SA" means the Creative Commons Attribution-Share Alike 3.0 19902 license published by Creative Commons Corporation, a not-for-profit 19903 corporation with a principal place of business in San Francisco, 19904 California, as well as future copyleft versions of that license 19905 published by that same organization. 19906 19907 "Incorporate" means to publish or republish a Document, in whole or 19908 in part, as part of another Document. 19909 19910 An MMC is "eligible for relicensing" if it is licensed under this 19911 License, and if all works that were first published under this 19912 License somewhere other than this MMC, and subsequently 19913 incorporated in whole or in part into the MMC, (1) had no cover 19914 texts or invariant sections, and (2) were thus incorporated prior 19915 to November 1, 2008. 19916 19917 The operator of an MMC Site may republish an MMC contained in the 19918 site under CC-BY-SA on the same site at any time before August 1, 19919 2009, provided the MMC is eligible for relicensing. 19920 19921 19922 ADDENDUM: How to use this License for your documents 19923 ==================================================== 19924 19925 To use this License in a document you have written, include a copy of 19926 the License in the document and put the following copyright and license 19927 notices just after the title page: 19928 19929 Copyright (C) YEAR YOUR NAME. 19930 Permission is granted to copy, distribute and/or modify this document 19931 under the terms of the GNU Free Documentation License, Version 1.3 19932 or any later version published by the Free Software Foundation; 19933 with no Invariant Sections, no Front-Cover Texts, and no Back-Cover 19934 Texts. A copy of the license is included in the section entitled ``GNU 19935 Free Documentation License''. 19936 19937 If you have Invariant Sections, Front-Cover Texts and Back-Cover 19938 Texts, replace the "with...Texts." line with this: 19939 19940 with the Invariant Sections being LIST THEIR TITLES, with 19941 the Front-Cover Texts being LIST, and with the Back-Cover Texts 19942 being LIST. 19943 19944 If you have Invariant Sections without Cover Texts, or some other 19945 combination of the three, merge those two alternatives to suit the 19946 situation. 19947 19948 If your document contains nontrivial examples of program code, we 19949 recommend releasing these examples in parallel under your choice of 19950 free software license, such as the GNU General Public License, to 19951 permit their use in free software. 19952 19953 19954 File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 19955 19956 AS Index 19957 ******** 19958 19959 [index] 19960 * Menu: 19961 19962 * #: Comments. (line 39) 19963 * #APP: Preprocessing. (line 26) 19964 * #NO_APP: Preprocessing. (line 26) 19965 * $ in symbol names <1>: D10V-Chars. (line 46) 19966 * $ in symbol names <2>: SH64-Chars. (line 10) 19967 * $ in symbol names <3>: D30V-Chars. (line 63) 19968 * $ in symbol names: SH-Chars. (line 10) 19969 * $a: ARM Mapping Symbols. (line 9) 19970 * $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 19971 * $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 19972 * $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 19973 * $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 19974 * $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 19975 * $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 19976 * $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 19977 * $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 19978 * $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 19979 * $d: ARM Mapping Symbols. (line 15) 19980 * $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 19981 * $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 19982 * $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 19983 * $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 19984 * $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 19985 * $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 19986 * $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 19987 * $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 19988 * $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 19989 * $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 19990 * $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 19991 * $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 19992 * $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 19993 * $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 19994 * $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 19995 * $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 19996 * $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 19997 * $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 19998 * $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 19999 * $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 20000 * $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 20001 * $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 20002 * $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 20003 * $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 20004 * $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 20005 * $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 20006 * $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 20007 * $t: ARM Mapping Symbols. (line 12) 20008 * $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 20009 * $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 20010 * $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 20011 * -+ option, VAX/VMS: VAX-Opts. (line 71) 20012 * --: Command Line. (line 10) 20013 * --32 option, i386: i386-Options. (line 8) 20014 * --32 option, x86-64: i386-Options. (line 8) 20015 * --64 option, i386: i386-Options. (line 8) 20016 * --64 option, x86-64: i386-Options. (line 8) 20017 * --absolute-literals: Xtensa Options. (line 23) 20018 * --allow-reg-prefix: SH Options. (line 9) 20019 * --alternate: alternate. (line 6) 20020 * --base-size-default-16: M68K-Opts. (line 65) 20021 * --base-size-default-32: M68K-Opts. (line 65) 20022 * --big: SH Options. (line 9) 20023 * --bitwise-or option, M680x0: M68K-Opts. (line 58) 20024 * --disp-size-default-16: M68K-Opts. (line 74) 20025 * --disp-size-default-32: M68K-Opts. (line 74) 20026 * --divide option, i386: i386-Options. (line 24) 20027 * --dsp: SH Options. (line 9) 20028 * --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9) 20029 * --emulation=criself command line option, CRIS: CRIS-Opts. (line 9) 20030 * --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 20031 * --fatal-warnings: W. (line 16) 20032 * --fdpic: SH Options. (line 31) 20033 * --fix-v4bx command line option, ARM: ARM Options. (line 165) 20034 * --fixed-special-register-names command line option, MMIX: MMIX-Opts. 20035 (line 8) 20036 * --force-long-branches: M68HC11-Opts. (line 69) 20037 * --generate-example: M68HC11-Opts. (line 86) 20038 * --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12) 20039 * --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16) 20040 * --hash-size=NUMBER: Overview. (line 354) 20041 * --linker-allocated-gregs command line option, MMIX: MMIX-Opts. 20042 (line 67) 20043 * --listing-cont-lines: listing. (line 34) 20044 * --listing-lhs-width: listing. (line 16) 20045 * --listing-lhs-width2: listing. (line 21) 20046 * --listing-rhs-width: listing. (line 28) 20047 * --little: SH Options. (line 9) 20048 * --longcalls: Xtensa Options. (line 37) 20049 * --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 33) 20050 * --MD: MD. (line 6) 20051 * --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 61) 20052 * --no-absolute-literals: Xtensa Options. (line 23) 20053 * --no-expand command line option, MMIX: MMIX-Opts. (line 31) 20054 * --no-longcalls: Xtensa Options. (line 37) 20055 * --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36) 20056 * --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 61) 20057 * --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22) 20058 * --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54) 20059 * --no-stubs command line option, MMIX: MMIX-Opts. (line 54) 20060 * --no-target-align: Xtensa Options. (line 30) 20061 * --no-text-section-literals: Xtensa Options. (line 9) 20062 * --no-transform: Xtensa Options. (line 46) 20063 * --no-underscore command line option, CRIS: CRIS-Opts. (line 15) 20064 * --no-warn: W. (line 11) 20065 * --pcrel: M68K-Opts. (line 86) 20066 * --pic command line option, CRIS: CRIS-Opts. (line 27) 20067 * --print-insn-syntax: M68HC11-Opts. (line 75) 20068 * --print-opcodes: M68HC11-Opts. (line 79) 20069 * --register-prefix-optional option, M680x0: M68K-Opts. (line 45) 20070 * --relax: SH Options. (line 9) 20071 * --relax command line option, MMIX: MMIX-Opts. (line 19) 20072 * --rename-section: Xtensa Options. (line 54) 20073 * --renesas: SH Options. (line 9) 20074 * --short-branches: M68HC11-Opts. (line 54) 20075 * --small: SH Options. (line 9) 20076 * --statistics: statistics. (line 6) 20077 * --strict-direct-mode: M68HC11-Opts. (line 44) 20078 * --target-align: Xtensa Options. (line 30) 20079 * --text-section-literals: Xtensa Options. (line 9) 20080 * --traditional-format: traditional-format. (line 6) 20081 * --transform: Xtensa Options. (line 46) 20082 * --underscore command line option, CRIS: CRIS-Opts. (line 15) 20083 * --warn: W. (line 19) 20084 * -1 option, VAX/VMS: VAX-Opts. (line 77) 20085 * -32addr command line option, Alpha: Alpha Options. (line 57) 20086 * -a: a. (line 6) 20087 * -A options, i960: Options-i960. (line 6) 20088 * -ac: a. (line 6) 20089 * -ad: a. (line 6) 20090 * -ag: a. (line 6) 20091 * -ah: a. (line 6) 20092 * -al: a. (line 6) 20093 * -an: a. (line 6) 20094 * -as: a. (line 6) 20095 * -Asparclet: Sparc-Opts. (line 25) 20096 * -Asparclite: Sparc-Opts. (line 25) 20097 * -Av6: Sparc-Opts. (line 25) 20098 * -Av8: Sparc-Opts. (line 25) 20099 * -Av9: Sparc-Opts. (line 25) 20100 * -Av9a: Sparc-Opts. (line 25) 20101 * -b option, i960: Options-i960. (line 22) 20102 * -big option, M32R: M32R-Opts. (line 35) 20103 * -D: D. (line 6) 20104 * -D, ignored on VAX: VAX-Opts. (line 11) 20105 * -d, VAX option: VAX-Opts. (line 16) 20106 * -eabi= command line option, ARM: ARM Options. (line 148) 20107 * -EB command line option, ARC: ARC Options. (line 31) 20108 * -EB command line option, ARM: ARM Options. (line 153) 20109 * -EB option (MIPS): MIPS Opts. (line 13) 20110 * -EB option, M32R: M32R-Opts. (line 39) 20111 * -EL command line option, ARC: ARC Options. (line 35) 20112 * -EL command line option, ARM: ARM Options. (line 157) 20113 * -EL option (MIPS): MIPS Opts. (line 13) 20114 * -EL option, M32R: M32R-Opts. (line 32) 20115 * -f: f. (line 6) 20116 * -F command line option, Alpha: Alpha Options. (line 57) 20117 * -g command line option, Alpha: Alpha Options. (line 47) 20118 * -G command line option, Alpha: Alpha Options. (line 53) 20119 * -G option (MIPS): MIPS Opts. (line 8) 20120 * -h option, VAX/VMS: VAX-Opts. (line 45) 20121 * -H option, VAX/VMS: VAX-Opts. (line 81) 20122 * -I PATH: I. (line 6) 20123 * -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 20124 * -Ip option, M32RX: M32R-Opts. (line 97) 20125 * -J, ignored on VAX: VAX-Opts. (line 27) 20126 * -K: K. (line 6) 20127 * -k command line option, ARM: ARM Options. (line 161) 20128 * -KPIC option, M32R: M32R-Opts. (line 42) 20129 * -KPIC option, MIPS: MIPS Opts. (line 21) 20130 * -L: L. (line 6) 20131 * -l option, M680x0: M68K-Opts. (line 33) 20132 * -little option, M32R: M32R-Opts. (line 27) 20133 * -M: M. (line 6) 20134 * -m11/03: PDP-11-Options. (line 140) 20135 * -m11/04: PDP-11-Options. (line 143) 20136 * -m11/05: PDP-11-Options. (line 146) 20137 * -m11/10: PDP-11-Options. (line 146) 20138 * -m11/15: PDP-11-Options. (line 149) 20139 * -m11/20: PDP-11-Options. (line 149) 20140 * -m11/21: PDP-11-Options. (line 152) 20141 * -m11/23: PDP-11-Options. (line 155) 20142 * -m11/24: PDP-11-Options. (line 155) 20143 * -m11/34: PDP-11-Options. (line 158) 20144 * -m11/34a: PDP-11-Options. (line 161) 20145 * -m11/35: PDP-11-Options. (line 164) 20146 * -m11/40: PDP-11-Options. (line 164) 20147 * -m11/44: PDP-11-Options. (line 167) 20148 * -m11/45: PDP-11-Options. (line 170) 20149 * -m11/50: PDP-11-Options. (line 170) 20150 * -m11/53: PDP-11-Options. (line 173) 20151 * -m11/55: PDP-11-Options. (line 170) 20152 * -m11/60: PDP-11-Options. (line 176) 20153 * -m11/70: PDP-11-Options. (line 170) 20154 * -m11/73: PDP-11-Options. (line 173) 20155 * -m11/83: PDP-11-Options. (line 173) 20156 * -m11/84: PDP-11-Options. (line 173) 20157 * -m11/93: PDP-11-Options. (line 173) 20158 * -m11/94: PDP-11-Options. (line 173) 20159 * -m16c option, M16C: M32C-Opts. (line 12) 20160 * -m31 option, s390: s390 Options. (line 8) 20161 * -m32bit-doubles: RX-Opts. (line 9) 20162 * -m32c option, M32C: M32C-Opts. (line 9) 20163 * -m32r option, M32R: M32R-Opts. (line 21) 20164 * -m32rx option, M32R2: M32R-Opts. (line 17) 20165 * -m32rx option, M32RX: M32R-Opts. (line 9) 20166 * -m64 option, s390: s390 Options. (line 8) 20167 * -m64bit-doubles: RX-Opts. (line 15) 20168 * -m68000 and related options: M68K-Opts. (line 98) 20169 * -m68hc11: M68HC11-Opts. (line 9) 20170 * -m68hc12: M68HC11-Opts. (line 14) 20171 * -m68hcs12: M68HC11-Opts. (line 21) 20172 * -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21) 20173 * -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21) 20174 * -m[no-]div command line option, M680x0: M68K-Opts. (line 21) 20175 * -m[no-]emac command line option, M680x0: M68K-Opts. (line 21) 20176 * -m[no-]float command line option, M680x0: M68K-Opts. (line 21) 20177 * -m[no-]mac command line option, M680x0: M68K-Opts. (line 21) 20178 * -m[no-]usp command line option, M680x0: M68K-Opts. (line 21) 20179 * -mall: PDP-11-Options. (line 26) 20180 * -mall-enabled command line option, LM32: LM32 Options. (line 30) 20181 * -mall-extensions: PDP-11-Options. (line 26) 20182 * -mall-opcodes command line option, AVR: AVR Options. (line 68) 20183 * -mapcs-26 command line option, ARM: ARM Options. (line 120) 20184 * -mapcs-32 command line option, ARM: ARM Options. (line 120) 20185 * -mapcs-float command line option, ARM: ARM Options. (line 134) 20186 * -mapcs-reentrant command line option, ARM: ARM Options. (line 139) 20187 * -marc[5|6|7|8] command line option, ARC: ARC Options. (line 6) 20188 * -march= command line option, ARM: ARM Options. (line 59) 20189 * -march= command line option, M680x0: M68K-Opts. (line 8) 20190 * -march= command line option, TIC6X: TIC6X Options. (line 6) 20191 * -march= option, i386: i386-Options. (line 31) 20192 * -march= option, s390: s390 Options. (line 25) 20193 * -march= option, x86-64: i386-Options. (line 31) 20194 * -matomic command line option, TIC6X: TIC6X Options. (line 13) 20195 * -matpcs command line option, ARM: ARM Options. (line 126) 20196 * -mavxscalar= option, i386: i386-Options. (line 79) 20197 * -mavxscalar= option, x86-64: i386-Options. (line 79) 20198 * -mbarrel-shift-enabled command line option, LM32: LM32 Options. 20199 (line 12) 20200 * -mbig-endian: RX-Opts. (line 20) 20201 * -mbreak-enabled command line option, LM32: LM32 Options. (line 27) 20202 * -mcis: PDP-11-Options. (line 32) 20203 * -mconstant-gp command line option, IA-64: IA-64 Options. (line 6) 20204 * -mCPU command line option, Alpha: Alpha Options. (line 6) 20205 * -mcpu option, cpu: TIC54X-Opts. (line 15) 20206 * -mcpu= command line option, ARM: ARM Options. (line 6) 20207 * -mcpu= command line option, Blackfin: Blackfin Options. (line 6) 20208 * -mcpu= command line option, M680x0: M68K-Opts. (line 14) 20209 * -mcsm: PDP-11-Options. (line 43) 20210 * -mdcache-enabled command line option, LM32: LM32 Options. (line 24) 20211 * -mdebug command line option, Alpha: Alpha Options. (line 25) 20212 * -mdivide-enabled command line option, LM32: LM32 Options. (line 9) 20213 * -mdsbt command line option, TIC6X: TIC6X Options. (line 25) 20214 * -me option, stderr redirect: TIC54X-Opts. (line 20) 20215 * -meis: PDP-11-Options. (line 46) 20216 * -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 20217 * -mesa option, s390: s390 Options. (line 17) 20218 * -mf option, far-mode: TIC54X-Opts. (line 8) 20219 * -mf11: PDP-11-Options. (line 122) 20220 * -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 20221 * -mfdpic command line option, Blackfin: Blackfin Options. (line 19) 20222 * -mfis: PDP-11-Options. (line 51) 20223 * -mfloat-abi= command line option, ARM: ARM Options. (line 143) 20224 * -mfp-11: PDP-11-Options. (line 56) 20225 * -mfpp: PDP-11-Options. (line 56) 20226 * -mfpu: PDP-11-Options. (line 56) 20227 * -mfpu= command line option, ARM: ARM Options. (line 74) 20228 * -micache-enabled command line option, LM32: LM32 Options. (line 21) 20229 * -mimplicit-it command line option, ARM: ARM Options. (line 104) 20230 * -mip2022 option, IP2K: IP2K-Opts. (line 14) 20231 * -mip2022ext option, IP2022: IP2K-Opts. (line 9) 20232 * -mj11: PDP-11-Options. (line 126) 20233 * -mka11: PDP-11-Options. (line 92) 20234 * -mkb11: PDP-11-Options. (line 95) 20235 * -mkd11a: PDP-11-Options. (line 98) 20236 * -mkd11b: PDP-11-Options. (line 101) 20237 * -mkd11d: PDP-11-Options. (line 104) 20238 * -mkd11e: PDP-11-Options. (line 107) 20239 * -mkd11f: PDP-11-Options. (line 110) 20240 * -mkd11h: PDP-11-Options. (line 110) 20241 * -mkd11k: PDP-11-Options. (line 114) 20242 * -mkd11q: PDP-11-Options. (line 110) 20243 * -mkd11z: PDP-11-Options. (line 118) 20244 * -mkev11: PDP-11-Options. (line 51) 20245 * -mlimited-eis: PDP-11-Options. (line 64) 20246 * -mlittle-endian: RX-Opts. (line 26) 20247 * -mlong: M68HC11-Opts. (line 32) 20248 * -mlong-double: M68HC11-Opts. (line 40) 20249 * -mmcu= command line option, AVR: AVR Options. (line 6) 20250 * -mmfpt: PDP-11-Options. (line 70) 20251 * -mmicrocode: PDP-11-Options. (line 83) 20252 * -mmnemonic= option, i386: i386-Options. (line 87) 20253 * -mmnemonic= option, x86-64: i386-Options. (line 87) 20254 * -mmultiply-enabled command line option, LM32: LM32 Options. (line 6) 20255 * -mmutiproc: PDP-11-Options. (line 73) 20256 * -mmxps: PDP-11-Options. (line 77) 20257 * -mnaked-reg option, i386: i386-Options. (line 99) 20258 * -mnaked-reg option, x86-64: i386-Options. (line 99) 20259 * -mno-atomic command line option, TIC6X: TIC6X Options. (line 13) 20260 * -mno-cis: PDP-11-Options. (line 32) 20261 * -mno-csm: PDP-11-Options. (line 43) 20262 * -mno-dsbt command line option, TIC6X: TIC6X Options. (line 25) 20263 * -mno-eis: PDP-11-Options. (line 46) 20264 * -mno-extensions: PDP-11-Options. (line 29) 20265 * -mno-fdpic command line option, Blackfin: Blackfin Options. (line 22) 20266 * -mno-fis: PDP-11-Options. (line 51) 20267 * -mno-fp-11: PDP-11-Options. (line 56) 20268 * -mno-fpp: PDP-11-Options. (line 56) 20269 * -mno-fpu: PDP-11-Options. (line 56) 20270 * -mno-kev11: PDP-11-Options. (line 51) 20271 * -mno-limited-eis: PDP-11-Options. (line 64) 20272 * -mno-mfpt: PDP-11-Options. (line 70) 20273 * -mno-microcode: PDP-11-Options. (line 83) 20274 * -mno-mutiproc: PDP-11-Options. (line 73) 20275 * -mno-mxps: PDP-11-Options. (line 77) 20276 * -mno-pic: PDP-11-Options. (line 11) 20277 * -mno-pic command line option, TIC6X: TIC6X Options. (line 48) 20278 * -mno-regnames option, s390: s390 Options. (line 35) 20279 * -mno-skip-bug command line option, AVR: AVR Options. (line 71) 20280 * -mno-spl: PDP-11-Options. (line 80) 20281 * -mno-sym32: MIPS Opts. (line 208) 20282 * -mno-wrap command line option, AVR: AVR Options. (line 74) 20283 * -mnopic command line option, Blackfin: Blackfin Options. (line 22) 20284 * -mpic: PDP-11-Options. (line 11) 20285 * -mpic command line option, TIC6X: TIC6X Options. (line 48) 20286 * -mpid= command line option, TIC6X: TIC6X Options. (line 35) 20287 * -mregnames option, s390: s390 Options. (line 32) 20288 * -mrelax command line option, V850: V850 Options. (line 63) 20289 * -mshort: M68HC11-Opts. (line 27) 20290 * -mshort-double: M68HC11-Opts. (line 36) 20291 * -msign-extend-enabled command line option, LM32: LM32 Options. 20292 (line 15) 20293 * -msmall-data-limit: RX-Opts. (line 42) 20294 * -mspl: PDP-11-Options. (line 80) 20295 * -msse-check= option, i386: i386-Options. (line 69) 20296 * -msse-check= option, x86-64: i386-Options. (line 69) 20297 * -msse2avx option, i386: i386-Options. (line 65) 20298 * -msse2avx option, x86-64: i386-Options. (line 65) 20299 * -msym32: MIPS Opts. (line 208) 20300 * -msyntax= option, i386: i386-Options. (line 93) 20301 * -msyntax= option, x86-64: i386-Options. (line 93) 20302 * -mt11: PDP-11-Options. (line 130) 20303 * -mthumb command line option, ARM: ARM Options. (line 95) 20304 * -mthumb-interwork command line option, ARM: ARM Options. (line 100) 20305 * -mtune= option, i386: i386-Options. (line 57) 20306 * -mtune= option, x86-64: i386-Options. (line 57) 20307 * -muse-conventional-section-names: RX-Opts. (line 33) 20308 * -muse-renesas-section-names: RX-Opts. (line 37) 20309 * -muser-enabled command line option, LM32: LM32 Options. (line 18) 20310 * -mv850 command line option, V850: V850 Options. (line 23) 20311 * -mv850any command line option, V850: V850 Options. (line 41) 20312 * -mv850e command line option, V850: V850 Options. (line 29) 20313 * -mv850e1 command line option, V850: V850 Options. (line 35) 20314 * -mv850e2 command line option, V850: V850 Options. (line 51) 20315 * -mv850e2v3 command line option, V850: V850 Options. (line 57) 20316 * -mvxworks-pic option, MIPS: MIPS Opts. (line 26) 20317 * -mwarn-areg-zero option, s390: s390 Options. (line 38) 20318 * -mwarn-deprecated command line option, ARM: ARM Options. (line 169) 20319 * -mzarch option, s390: s390 Options. (line 17) 20320 * -N command line option, CRIS: CRIS-Opts. (line 57) 20321 * -nIp option, M32RX: M32R-Opts. (line 101) 20322 * -no-bitinst, M32R2: M32R-Opts. (line 54) 20323 * -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 20324 * -no-mdebug command line option, Alpha: Alpha Options. (line 25) 20325 * -no-parallel option, M32RX: M32R-Opts. (line 51) 20326 * -no-relax option, i960: Options-i960. (line 66) 20327 * -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 20328 (line 79) 20329 * -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 20330 * -nocpp ignored (MIPS): MIPS Opts. (line 211) 20331 * -noreplace command line option, Alpha: Alpha Options. (line 40) 20332 * -o: o. (line 6) 20333 * -O option, M32RX: M32R-Opts. (line 59) 20334 * -parallel option, M32RX: M32R-Opts. (line 46) 20335 * -R: R. (line 6) 20336 * -r800 command line option, Z80: Z80 Options. (line 41) 20337 * -relax command line option, Alpha: Alpha Options. (line 32) 20338 * -replace command line option, Alpha: Alpha Options. (line 40) 20339 * -S, ignored on VAX: VAX-Opts. (line 11) 20340 * -T, ignored on VAX: VAX-Opts. (line 11) 20341 * -t, ignored on VAX: VAX-Opts. (line 36) 20342 * -v: v. (line 6) 20343 * -V, redundant on VAX: VAX-Opts. (line 22) 20344 * -version: v. (line 6) 20345 * -W: W. (line 11) 20346 * -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line 65) 20347 * -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 20348 * -Wnp option, M32RX: M32R-Opts. (line 83) 20349 * -Wnuh option, M32RX: M32R-Opts. (line 117) 20350 * -Wp option, M32RX: M32R-Opts. (line 75) 20351 * -wsigned_overflow command line option, V850: V850 Options. (line 9) 20352 * -Wuh option, M32RX: M32R-Opts. (line 114) 20353 * -wunsigned_overflow command line option, V850: V850 Options. 20354 (line 16) 20355 * -x command line option, MMIX: MMIX-Opts. (line 44) 20356 * -z80 command line option, Z80: Z80 Options. (line 8) 20357 * -z8001 command line option, Z8000: Z8000 Options. (line 6) 20358 * -z8002 command line option, Z8000: Z8000 Options. (line 9) 20359 * . (symbol): Dot. (line 6) 20360 * .2byte directive, ARM: ARM Directives. (line 6) 20361 * .4byte directive, ARM: ARM Directives. (line 6) 20362 * .8byte directive, ARM: ARM Directives. (line 6) 20363 * .align directive, ARM: ARM Directives. (line 11) 20364 * .arch directive, ARM: ARM Directives. (line 18) 20365 * .arch directive, TIC6X: TIC6X Directives. (line 10) 20366 * .arch_extension directive, ARM: ARM Directives. (line 25) 20367 * .arm directive, ARM: ARM Directives. (line 34) 20368 * .atomic directive, TIC6X: TIC6X Directives. (line 13) 20369 * .big directive, M32RX: M32R-Directives. (line 88) 20370 * .bss directive, ARM: ARM Directives. (line 42) 20371 * .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 17) 20372 * .cantunwind directive, ARM: ARM Directives. (line 45) 20373 * .code directive, ARM: ARM Directives. (line 49) 20374 * .cpu directive, ARM: ARM Directives. (line 53) 20375 * .dn and .qn directives, ARM: ARM Directives. (line 60) 20376 * .eabi_attribute directive, ARM: ARM Directives. (line 83) 20377 * .even directive, ARM: ARM Directives. (line 111) 20378 * .extend directive, ARM: ARM Directives. (line 114) 20379 * .fnend directive, ARM: ARM Directives. (line 120) 20380 * .fnstart directive, ARM: ARM Directives. (line 129) 20381 * .force_thumb directive, ARM: ARM Directives. (line 132) 20382 * .fpu directive, ARM: ARM Directives. (line 136) 20383 * .global: MIPS insn. (line 12) 20384 * .handlerdata directive, ARM: ARM Directives. (line 140) 20385 * .insn: MIPS insn. (line 6) 20386 * .insn directive, s390: s390 Directives. (line 11) 20387 * .inst directive, ARM: ARM Directives. (line 149) 20388 * .ldouble directive, ARM: ARM Directives. (line 114) 20389 * .little directive, M32RX: M32R-Directives. (line 82) 20390 * .long directive, s390: s390 Directives. (line 16) 20391 * .ltorg directive, ARM: ARM Directives. (line 159) 20392 * .ltorg directive, s390: s390 Directives. (line 88) 20393 * .m32r directive, M32R: M32R-Directives. (line 66) 20394 * .m32r2 directive, M32R2: M32R-Directives. (line 77) 20395 * .m32rx directive, M32RX: M32R-Directives. (line 72) 20396 * .movsp directive, ARM: ARM Directives. (line 173) 20397 * .noatomic directive, TIC6X: TIC6X Directives. (line 13) 20398 * .nocmp directive, TIC6X: TIC6X Directives. (line 28) 20399 * .o: Object. (line 6) 20400 * .object_arch directive, ARM: ARM Directives. (line 178) 20401 * .packed directive, ARM: ARM Directives. (line 184) 20402 * .pad directive, ARM: ARM Directives. (line 189) 20403 * .param on HPPA: HPPA Directives. (line 19) 20404 * .personality directive, ARM: ARM Directives. (line 194) 20405 * .personalityindex directive, ARM: ARM Directives. (line 197) 20406 * .pool directive, ARM: ARM Directives. (line 201) 20407 * .quad directive, s390: s390 Directives. (line 16) 20408 * .req directive, ARM: ARM Directives. (line 204) 20409 * .save directive, ARM: ARM Directives. (line 209) 20410 * .secrel32 directive, ARM: ARM Directives. (line 247) 20411 * .set arch=CPU: MIPS ISA. (line 18) 20412 * .set autoextend: MIPS autoextend. (line 6) 20413 * .set doublefloat: MIPS floating-point. (line 12) 20414 * .set dsp: MIPS ASE instruction generation overrides. 20415 (line 21) 20416 * .set dspr2: MIPS ASE instruction generation overrides. 20417 (line 26) 20418 * .set hardfloat: MIPS floating-point. (line 6) 20419 * .set mdmx: MIPS ASE instruction generation overrides. 20420 (line 16) 20421 * .set mips3d: MIPS ASE instruction generation overrides. 20422 (line 6) 20423 * .set mipsN: MIPS ISA. (line 6) 20424 * .set mt: MIPS ASE instruction generation overrides. 20425 (line 32) 20426 * .set noautoextend: MIPS autoextend. (line 6) 20427 * .set nodsp: MIPS ASE instruction generation overrides. 20428 (line 21) 20429 * .set nodspr2: MIPS ASE instruction generation overrides. 20430 (line 26) 20431 * .set nomdmx: MIPS ASE instruction generation overrides. 20432 (line 16) 20433 * .set nomips3d: MIPS ASE instruction generation overrides. 20434 (line 6) 20435 * .set nomt: MIPS ASE instruction generation overrides. 20436 (line 32) 20437 * .set nosmartmips: MIPS ASE instruction generation overrides. 20438 (line 11) 20439 * .set nosym32: MIPS symbol sizes. (line 6) 20440 * .set pop: MIPS option stack. (line 6) 20441 * .set push: MIPS option stack. (line 6) 20442 * .set singlefloat: MIPS floating-point. (line 12) 20443 * .set smartmips: MIPS ASE instruction generation overrides. 20444 (line 11) 20445 * .set softfloat: MIPS floating-point. (line 6) 20446 * .set sym32: MIPS symbol sizes. (line 6) 20447 * .setfp directive, ARM: ARM Directives. (line 233) 20448 * .short directive, s390: s390 Directives. (line 16) 20449 * .syntax directive, ARM: ARM Directives. (line 252) 20450 * .thumb directive, ARM: ARM Directives. (line 256) 20451 * .thumb_func directive, ARM: ARM Directives. (line 259) 20452 * .thumb_set directive, ARM: ARM Directives. (line 270) 20453 * .unreq directive, ARM: ARM Directives. (line 277) 20454 * .unwind_raw directive, ARM: ARM Directives. (line 288) 20455 * .v850 directive, V850: V850 Directives. (line 14) 20456 * .v850e directive, V850: V850 Directives. (line 20) 20457 * .v850e1 directive, V850: V850 Directives. (line 26) 20458 * .v850e2 directive, V850: V850 Directives. (line 32) 20459 * .v850e2v3 directive, V850: V850 Directives. (line 38) 20460 * .vsave directive, ARM: ARM Directives. (line 295) 20461 * .z8001: Z8000 Directives. (line 11) 20462 * .z8002: Z8000 Directives. (line 15) 20463 * 16-bit code, i386: i386-16bit. (line 6) 20464 * 2byte directive, ARC: ARC Directives. (line 9) 20465 * 3byte directive, ARC: ARC Directives. (line 12) 20466 * 3DNow!, i386: i386-SIMD. (line 6) 20467 * 3DNow!, x86-64: i386-SIMD. (line 6) 20468 * 430 support: MSP430-Dependent. (line 6) 20469 * 4byte directive, ARC: ARC Directives. (line 15) 20470 * : (label): Statements. (line 30) 20471 * @word modifier, D10V: D10V-Word. (line 6) 20472 * \" (doublequote character): Strings. (line 43) 20473 * \\ (\ character): Strings. (line 40) 20474 * \b (backspace character): Strings. (line 15) 20475 * \DDD (octal character code): Strings. (line 30) 20476 * \f (formfeed character): Strings. (line 18) 20477 * \n (newline character): Strings. (line 21) 20478 * \r (carriage return character): Strings. (line 24) 20479 * \t (tab): Strings. (line 27) 20480 * \XD... (hex character code): Strings. (line 36) 20481 * _ opcode prefix: Xtensa Opcodes. (line 9) 20482 * a.out: Object. (line 6) 20483 * a.out symbol attributes: a.out Symbols. (line 6) 20484 * A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 20485 * ABI options, SH64: SH64 Options. (line 29) 20486 * abort directive: Abort. (line 6) 20487 * ABORT directive: ABORT (COFF). (line 6) 20488 * absolute section: Ld Sections. (line 29) 20489 * absolute-literals directive: Absolute Literals Directive. 20490 (line 6) 20491 * ADDI instructions, relaxation: Xtensa Immediate Relaxation. 20492 (line 43) 20493 * addition, permitted arguments: Infix Ops. (line 44) 20494 * addresses: Expressions. (line 6) 20495 * addresses, format of: Secs Background. (line 68) 20496 * addressing modes, D10V: D10V-Addressing. (line 6) 20497 * addressing modes, D30V: D30V-Addressing. (line 6) 20498 * addressing modes, H8/300: H8/300-Addressing. (line 6) 20499 * addressing modes, M680x0: M68K-Syntax. (line 21) 20500 * addressing modes, M68HC11: M68HC11-Syntax. (line 17) 20501 * addressing modes, SH: SH-Addressing. (line 6) 20502 * addressing modes, SH64: SH64-Addressing. (line 6) 20503 * addressing modes, Z8000: Z8000-Addressing. (line 6) 20504 * ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 20505 * ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35) 20506 * advancing location counter: Org. (line 6) 20507 * align directive: Align. (line 6) 20508 * align directive, SPARC: Sparc-Directives. (line 9) 20509 * align directive, TIC54X: TIC54X-Directives. (line 6) 20510 * alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 20511 * alignment of branch targets: Xtensa Automatic Alignment. 20512 (line 6) 20513 * alignment of LOOP instructions: Xtensa Automatic Alignment. 20514 (line 6) 20515 * Alpha floating point (IEEE): Alpha Floating Point. 20516 (line 6) 20517 * Alpha line comment character: Alpha-Chars. (line 6) 20518 * Alpha line separator: Alpha-Chars. (line 8) 20519 * Alpha notes: Alpha Notes. (line 6) 20520 * Alpha options: Alpha Options. (line 6) 20521 * Alpha registers: Alpha-Regs. (line 6) 20522 * Alpha relocations: Alpha-Relocs. (line 6) 20523 * Alpha support: Alpha-Dependent. (line 6) 20524 * Alpha Syntax: Alpha Options. (line 61) 20525 * Alpha-only directives: Alpha Directives. (line 10) 20526 * altered difference tables: Word. (line 12) 20527 * alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 20528 * ARC floating point (IEEE): ARC Floating Point. (line 6) 20529 * ARC machine directives: ARC Directives. (line 6) 20530 * ARC opcodes: ARC Opcodes. (line 6) 20531 * ARC options (none): ARC Options. (line 6) 20532 * ARC register names: ARC-Regs. (line 6) 20533 * ARC special characters: ARC-Chars. (line 6) 20534 * ARC support: ARC-Dependent. (line 6) 20535 * arc5 arc5, ARC: ARC Options. (line 10) 20536 * arc6 arc6, ARC: ARC Options. (line 13) 20537 * arc7 arc7, ARC: ARC Options. (line 21) 20538 * arc8 arc8, ARC: ARC Options. (line 24) 20539 * arch directive, i386: i386-Arch. (line 6) 20540 * arch directive, M680x0: M68K-Directives. (line 22) 20541 * arch directive, x86-64: i386-Arch. (line 6) 20542 * architecture options, i960: Options-i960. (line 6) 20543 * architecture options, IP2022: IP2K-Opts. (line 9) 20544 * architecture options, IP2K: IP2K-Opts. (line 14) 20545 * architecture options, M16C: M32C-Opts. (line 12) 20546 * architecture options, M32C: M32C-Opts. (line 9) 20547 * architecture options, M32R: M32R-Opts. (line 21) 20548 * architecture options, M32R2: M32R-Opts. (line 17) 20549 * architecture options, M32RX: M32R-Opts. (line 9) 20550 * architecture options, M680x0: M68K-Opts. (line 98) 20551 * Architecture variant option, CRIS: CRIS-Opts. (line 33) 20552 * architectures, PowerPC: PowerPC-Opts. (line 6) 20553 * architectures, SCORE: SCORE-Opts. (line 6) 20554 * architectures, SPARC: Sparc-Opts. (line 6) 20555 * arguments for addition: Infix Ops. (line 44) 20556 * arguments for subtraction: Infix Ops. (line 49) 20557 * arguments in expressions: Arguments. (line 6) 20558 * arithmetic functions: Operators. (line 6) 20559 * arithmetic operands: Arguments. (line 6) 20560 * ARM data relocations: ARM-Relocations. (line 6) 20561 * ARM floating point (IEEE): ARM Floating Point. (line 6) 20562 * ARM identifiers: ARM-Chars. (line 15) 20563 * ARM immediate character: ARM-Chars. (line 13) 20564 * ARM line comment character: ARM-Chars. (line 6) 20565 * ARM line separator: ARM-Chars. (line 10) 20566 * ARM machine directives: ARM Directives. (line 6) 20567 * ARM opcodes: ARM Opcodes. (line 6) 20568 * ARM options (none): ARM Options. (line 6) 20569 * ARM register names: ARM-Regs. (line 6) 20570 * ARM support: ARM-Dependent. (line 6) 20571 * ascii directive: Ascii. (line 6) 20572 * asciz directive: Asciz. (line 6) 20573 * asg directive, TIC54X: TIC54X-Directives. (line 20) 20574 * assembler bugs, reporting: Bug Reporting. (line 6) 20575 * assembler crash: Bug Criteria. (line 9) 20576 * assembler directive .3byte, RX: RX-Directives. (line 9) 20577 * assembler directive .arch, CRIS: CRIS-Pseudos. (line 45) 20578 * assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 20579 * assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 20580 * assembler directive .interrupt, M68HC11: M68HC11-Directives. 20581 (line 26) 20582 * assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 20583 * assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 20584 * assembler directive .syntax, CRIS: CRIS-Pseudos. (line 17) 20585 * assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 20586 * assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 131) 20587 * assembler directive BYTE, MMIX: MMIX-Pseudos. (line 97) 20588 * assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 131) 20589 * assembler directive GREG, MMIX: MMIX-Pseudos. (line 50) 20590 * assembler directive IS, MMIX: MMIX-Pseudos. (line 42) 20591 * assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 20592 * assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 28) 20593 * assembler directive OCTA, MMIX: MMIX-Pseudos. (line 108) 20594 * assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 120) 20595 * assembler directive TETRA, MMIX: MMIX-Pseudos. (line 108) 20596 * assembler directive WYDE, MMIX: MMIX-Pseudos. (line 108) 20597 * assembler directives, CRIS: CRIS-Pseudos. (line 6) 20598 * assembler directives, M68HC11: M68HC11-Directives. (line 6) 20599 * assembler directives, M68HC12: M68HC11-Directives. (line 6) 20600 * assembler directives, MMIX: MMIX-Pseudos. (line 6) 20601 * assembler directives, RX: RX-Directives. (line 6) 20602 * assembler internal logic error: As Sections. (line 13) 20603 * assembler version: v. (line 6) 20604 * assembler, and linker: Secs Background. (line 10) 20605 * assembly listings, enabling: a. (line 6) 20606 * assigning values to symbols <1>: Equ. (line 6) 20607 * assigning values to symbols: Setting Symbols. (line 6) 20608 * atmp directive, i860: Directives-i860. (line 16) 20609 * att_syntax pseudo op, i386: i386-Syntax. (line 6) 20610 * att_syntax pseudo op, x86-64: i386-Syntax. (line 6) 20611 * attributes, symbol: Symbol Attributes. (line 6) 20612 * auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 20613 * auxiliary symbol information, COFF: Dim. (line 6) 20614 * Av7: Sparc-Opts. (line 25) 20615 * AVR line comment character: AVR-Chars. (line 6) 20616 * AVR line separator: AVR-Chars. (line 10) 20617 * AVR modifiers: AVR-Modifiers. (line 6) 20618 * AVR opcode summary: AVR Opcodes. (line 6) 20619 * AVR options (none): AVR Options. (line 6) 20620 * AVR register names: AVR-Regs. (line 6) 20621 * AVR support: AVR-Dependent. (line 6) 20622 * backslash (\\): Strings. (line 40) 20623 * backspace (\b): Strings. (line 15) 20624 * balign directive: Balign. (line 6) 20625 * balignl directive: Balign. (line 27) 20626 * balignw directive: Balign. (line 27) 20627 * bes directive, TIC54X: TIC54X-Directives. (line 196) 20628 * big endian output, MIPS: Overview. (line 683) 20629 * big endian output, PJ: Overview. (line 590) 20630 * big-endian output, MIPS: MIPS Opts. (line 13) 20631 * big-endian output, TIC6X: TIC6X Options. (line 58) 20632 * bignums: Bignums. (line 6) 20633 * binary constants, TIC54X: TIC54X-Constants. (line 8) 20634 * binary files, including: Incbin. (line 6) 20635 * binary integers: Integers. (line 6) 20636 * bit names, IA-64: IA-64-Bits. (line 6) 20637 * bitfields, not supported on VAX: VAX-no. (line 6) 20638 * Blackfin directives: Blackfin Directives. (line 6) 20639 * Blackfin options (none): Blackfin Options. (line 6) 20640 * Blackfin support: Blackfin-Dependent. (line 6) 20641 * Blackfin syntax: Blackfin Syntax. (line 6) 20642 * block: Z8000 Directives. (line 55) 20643 * branch improvement, M680x0: M68K-Branch. (line 6) 20644 * branch improvement, M68HC11: M68HC11-Branch. (line 6) 20645 * branch improvement, VAX: VAX-branch. (line 6) 20646 * branch instructions, relaxation: Xtensa Branch Relaxation. 20647 (line 6) 20648 * branch recording, i960: Options-i960. (line 22) 20649 * branch statistics table, i960: Options-i960. (line 40) 20650 * branch target alignment: Xtensa Automatic Alignment. 20651 (line 6) 20652 * break directive, TIC54X: TIC54X-Directives. (line 143) 20653 * BSD syntax: PDP-11-Syntax. (line 6) 20654 * bss directive, i960: Directives-i960. (line 6) 20655 * bss directive, TIC54X: TIC54X-Directives. (line 29) 20656 * bss section <1>: Ld Sections. (line 20) 20657 * bss section: bss. (line 6) 20658 * bug criteria: Bug Criteria. (line 6) 20659 * bug reports: Bug Reporting. (line 6) 20660 * bugs in assembler: Reporting Bugs. (line 6) 20661 * Built-in symbols, CRIS: CRIS-Symbols. (line 6) 20662 * builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 20663 * builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 20664 * bus lock prefixes, i386: i386-Prefixes. (line 36) 20665 * bval: Z8000 Directives. (line 30) 20666 * byte directive: Byte. (line 6) 20667 * byte directive, TIC54X: TIC54X-Directives. (line 36) 20668 * C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 20669 * c_mode directive, TIC54X: TIC54X-Directives. (line 51) 20670 * call instructions, i386: i386-Mnemonics. (line 56) 20671 * call instructions, relaxation: Xtensa Call Relaxation. 20672 (line 6) 20673 * call instructions, x86-64: i386-Mnemonics. (line 56) 20674 * callj, i960 pseudo-opcode: callj-i960. (line 6) 20675 * carriage return (\r): Strings. (line 24) 20676 * case sensitivity, Z80: Z80-Case. (line 6) 20677 * cfi_endproc directive: CFI directives. (line 26) 20678 * cfi_sections directive: CFI directives. (line 6) 20679 * cfi_startproc directive: CFI directives. (line 16) 20680 * char directive, TIC54X: TIC54X-Directives. (line 36) 20681 * character constant, Z80: Z80-Chars. (line 13) 20682 * character constants: Characters. (line 6) 20683 * character escape codes: Strings. (line 15) 20684 * character escapes, Z80: Z80-Chars. (line 11) 20685 * character, single: Chars. (line 6) 20686 * characters used in symbols: Symbol Intro. (line 6) 20687 * clink directive, TIC54X: TIC54X-Directives. (line 45) 20688 * code16 directive, i386: i386-16bit. (line 6) 20689 * code16gcc directive, i386: i386-16bit. (line 6) 20690 * code32 directive, i386: i386-16bit. (line 6) 20691 * code64 directive, i386: i386-16bit. (line 6) 20692 * code64 directive, x86-64: i386-16bit. (line 6) 20693 * COFF auxiliary symbol information: Dim. (line 6) 20694 * COFF structure debugging: Tag. (line 6) 20695 * COFF symbol attributes: COFF Symbols. (line 6) 20696 * COFF symbol descriptor: Desc. (line 6) 20697 * COFF symbol storage class: Scl. (line 6) 20698 * COFF symbol type: Type. (line 11) 20699 * COFF symbols, debugging: Def. (line 6) 20700 * COFF value attribute: Val. (line 6) 20701 * COMDAT: Linkonce. (line 6) 20702 * comm directive: Comm. (line 6) 20703 * command line conventions: Command Line. (line 6) 20704 * command line options, V850: V850 Options. (line 9) 20705 * command-line options ignored, VAX: VAX-Opts. (line 6) 20706 * comments: Comments. (line 6) 20707 * comments, M680x0: M68K-Chars. (line 6) 20708 * comments, removed by preprocessor: Preprocessing. (line 11) 20709 * common directive, SPARC: Sparc-Directives. (line 12) 20710 * common sections: Linkonce. (line 6) 20711 * common variable storage: bss. (line 6) 20712 * compare and jump expansions, i960: Compare-and-branch-i960. 20713 (line 13) 20714 * compare/branch instructions, i960: Compare-and-branch-i960. 20715 (line 6) 20716 * comparison expressions: Infix Ops. (line 55) 20717 * conditional assembly: If. (line 6) 20718 * constant, single character: Chars. (line 6) 20719 * constants: Constants. (line 6) 20720 * constants, bignum: Bignums. (line 6) 20721 * constants, character: Characters. (line 6) 20722 * constants, converted by preprocessor: Preprocessing. (line 14) 20723 * constants, floating point: Flonums. (line 6) 20724 * constants, integer: Integers. (line 6) 20725 * constants, number: Numbers. (line 6) 20726 * constants, Sparc: Sparc-Constants. (line 6) 20727 * constants, string: Strings. (line 6) 20728 * constants, TIC54X: TIC54X-Constants. (line 6) 20729 * conversion instructions, i386: i386-Mnemonics. (line 37) 20730 * conversion instructions, x86-64: i386-Mnemonics. (line 37) 20731 * coprocessor wait, i386: i386-Prefixes. (line 40) 20732 * copy directive, TIC54X: TIC54X-Directives. (line 54) 20733 * cpu directive, M680x0: M68K-Directives. (line 30) 20734 * CR16 Operand Qualifiers: CR16 Operand Qualifiers. 20735 (line 6) 20736 * CR16 support: CR16-Dependent. (line 6) 20737 * crash of assembler: Bug Criteria. (line 9) 20738 * CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9) 20739 * CRIS --emulation=criself command line option: CRIS-Opts. (line 9) 20740 * CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 33) 20741 * CRIS --mul-bug-abort command line option: CRIS-Opts. (line 61) 20742 * CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 61) 20743 * CRIS --no-underscore command line option: CRIS-Opts. (line 15) 20744 * CRIS --pic command line option: CRIS-Opts. (line 27) 20745 * CRIS --underscore command line option: CRIS-Opts. (line 15) 20746 * CRIS -N command line option: CRIS-Opts. (line 57) 20747 * CRIS architecture variant option: CRIS-Opts. (line 33) 20748 * CRIS assembler directive .arch: CRIS-Pseudos. (line 45) 20749 * CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 20750 * CRIS assembler directive .syntax: CRIS-Pseudos. (line 17) 20751 * CRIS assembler directives: CRIS-Pseudos. (line 6) 20752 * CRIS built-in symbols: CRIS-Symbols. (line 6) 20753 * CRIS instruction expansion: CRIS-Expand. (line 6) 20754 * CRIS line comment characters: CRIS-Chars. (line 6) 20755 * CRIS options: CRIS-Opts. (line 6) 20756 * CRIS position-independent code: CRIS-Opts. (line 27) 20757 * CRIS pseudo-op .arch: CRIS-Pseudos. (line 45) 20758 * CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 20759 * CRIS pseudo-op .syntax: CRIS-Pseudos. (line 17) 20760 * CRIS pseudo-ops: CRIS-Pseudos. (line 6) 20761 * CRIS register names: CRIS-Regs. (line 6) 20762 * CRIS support: CRIS-Dependent. (line 6) 20763 * CRIS symbols in position-independent code: CRIS-Pic. (line 6) 20764 * ctbp register, V850: V850-Regs. (line 131) 20765 * ctoff pseudo-op, V850: V850 Opcodes. (line 111) 20766 * ctpc register, V850: V850-Regs. (line 119) 20767 * ctpsw register, V850: V850-Regs. (line 122) 20768 * current address: Dot. (line 6) 20769 * current address, advancing: Org. (line 6) 20770 * D10V @word modifier: D10V-Word. (line 6) 20771 * D10V addressing modes: D10V-Addressing. (line 6) 20772 * D10V floating point: D10V-Float. (line 6) 20773 * D10V line comment character: D10V-Chars. (line 6) 20774 * D10V opcode summary: D10V-Opcodes. (line 6) 20775 * D10V optimization: Overview. (line 462) 20776 * D10V options: D10V-Opts. (line 6) 20777 * D10V registers: D10V-Regs. (line 6) 20778 * D10V size modifiers: D10V-Size. (line 6) 20779 * D10V sub-instruction ordering: D10V-Chars. (line 6) 20780 * D10V sub-instructions: D10V-Subs. (line 6) 20781 * D10V support: D10V-Dependent. (line 6) 20782 * D10V syntax: D10V-Syntax. (line 6) 20783 * D30V addressing modes: D30V-Addressing. (line 6) 20784 * D30V floating point: D30V-Float. (line 6) 20785 * D30V Guarded Execution: D30V-Guarded. (line 6) 20786 * D30V line comment character: D30V-Chars. (line 6) 20787 * D30V nops: Overview. (line 470) 20788 * D30V nops after 32-bit multiply: Overview. (line 473) 20789 * D30V opcode summary: D30V-Opcodes. (line 6) 20790 * D30V optimization: Overview. (line 467) 20791 * D30V options: D30V-Opts. (line 6) 20792 * D30V registers: D30V-Regs. (line 6) 20793 * D30V size modifiers: D30V-Size. (line 6) 20794 * D30V sub-instruction ordering: D30V-Chars. (line 6) 20795 * D30V sub-instructions: D30V-Subs. (line 6) 20796 * D30V support: D30V-Dependent. (line 6) 20797 * D30V syntax: D30V-Syntax. (line 6) 20798 * data alignment on SPARC: Sparc-Aligned-Data. (line 6) 20799 * data and text sections, joining: R. (line 6) 20800 * data directive: Data. (line 6) 20801 * data directive, TIC54X: TIC54X-Directives. (line 61) 20802 * data relocations, ARM: ARM-Relocations. (line 6) 20803 * data section: Ld Sections. (line 9) 20804 * data1 directive, M680x0: M68K-Directives. (line 9) 20805 * data2 directive, M680x0: M68K-Directives. (line 12) 20806 * datalabel, SH64: SH64-Addressing. (line 16) 20807 * dbpc register, V850: V850-Regs. (line 125) 20808 * dbpsw register, V850: V850-Regs. (line 128) 20809 * debuggers, and symbol order: Symbols. (line 10) 20810 * debugging COFF symbols: Def. (line 6) 20811 * DEC syntax: PDP-11-Syntax. (line 6) 20812 * decimal integers: Integers. (line 12) 20813 * def directive: Def. (line 6) 20814 * def directive, TIC54X: TIC54X-Directives. (line 103) 20815 * density instructions: Density Instructions. 20816 (line 6) 20817 * dependency tracking: MD. (line 6) 20818 * deprecated directives: Deprecated. (line 6) 20819 * desc directive: Desc. (line 6) 20820 * descriptor, of a.out symbol: Symbol Desc. (line 6) 20821 * dfloat directive, VAX: VAX-directives. (line 10) 20822 * difference tables altered: Word. (line 12) 20823 * difference tables, warning: K. (line 6) 20824 * differences, mmixal: MMIX-mmixal. (line 6) 20825 * dim directive: Dim. (line 6) 20826 * directives and instructions: Statements. (line 19) 20827 * directives for PowerPC: PowerPC-Pseudo. (line 6) 20828 * directives for SCORE: SCORE-Pseudo. (line 6) 20829 * directives, Blackfin: Blackfin Directives. (line 6) 20830 * directives, M32R: M32R-Directives. (line 6) 20831 * directives, M680x0: M68K-Directives. (line 6) 20832 * directives, machine independent: Pseudo Ops. (line 6) 20833 * directives, Xtensa: Xtensa Directives. (line 6) 20834 * directives, Z8000: Z8000 Directives. (line 6) 20835 * Disable floating-point instructions: MIPS floating-point. (line 6) 20836 * Disable single-precision floating-point operations: MIPS floating-point. 20837 (line 12) 20838 * displacement sizing character, VAX: VAX-operands. (line 12) 20839 * dollar local symbols: Symbol Names. (line 105) 20840 * dot (symbol): Dot. (line 6) 20841 * double directive: Double. (line 6) 20842 * double directive, i386: i386-Float. (line 14) 20843 * double directive, M680x0: M68K-Float. (line 14) 20844 * double directive, M68HC11: M68HC11-Float. (line 14) 20845 * double directive, RX: RX-Float. (line 11) 20846 * double directive, TIC54X: TIC54X-Directives. (line 64) 20847 * double directive, VAX: VAX-float. (line 15) 20848 * double directive, x86-64: i386-Float. (line 14) 20849 * doublequote (\"): Strings. (line 43) 20850 * drlist directive, TIC54X: TIC54X-Directives. (line 73) 20851 * drnolist directive, TIC54X: TIC54X-Directives. (line 73) 20852 * dual directive, i860: Directives-i860. (line 6) 20853 * ECOFF sections: MIPS Object. (line 6) 20854 * ecr register, V850: V850-Regs. (line 113) 20855 * eight-byte integer: Quad. (line 9) 20856 * eipc register, V850: V850-Regs. (line 101) 20857 * eipsw register, V850: V850-Regs. (line 104) 20858 * eject directive: Eject. (line 6) 20859 * ELF symbol type: Type. (line 22) 20860 * else directive: Else. (line 6) 20861 * elseif directive: Elseif. (line 6) 20862 * empty expressions: Empty Exprs. (line 6) 20863 * emsg directive, TIC54X: TIC54X-Directives. (line 77) 20864 * emulation: Overview. (line 786) 20865 * encoding options, i386: i386-Mnemonics. (line 32) 20866 * encoding options, x86-64: i386-Mnemonics. (line 32) 20867 * end directive: End. (line 6) 20868 * enddual directive, i860: Directives-i860. (line 11) 20869 * endef directive: Endef. (line 6) 20870 * endfunc directive: Endfunc. (line 6) 20871 * endianness, MIPS: Overview. (line 683) 20872 * endianness, PJ: Overview. (line 590) 20873 * endif directive: Endif. (line 6) 20874 * endloop directive, TIC54X: TIC54X-Directives. (line 143) 20875 * endm directive: Macro. (line 138) 20876 * endm directive, TIC54X: TIC54X-Directives. (line 153) 20877 * endstruct directive, TIC54X: TIC54X-Directives. (line 216) 20878 * endunion directive, TIC54X: TIC54X-Directives. (line 250) 20879 * environment settings, TIC54X: TIC54X-Env. (line 6) 20880 * EOF, newline must precede: Statements. (line 13) 20881 * ep register, V850: V850-Regs. (line 95) 20882 * equ directive: Equ. (line 6) 20883 * equ directive, TIC54X: TIC54X-Directives. (line 191) 20884 * equiv directive: Equiv. (line 6) 20885 * eqv directive: Eqv. (line 6) 20886 * err directive: Err. (line 6) 20887 * error directive: Error. (line 6) 20888 * error messages: Errors. (line 6) 20889 * error on valid input: Bug Criteria. (line 12) 20890 * errors, caused by warnings: W. (line 16) 20891 * errors, continuing after: Z. (line 6) 20892 * ESA/390 floating point (IEEE): ESA/390 Floating Point. 20893 (line 6) 20894 * ESA/390 support: ESA/390-Dependent. (line 6) 20895 * ESA/390 Syntax: ESA/390 Options. (line 8) 20896 * ESA/390-only directives: ESA/390 Directives. (line 12) 20897 * escape codes, character: Strings. (line 15) 20898 * eval directive, TIC54X: TIC54X-Directives. (line 24) 20899 * even: Z8000 Directives. (line 58) 20900 * even directive, M680x0: M68K-Directives. (line 15) 20901 * even directive, TIC54X: TIC54X-Directives. (line 6) 20902 * exitm directive: Macro. (line 141) 20903 * expr (internal section): As Sections. (line 17) 20904 * expression arguments: Arguments. (line 6) 20905 * expressions: Expressions. (line 6) 20906 * expressions, comparison: Infix Ops. (line 55) 20907 * expressions, empty: Empty Exprs. (line 6) 20908 * expressions, integer: Integer Exprs. (line 6) 20909 * extAuxRegister directive, ARC: ARC Directives. (line 18) 20910 * extCondCode directive, ARC: ARC Directives. (line 41) 20911 * extCoreRegister directive, ARC: ARC Directives. (line 53) 20912 * extend directive M680x0: M68K-Float. (line 17) 20913 * extend directive M68HC11: M68HC11-Float. (line 17) 20914 * extended directive, i960: Directives-i960. (line 13) 20915 * extern directive: Extern. (line 6) 20916 * extInstruction directive, ARC: ARC Directives. (line 78) 20917 * fail directive: Fail. (line 6) 20918 * far_mode directive, TIC54X: TIC54X-Directives. (line 82) 20919 * faster processing (-f): f. (line 6) 20920 * fatal signal: Bug Criteria. (line 9) 20921 * fclist directive, TIC54X: TIC54X-Directives. (line 87) 20922 * fcnolist directive, TIC54X: TIC54X-Directives. (line 87) 20923 * fepc register, V850: V850-Regs. (line 107) 20924 * fepsw register, V850: V850-Regs. (line 110) 20925 * ffloat directive, VAX: VAX-directives. (line 14) 20926 * field directive, TIC54X: TIC54X-Directives. (line 91) 20927 * file directive: File. (line 6) 20928 * file directive, MSP 430: MSP430 Directives. (line 6) 20929 * file name, logical: File. (line 13) 20930 * files, including: Include. (line 6) 20931 * files, input: Input Files. (line 6) 20932 * fill directive: Fill. (line 6) 20933 * filling memory <1>: Skip. (line 6) 20934 * filling memory: Space. (line 6) 20935 * FLIX syntax: Xtensa Syntax. (line 6) 20936 * float directive: Float. (line 6) 20937 * float directive, i386: i386-Float. (line 14) 20938 * float directive, M680x0: M68K-Float. (line 11) 20939 * float directive, M68HC11: M68HC11-Float. (line 11) 20940 * float directive, RX: RX-Float. (line 8) 20941 * float directive, TIC54X: TIC54X-Directives. (line 64) 20942 * float directive, VAX: VAX-float. (line 15) 20943 * float directive, x86-64: i386-Float. (line 14) 20944 * floating point numbers: Flonums. (line 6) 20945 * floating point numbers (double): Double. (line 6) 20946 * floating point numbers (single) <1>: Float. (line 6) 20947 * floating point numbers (single): Single. (line 6) 20948 * floating point, Alpha (IEEE): Alpha Floating Point. 20949 (line 6) 20950 * floating point, ARC (IEEE): ARC Floating Point. (line 6) 20951 * floating point, ARM (IEEE): ARM Floating Point. (line 6) 20952 * floating point, D10V: D10V-Float. (line 6) 20953 * floating point, D30V: D30V-Float. (line 6) 20954 * floating point, ESA/390 (IEEE): ESA/390 Floating Point. 20955 (line 6) 20956 * floating point, H8/300 (IEEE): H8/300 Floating Point. 20957 (line 6) 20958 * floating point, HPPA (IEEE): HPPA Floating Point. (line 6) 20959 * floating point, i386: i386-Float. (line 6) 20960 * floating point, i960 (IEEE): Floating Point-i960. (line 6) 20961 * floating point, M680x0: M68K-Float. (line 6) 20962 * floating point, M68HC11: M68HC11-Float. (line 6) 20963 * floating point, MSP 430 (IEEE): MSP430 Floating Point. 20964 (line 6) 20965 * floating point, RX: RX-Float. (line 6) 20966 * floating point, s390: s390 Floating Point. (line 6) 20967 * floating point, SH (IEEE): SH Floating Point. (line 6) 20968 * floating point, SPARC (IEEE): Sparc-Float. (line 6) 20969 * floating point, V850 (IEEE): V850 Floating Point. (line 6) 20970 * floating point, VAX: VAX-float. (line 6) 20971 * floating point, x86-64: i386-Float. (line 6) 20972 * floating point, Z80: Z80 Floating Point. (line 6) 20973 * flonums: Flonums. (line 6) 20974 * format of error messages: Errors. (line 24) 20975 * format of warning messages: Errors. (line 12) 20976 * formfeed (\f): Strings. (line 18) 20977 * func directive: Func. (line 6) 20978 * functions, in expressions: Operators. (line 6) 20979 * gbr960, i960 postprocessor: Options-i960. (line 40) 20980 * gfloat directive, VAX: VAX-directives. (line 18) 20981 * global: Z8000 Directives. (line 21) 20982 * global directive: Global. (line 6) 20983 * global directive, TIC54X: TIC54X-Directives. (line 103) 20984 * gp register, MIPS: MIPS Object. (line 11) 20985 * gp register, V850: V850-Regs. (line 17) 20986 * grouping data: Sub-Sections. (line 6) 20987 * H8/300 addressing modes: H8/300-Addressing. (line 6) 20988 * H8/300 floating point (IEEE): H8/300 Floating Point. 20989 (line 6) 20990 * H8/300 line comment character: H8/300-Chars. (line 6) 20991 * H8/300 line separator: H8/300-Chars. (line 8) 20992 * H8/300 machine directives (none): H8/300 Directives. (line 6) 20993 * H8/300 opcode summary: H8/300 Opcodes. (line 6) 20994 * H8/300 options: H8/300 Options. (line 6) 20995 * H8/300 registers: H8/300-Regs. (line 6) 20996 * H8/300 size suffixes: H8/300 Opcodes. (line 163) 20997 * H8/300 support: H8/300-Dependent. (line 6) 20998 * H8/300H, assembling for: H8/300 Directives. (line 8) 20999 * half directive, ARC: ARC Directives. (line 156) 21000 * half directive, SPARC: Sparc-Directives. (line 17) 21001 * half directive, TIC54X: TIC54X-Directives. (line 111) 21002 * hex character code (\XD...): Strings. (line 36) 21003 * hexadecimal integers: Integers. (line 15) 21004 * hexadecimal prefix, Z80: Z80-Chars. (line 8) 21005 * hfloat directive, VAX: VAX-directives. (line 22) 21006 * hi pseudo-op, V850: V850 Opcodes. (line 33) 21007 * hi0 pseudo-op, V850: V850 Opcodes. (line 10) 21008 * hidden directive: Hidden. (line 6) 21009 * high directive, M32R: M32R-Directives. (line 18) 21010 * hilo pseudo-op, V850: V850 Opcodes. (line 55) 21011 * HPPA directives not supported: HPPA Directives. (line 11) 21012 * HPPA floating point (IEEE): HPPA Floating Point. (line 6) 21013 * HPPA Syntax: HPPA Options. (line 8) 21014 * HPPA-only directives: HPPA Directives. (line 24) 21015 * hword directive: hword. (line 6) 21016 * i370 support: ESA/390-Dependent. (line 6) 21017 * i386 16-bit code: i386-16bit. (line 6) 21018 * i386 arch directive: i386-Arch. (line 6) 21019 * i386 att_syntax pseudo op: i386-Syntax. (line 6) 21020 * i386 conversion instructions: i386-Mnemonics. (line 37) 21021 * i386 floating point: i386-Float. (line 6) 21022 * i386 immediate operands: i386-Syntax. (line 15) 21023 * i386 instruction naming: i386-Mnemonics. (line 6) 21024 * i386 instruction prefixes: i386-Prefixes. (line 6) 21025 * i386 intel_syntax pseudo op: i386-Syntax. (line 6) 21026 * i386 jump optimization: i386-Jumps. (line 6) 21027 * i386 jump, call, return: i386-Syntax. (line 41) 21028 * i386 jump/call operands: i386-Syntax. (line 15) 21029 * i386 memory references: i386-Memory. (line 6) 21030 * i386 mnemonic compatibility: i386-Mnemonics. (line 62) 21031 * i386 mul, imul instructions: i386-Notes. (line 6) 21032 * i386 options: i386-Options. (line 6) 21033 * i386 register operands: i386-Syntax. (line 15) 21034 * i386 registers: i386-Regs. (line 6) 21035 * i386 sections: i386-Syntax. (line 47) 21036 * i386 size suffixes: i386-Syntax. (line 29) 21037 * i386 source, destination operands: i386-Syntax. (line 22) 21038 * i386 support: i386-Dependent. (line 6) 21039 * i386 syntax compatibility: i386-Syntax. (line 6) 21040 * i80386 support: i386-Dependent. (line 6) 21041 * i860 machine directives: Directives-i860. (line 6) 21042 * i860 opcodes: Opcodes for i860. (line 6) 21043 * i860 support: i860-Dependent. (line 6) 21044 * i960 architecture options: Options-i960. (line 6) 21045 * i960 branch recording: Options-i960. (line 22) 21046 * i960 callj pseudo-opcode: callj-i960. (line 6) 21047 * i960 compare and jump expansions: Compare-and-branch-i960. 21048 (line 13) 21049 * i960 compare/branch instructions: Compare-and-branch-i960. 21050 (line 6) 21051 * i960 floating point (IEEE): Floating Point-i960. (line 6) 21052 * i960 machine directives: Directives-i960. (line 6) 21053 * i960 opcodes: Opcodes for i960. (line 6) 21054 * i960 options: Options-i960. (line 6) 21055 * i960 support: i960-Dependent. (line 6) 21056 * IA-64 line comment character: IA-64-Chars. (line 6) 21057 * IA-64 line separator: IA-64-Chars. (line 8) 21058 * IA-64 options: IA-64 Options. (line 6) 21059 * IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 21060 * IA-64 registers: IA-64-Regs. (line 6) 21061 * IA-64 relocations: IA-64-Relocs. (line 6) 21062 * IA-64 support: IA-64-Dependent. (line 6) 21063 * IA-64 Syntax: IA-64 Options. (line 87) 21064 * ident directive: Ident. (line 6) 21065 * identifiers, ARM: ARM-Chars. (line 15) 21066 * identifiers, MSP 430: MSP430-Chars. (line 8) 21067 * if directive: If. (line 6) 21068 * ifb directive: If. (line 21) 21069 * ifc directive: If. (line 25) 21070 * ifdef directive: If. (line 16) 21071 * ifeq directive: If. (line 33) 21072 * ifeqs directive: If. (line 36) 21073 * ifge directive: If. (line 40) 21074 * ifgt directive: If. (line 44) 21075 * ifle directive: If. (line 48) 21076 * iflt directive: If. (line 52) 21077 * ifnb directive: If. (line 56) 21078 * ifnc directive: If. (line 61) 21079 * ifndef directive: If. (line 65) 21080 * ifne directive: If. (line 72) 21081 * ifnes directive: If. (line 76) 21082 * ifnotdef directive: If. (line 65) 21083 * immediate character, ARM: ARM-Chars. (line 13) 21084 * immediate character, M680x0: M68K-Chars. (line 6) 21085 * immediate character, VAX: VAX-operands. (line 6) 21086 * immediate fields, relaxation: Xtensa Immediate Relaxation. 21087 (line 6) 21088 * immediate operands, i386: i386-Syntax. (line 15) 21089 * immediate operands, x86-64: i386-Syntax. (line 15) 21090 * imul instruction, i386: i386-Notes. (line 6) 21091 * imul instruction, x86-64: i386-Notes. (line 6) 21092 * incbin directive: Incbin. (line 6) 21093 * include directive: Include. (line 6) 21094 * include directive search path: I. (line 6) 21095 * indirect character, VAX: VAX-operands. (line 9) 21096 * infix operators: Infix Ops. (line 6) 21097 * inhibiting interrupts, i386: i386-Prefixes. (line 36) 21098 * input: Input Files. (line 6) 21099 * input file linenumbers: Input Files. (line 35) 21100 * instruction aliases, s390: s390 Aliases. (line 6) 21101 * instruction expansion, CRIS: CRIS-Expand. (line 6) 21102 * instruction expansion, MMIX: MMIX-Expand. (line 6) 21103 * instruction formats, s390: s390 Formats. (line 6) 21104 * instruction marker, s390: s390 Instruction Marker. 21105 (line 6) 21106 * instruction mnemonics, s390: s390 Mnemonics. (line 6) 21107 * instruction naming, i386: i386-Mnemonics. (line 6) 21108 * instruction naming, x86-64: i386-Mnemonics. (line 6) 21109 * instruction operand modifier, s390: s390 Operand Modifier. 21110 (line 6) 21111 * instruction operands, s390: s390 Operands. (line 6) 21112 * instruction prefixes, i386: i386-Prefixes. (line 6) 21113 * instruction set, M680x0: M68K-opcodes. (line 6) 21114 * instruction set, M68HC11: M68HC11-opcodes. (line 6) 21115 * instruction summary, AVR: AVR Opcodes. (line 6) 21116 * instruction summary, D10V: D10V-Opcodes. (line 6) 21117 * instruction summary, D30V: D30V-Opcodes. (line 6) 21118 * instruction summary, H8/300: H8/300 Opcodes. (line 6) 21119 * instruction summary, LM32: LM32 Opcodes. (line 6) 21120 * instruction summary, SH: SH Opcodes. (line 6) 21121 * instruction summary, SH64: SH64 Opcodes. (line 6) 21122 * instruction summary, Z8000: Z8000 Opcodes. (line 6) 21123 * instruction syntax, s390: s390 Syntax. (line 6) 21124 * instructions and directives: Statements. (line 19) 21125 * int directive: Int. (line 6) 21126 * int directive, H8/300: H8/300 Directives. (line 6) 21127 * int directive, i386: i386-Float. (line 21) 21128 * int directive, TIC54X: TIC54X-Directives. (line 111) 21129 * int directive, x86-64: i386-Float. (line 21) 21130 * integer expressions: Integer Exprs. (line 6) 21131 * integer, 16-byte: Octa. (line 6) 21132 * integer, 8-byte: Quad. (line 9) 21133 * integers: Integers. (line 6) 21134 * integers, 16-bit: hword. (line 6) 21135 * integers, 32-bit: Int. (line 6) 21136 * integers, binary: Integers. (line 6) 21137 * integers, decimal: Integers. (line 12) 21138 * integers, hexadecimal: Integers. (line 15) 21139 * integers, octal: Integers. (line 9) 21140 * integers, one byte: Byte. (line 6) 21141 * intel_syntax pseudo op, i386: i386-Syntax. (line 6) 21142 * intel_syntax pseudo op, x86-64: i386-Syntax. (line 6) 21143 * internal assembler sections: As Sections. (line 6) 21144 * internal directive: Internal. (line 6) 21145 * invalid input: Bug Criteria. (line 14) 21146 * invocation summary: Overview. (line 6) 21147 * IP2K architecture options: IP2K-Opts. (line 14) 21148 * IP2K options: IP2K-Opts. (line 6) 21149 * IP2K support: IP2K-Dependent. (line 6) 21150 * irp directive: Irp. (line 6) 21151 * irpc directive: Irpc. (line 6) 21152 * ISA options, SH64: SH64 Options. (line 6) 21153 * joining text and data sections: R. (line 6) 21154 * jump instructions, i386: i386-Mnemonics. (line 56) 21155 * jump instructions, x86-64: i386-Mnemonics. (line 56) 21156 * jump optimization, i386: i386-Jumps. (line 6) 21157 * jump optimization, x86-64: i386-Jumps. (line 6) 21158 * jump/call operands, i386: i386-Syntax. (line 15) 21159 * jump/call operands, x86-64: i386-Syntax. (line 15) 21160 * L16SI instructions, relaxation: Xtensa Immediate Relaxation. 21161 (line 23) 21162 * L16UI instructions, relaxation: Xtensa Immediate Relaxation. 21163 (line 23) 21164 * L32I instructions, relaxation: Xtensa Immediate Relaxation. 21165 (line 23) 21166 * L8UI instructions, relaxation: Xtensa Immediate Relaxation. 21167 (line 23) 21168 * label (:): Statements. (line 30) 21169 * label directive, TIC54X: TIC54X-Directives. (line 123) 21170 * labels: Labels. (line 6) 21171 * lcomm directive: Lcomm. (line 6) 21172 * lcomm directive, COFF: i386-Directives. (line 6) 21173 * ld: Object. (line 15) 21174 * ldouble directive M680x0: M68K-Float. (line 17) 21175 * ldouble directive M68HC11: M68HC11-Float. (line 17) 21176 * ldouble directive, TIC54X: TIC54X-Directives. (line 64) 21177 * LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 21178 * leafproc directive, i960: Directives-i960. (line 18) 21179 * length directive, TIC54X: TIC54X-Directives. (line 127) 21180 * length of symbols: Symbol Intro. (line 14) 21181 * lflags directive (ignored): Lflags. (line 6) 21182 * line comment character: Comments. (line 19) 21183 * line comment character, Alpha: Alpha-Chars. (line 6) 21184 * line comment character, ARM: ARM-Chars. (line 6) 21185 * line comment character, AVR: AVR-Chars. (line 6) 21186 * line comment character, D10V: D10V-Chars. (line 6) 21187 * line comment character, D30V: D30V-Chars. (line 6) 21188 * line comment character, H8/300: H8/300-Chars. (line 6) 21189 * line comment character, IA-64: IA-64-Chars. (line 6) 21190 * line comment character, M680x0: M68K-Chars. (line 6) 21191 * line comment character, MSP 430: MSP430-Chars. (line 6) 21192 * line comment character, s390: s390 Characters. (line 6) 21193 * line comment character, SH: SH-Chars. (line 6) 21194 * line comment character, SH64: SH64-Chars. (line 6) 21195 * line comment character, Sparc: Sparc-Chars. (line 6) 21196 * line comment character, TIC6X: TIC6X Syntax. (line 6) 21197 * line comment character, V850: V850-Chars. (line 6) 21198 * line comment character, Z80: Z80-Chars. (line 6) 21199 * line comment character, Z8000: Z8000-Chars. (line 6) 21200 * line comment characters, CRIS: CRIS-Chars. (line 6) 21201 * line comment characters, MMIX: MMIX-Chars. (line 6) 21202 * line directive: Line. (line 6) 21203 * line directive, MSP 430: MSP430 Directives. (line 14) 21204 * line numbers, in input files: Input Files. (line 35) 21205 * line numbers, in warnings/errors: Errors. (line 16) 21206 * line separator character: Statements. (line 6) 21207 * line separator, Alpha: Alpha-Chars. (line 8) 21208 * line separator, ARM: ARM-Chars. (line 10) 21209 * line separator, AVR: AVR-Chars. (line 10) 21210 * line separator, H8/300: H8/300-Chars. (line 8) 21211 * line separator, IA-64: IA-64-Chars. (line 8) 21212 * line separator, SH: SH-Chars. (line 8) 21213 * line separator, SH64: SH64-Chars. (line 8) 21214 * line separator, Sparc: Sparc-Chars. (line 8) 21215 * line separator, TIC6X: TIC6X Syntax. (line 10) 21216 * line separator, Z8000: Z8000-Chars. (line 8) 21217 * lines starting with #: Comments. (line 39) 21218 * linker: Object. (line 15) 21219 * linker, and assembler: Secs Background. (line 10) 21220 * linkonce directive: Linkonce. (line 6) 21221 * list directive: List. (line 6) 21222 * list directive, TIC54X: TIC54X-Directives. (line 131) 21223 * listing control, turning off: Nolist. (line 6) 21224 * listing control, turning on: List. (line 6) 21225 * listing control: new page: Eject. (line 6) 21226 * listing control: paper size: Psize. (line 6) 21227 * listing control: subtitle: Sbttl. (line 6) 21228 * listing control: title line: Title. (line 6) 21229 * listings, enabling: a. (line 6) 21230 * literal directive: Literal Directive. (line 6) 21231 * literal pool entries, s390: s390 Literal Pool Entries. 21232 (line 6) 21233 * literal_position directive: Literal Position Directive. 21234 (line 6) 21235 * literal_prefix directive: Literal Prefix Directive. 21236 (line 6) 21237 * little endian output, MIPS: Overview. (line 686) 21238 * little endian output, PJ: Overview. (line 593) 21239 * little-endian output, MIPS: MIPS Opts. (line 13) 21240 * little-endian output, TIC6X: TIC6X Options. (line 58) 21241 * LM32 modifiers: LM32-Modifiers. (line 6) 21242 * LM32 opcode summary: LM32 Opcodes. (line 6) 21243 * LM32 options (none): LM32 Options. (line 6) 21244 * LM32 register names: LM32-Regs. (line 6) 21245 * LM32 support: LM32-Dependent. (line 6) 21246 * ln directive: Ln. (line 6) 21247 * lo pseudo-op, V850: V850 Opcodes. (line 22) 21248 * loc directive: Loc. (line 6) 21249 * loc_mark_labels directive: Loc_mark_labels. (line 6) 21250 * local common symbols: Lcomm. (line 6) 21251 * local directive: Local. (line 6) 21252 * local labels: Symbol Names. (line 35) 21253 * local symbol names: Symbol Names. (line 22) 21254 * local symbols, retaining in output: L. (line 6) 21255 * location counter: Dot. (line 6) 21256 * location counter, advancing: Org. (line 6) 21257 * location counter, Z80: Z80-Chars. (line 8) 21258 * logical file name: File. (line 13) 21259 * logical line number: Line. (line 6) 21260 * logical line numbers: Comments. (line 39) 21261 * long directive: Long. (line 6) 21262 * long directive, ARC: ARC Directives. (line 159) 21263 * long directive, i386: i386-Float. (line 21) 21264 * long directive, TIC54X: TIC54X-Directives. (line 135) 21265 * long directive, x86-64: i386-Float. (line 21) 21266 * longcall pseudo-op, V850: V850 Opcodes. (line 123) 21267 * longcalls directive: Longcalls Directive. (line 6) 21268 * longjump pseudo-op, V850: V850 Opcodes. (line 129) 21269 * loop directive, TIC54X: TIC54X-Directives. (line 143) 21270 * LOOP instructions, alignment: Xtensa Automatic Alignment. 21271 (line 6) 21272 * low directive, M32R: M32R-Directives. (line 9) 21273 * lp register, V850: V850-Regs. (line 98) 21274 * lval: Z8000 Directives. (line 27) 21275 * LWP, i386: i386-LWP. (line 6) 21276 * LWP, x86-64: i386-LWP. (line 6) 21277 * M16C architecture option: M32C-Opts. (line 12) 21278 * M32C architecture option: M32C-Opts. (line 9) 21279 * M32C modifiers: M32C-Modifiers. (line 6) 21280 * M32C options: M32C-Opts. (line 6) 21281 * M32C support: M32C-Dependent. (line 6) 21282 * M32R architecture options: M32R-Opts. (line 17) 21283 * M32R directives: M32R-Directives. (line 6) 21284 * M32R options: M32R-Opts. (line 6) 21285 * M32R support: M32R-Dependent. (line 6) 21286 * M32R warnings: M32R-Warnings. (line 6) 21287 * M680x0 addressing modes: M68K-Syntax. (line 21) 21288 * M680x0 architecture options: M68K-Opts. (line 98) 21289 * M680x0 branch improvement: M68K-Branch. (line 6) 21290 * M680x0 directives: M68K-Directives. (line 6) 21291 * M680x0 floating point: M68K-Float. (line 6) 21292 * M680x0 immediate character: M68K-Chars. (line 6) 21293 * M680x0 line comment character: M68K-Chars. (line 6) 21294 * M680x0 opcodes: M68K-opcodes. (line 6) 21295 * M680x0 options: M68K-Opts. (line 6) 21296 * M680x0 pseudo-opcodes: M68K-Branch. (line 6) 21297 * M680x0 size modifiers: M68K-Syntax. (line 8) 21298 * M680x0 support: M68K-Dependent. (line 6) 21299 * M680x0 syntax: M68K-Syntax. (line 8) 21300 * M68HC11 addressing modes: M68HC11-Syntax. (line 17) 21301 * M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 21302 * M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 21303 * M68HC11 assembler directive .interrupt: M68HC11-Directives. (line 26) 21304 * M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 21305 * M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 21306 * M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 21307 * M68HC11 assembler directives: M68HC11-Directives. (line 6) 21308 * M68HC11 branch improvement: M68HC11-Branch. (line 6) 21309 * M68HC11 floating point: M68HC11-Float. (line 6) 21310 * M68HC11 modifiers: M68HC11-Modifiers. (line 6) 21311 * M68HC11 opcodes: M68HC11-opcodes. (line 6) 21312 * M68HC11 options: M68HC11-Opts. (line 6) 21313 * M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 21314 * M68HC11 syntax: M68HC11-Syntax. (line 6) 21315 * M68HC12 assembler directives: M68HC11-Directives. (line 6) 21316 * machine dependencies: Machine Dependencies. 21317 (line 6) 21318 * machine directives, ARC: ARC Directives. (line 6) 21319 * machine directives, ARM: ARM Directives. (line 6) 21320 * machine directives, H8/300 (none): H8/300 Directives. (line 6) 21321 * machine directives, i860: Directives-i860. (line 6) 21322 * machine directives, i960: Directives-i960. (line 6) 21323 * machine directives, MSP 430: MSP430 Directives. (line 6) 21324 * machine directives, SH: SH Directives. (line 6) 21325 * machine directives, SH64: SH64 Directives. (line 9) 21326 * machine directives, SPARC: Sparc-Directives. (line 6) 21327 * machine directives, TIC54X: TIC54X-Directives. (line 6) 21328 * machine directives, TIC6X: TIC6X Directives. (line 6) 21329 * machine directives, V850: V850 Directives. (line 6) 21330 * machine directives, VAX: VAX-directives. (line 6) 21331 * machine directives, x86: i386-Directives. (line 6) 21332 * machine independent directives: Pseudo Ops. (line 6) 21333 * machine instructions (not covered): Manual. (line 14) 21334 * machine-independent syntax: Syntax. (line 6) 21335 * macro directive: Macro. (line 28) 21336 * macro directive, TIC54X: TIC54X-Directives. (line 153) 21337 * macros: Macro. (line 6) 21338 * macros, count executed: Macro. (line 143) 21339 * Macros, MSP 430: MSP430-Macros. (line 6) 21340 * macros, TIC54X: TIC54X-Macros. (line 6) 21341 * make rules: MD. (line 6) 21342 * manual, structure and purpose: Manual. (line 6) 21343 * math builtins, TIC54X: TIC54X-Builtins. (line 6) 21344 * Maximum number of continuation lines: listing. (line 34) 21345 * memory references, i386: i386-Memory. (line 6) 21346 * memory references, x86-64: i386-Memory. (line 6) 21347 * memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 21348 * merging text and data sections: R. (line 6) 21349 * messages from assembler: Errors. (line 6) 21350 * MicroBlaze architectures: MicroBlaze-Dependent. 21351 (line 6) 21352 * MicroBlaze directives: MicroBlaze Directives. 21353 (line 6) 21354 * MicroBlaze support: MicroBlaze-Dependent. 21355 (line 13) 21356 * minus, permitted arguments: Infix Ops. (line 49) 21357 * MIPS architecture options: MIPS Opts. (line 29) 21358 * MIPS big-endian output: MIPS Opts. (line 13) 21359 * MIPS CPU override: MIPS ISA. (line 18) 21360 * MIPS debugging directives: MIPS Stabs. (line 6) 21361 * MIPS DSP Release 1 instruction generation override: MIPS ASE instruction generation overrides. 21362 (line 21) 21363 * MIPS DSP Release 2 instruction generation override: MIPS ASE instruction generation overrides. 21364 (line 26) 21365 * MIPS ECOFF sections: MIPS Object. (line 6) 21366 * MIPS endianness: Overview. (line 683) 21367 * MIPS ISA: Overview. (line 689) 21368 * MIPS ISA override: MIPS ISA. (line 6) 21369 * MIPS little-endian output: MIPS Opts. (line 13) 21370 * MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides. 21371 (line 16) 21372 * MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides. 21373 (line 6) 21374 * MIPS MT instruction generation override: MIPS ASE instruction generation overrides. 21375 (line 32) 21376 * MIPS option stack: MIPS option stack. (line 6) 21377 * MIPS processor: MIPS-Dependent. (line 6) 21378 * MIT: M68K-Syntax. (line 6) 21379 * mlib directive, TIC54X: TIC54X-Directives. (line 159) 21380 * mlist directive, TIC54X: TIC54X-Directives. (line 164) 21381 * MMIX assembler directive BSPEC: MMIX-Pseudos. (line 131) 21382 * MMIX assembler directive BYTE: MMIX-Pseudos. (line 97) 21383 * MMIX assembler directive ESPEC: MMIX-Pseudos. (line 131) 21384 * MMIX assembler directive GREG: MMIX-Pseudos. (line 50) 21385 * MMIX assembler directive IS: MMIX-Pseudos. (line 42) 21386 * MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 21387 * MMIX assembler directive LOCAL: MMIX-Pseudos. (line 28) 21388 * MMIX assembler directive OCTA: MMIX-Pseudos. (line 108) 21389 * MMIX assembler directive PREFIX: MMIX-Pseudos. (line 120) 21390 * MMIX assembler directive TETRA: MMIX-Pseudos. (line 108) 21391 * MMIX assembler directive WYDE: MMIX-Pseudos. (line 108) 21392 * MMIX assembler directives: MMIX-Pseudos. (line 6) 21393 * MMIX line comment characters: MMIX-Chars. (line 6) 21394 * MMIX options: MMIX-Opts. (line 6) 21395 * MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 131) 21396 * MMIX pseudo-op BYTE: MMIX-Pseudos. (line 97) 21397 * MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 131) 21398 * MMIX pseudo-op GREG: MMIX-Pseudos. (line 50) 21399 * MMIX pseudo-op IS: MMIX-Pseudos. (line 42) 21400 * MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 21401 * MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 28) 21402 * MMIX pseudo-op OCTA: MMIX-Pseudos. (line 108) 21403 * MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 120) 21404 * MMIX pseudo-op TETRA: MMIX-Pseudos. (line 108) 21405 * MMIX pseudo-op WYDE: MMIX-Pseudos. (line 108) 21406 * MMIX pseudo-ops: MMIX-Pseudos. (line 6) 21407 * MMIX register names: MMIX-Regs. (line 6) 21408 * MMIX support: MMIX-Dependent. (line 6) 21409 * mmixal differences: MMIX-mmixal. (line 6) 21410 * mmregs directive, TIC54X: TIC54X-Directives. (line 169) 21411 * mmsg directive, TIC54X: TIC54X-Directives. (line 77) 21412 * MMX, i386: i386-SIMD. (line 6) 21413 * MMX, x86-64: i386-SIMD. (line 6) 21414 * mnemonic compatibility, i386: i386-Mnemonics. (line 62) 21415 * mnemonic suffixes, i386: i386-Syntax. (line 29) 21416 * mnemonic suffixes, x86-64: i386-Syntax. (line 29) 21417 * mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 21418 * mnemonics, AVR: AVR Opcodes. (line 6) 21419 * mnemonics, D10V: D10V-Opcodes. (line 6) 21420 * mnemonics, D30V: D30V-Opcodes. (line 6) 21421 * mnemonics, H8/300: H8/300 Opcodes. (line 6) 21422 * mnemonics, LM32: LM32 Opcodes. (line 6) 21423 * mnemonics, SH: SH Opcodes. (line 6) 21424 * mnemonics, SH64: SH64 Opcodes. (line 6) 21425 * mnemonics, Z8000: Z8000 Opcodes. (line 6) 21426 * mnolist directive, TIC54X: TIC54X-Directives. (line 164) 21427 * Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 21428 * MOVI instructions, relaxation: Xtensa Immediate Relaxation. 21429 (line 12) 21430 * MOVW and MOVT relocations, ARM: ARM-Relocations. (line 20) 21431 * MRI compatibility mode: M. (line 6) 21432 * mri directive: MRI. (line 6) 21433 * MRI mode, temporarily: MRI. (line 6) 21434 * MSP 430 floating point (IEEE): MSP430 Floating Point. 21435 (line 6) 21436 * MSP 430 identifiers: MSP430-Chars. (line 8) 21437 * MSP 430 line comment character: MSP430-Chars. (line 6) 21438 * MSP 430 machine directives: MSP430 Directives. (line 6) 21439 * MSP 430 macros: MSP430-Macros. (line 6) 21440 * MSP 430 opcodes: MSP430 Opcodes. (line 6) 21441 * MSP 430 options (none): MSP430 Options. (line 6) 21442 * MSP 430 profiling capability: MSP430 Profiling Capability. 21443 (line 6) 21444 * MSP 430 register names: MSP430-Regs. (line 6) 21445 * MSP 430 support: MSP430-Dependent. (line 6) 21446 * MSP430 Assembler Extensions: MSP430-Ext. (line 6) 21447 * mul instruction, i386: i386-Notes. (line 6) 21448 * mul instruction, x86-64: i386-Notes. (line 6) 21449 * name: Z8000 Directives. (line 18) 21450 * named section: Section. (line 6) 21451 * named sections: Ld Sections. (line 8) 21452 * names, symbol: Symbol Names. (line 6) 21453 * naming object file: o. (line 6) 21454 * new page, in listings: Eject. (line 6) 21455 * newblock directive, TIC54X: TIC54X-Directives. (line 175) 21456 * newline (\n): Strings. (line 21) 21457 * newline, required at file end: Statements. (line 13) 21458 * no-absolute-literals directive: Absolute Literals Directive. 21459 (line 6) 21460 * no-longcalls directive: Longcalls Directive. (line 6) 21461 * no-schedule directive: Schedule Directive. (line 6) 21462 * no-transform directive: Transform Directive. (line 6) 21463 * nolist directive: Nolist. (line 6) 21464 * nolist directive, TIC54X: TIC54X-Directives. (line 131) 21465 * NOP pseudo op, ARM: ARM Opcodes. (line 9) 21466 * notes for Alpha: Alpha Notes. (line 6) 21467 * null-terminated strings: Asciz. (line 6) 21468 * number constants: Numbers. (line 6) 21469 * number of macros executed: Macro. (line 143) 21470 * numbered subsections: Sub-Sections. (line 6) 21471 * numbers, 16-bit: hword. (line 6) 21472 * numeric values: Expressions. (line 6) 21473 * nword directive, SPARC: Sparc-Directives. (line 20) 21474 * object attributes: Object Attributes. (line 6) 21475 * object file: Object. (line 6) 21476 * object file format: Object Formats. (line 6) 21477 * object file name: o. (line 6) 21478 * object file, after errors: Z. (line 6) 21479 * obsolescent directives: Deprecated. (line 6) 21480 * octa directive: Octa. (line 6) 21481 * octal character code (\DDD): Strings. (line 30) 21482 * octal integers: Integers. (line 9) 21483 * offset directive, V850: V850 Directives. (line 6) 21484 * opcode mnemonics, VAX: VAX-opcodes. (line 6) 21485 * opcode names, Xtensa: Xtensa Opcodes. (line 6) 21486 * opcode summary, AVR: AVR Opcodes. (line 6) 21487 * opcode summary, D10V: D10V-Opcodes. (line 6) 21488 * opcode summary, D30V: D30V-Opcodes. (line 6) 21489 * opcode summary, H8/300: H8/300 Opcodes. (line 6) 21490 * opcode summary, LM32: LM32 Opcodes. (line 6) 21491 * opcode summary, SH: SH Opcodes. (line 6) 21492 * opcode summary, SH64: SH64 Opcodes. (line 6) 21493 * opcode summary, Z8000: Z8000 Opcodes. (line 6) 21494 * opcodes for ARC: ARC Opcodes. (line 6) 21495 * opcodes for ARM: ARM Opcodes. (line 6) 21496 * opcodes for MSP 430: MSP430 Opcodes. (line 6) 21497 * opcodes for V850: V850 Opcodes. (line 6) 21498 * opcodes, i860: Opcodes for i860. (line 6) 21499 * opcodes, i960: Opcodes for i960. (line 6) 21500 * opcodes, M680x0: M68K-opcodes. (line 6) 21501 * opcodes, M68HC11: M68HC11-opcodes. (line 6) 21502 * operand delimiters, i386: i386-Syntax. (line 15) 21503 * operand delimiters, x86-64: i386-Syntax. (line 15) 21504 * operand notation, VAX: VAX-operands. (line 6) 21505 * operands in expressions: Arguments. (line 6) 21506 * operator precedence: Infix Ops. (line 11) 21507 * operators, in expressions: Operators. (line 6) 21508 * operators, permitted arguments: Infix Ops. (line 6) 21509 * optimization, D10V: Overview. (line 462) 21510 * optimization, D30V: Overview. (line 467) 21511 * optimizations: Xtensa Optimizations. 21512 (line 6) 21513 * option directive, ARC: ARC Directives. (line 162) 21514 * option directive, TIC54X: TIC54X-Directives. (line 179) 21515 * option summary: Overview. (line 6) 21516 * options for Alpha: Alpha Options. (line 6) 21517 * options for ARC (none): ARC Options. (line 6) 21518 * options for ARM (none): ARM Options. (line 6) 21519 * options for AVR (none): AVR Options. (line 6) 21520 * options for Blackfin (none): Blackfin Options. (line 6) 21521 * options for i386: i386-Options. (line 6) 21522 * options for IA-64: IA-64 Options. (line 6) 21523 * options for LM32 (none): LM32 Options. (line 6) 21524 * options for MSP430 (none): MSP430 Options. (line 6) 21525 * options for PDP-11: PDP-11-Options. (line 6) 21526 * options for PowerPC: PowerPC-Opts. (line 6) 21527 * options for s390: s390 Options. (line 6) 21528 * options for SCORE: SCORE-Opts. (line 6) 21529 * options for SPARC: Sparc-Opts. (line 6) 21530 * options for TIC6X: TIC6X Options. (line 6) 21531 * options for V850 (none): V850 Options. (line 6) 21532 * options for VAX/VMS: VAX-Opts. (line 42) 21533 * options for x86-64: i386-Options. (line 6) 21534 * options for Z80: Z80 Options. (line 6) 21535 * options, all versions of assembler: Invoking. (line 6) 21536 * options, command line: Command Line. (line 13) 21537 * options, CRIS: CRIS-Opts. (line 6) 21538 * options, D10V: D10V-Opts. (line 6) 21539 * options, D30V: D30V-Opts. (line 6) 21540 * options, H8/300: H8/300 Options. (line 6) 21541 * options, i960: Options-i960. (line 6) 21542 * options, IP2K: IP2K-Opts. (line 6) 21543 * options, M32C: M32C-Opts. (line 6) 21544 * options, M32R: M32R-Opts. (line 6) 21545 * options, M680x0: M68K-Opts. (line 6) 21546 * options, M68HC11: M68HC11-Opts. (line 6) 21547 * options, MMIX: MMIX-Opts. (line 6) 21548 * options, PJ: PJ Options. (line 6) 21549 * options, RX: RX-Opts. (line 6) 21550 * options, SH: SH Options. (line 6) 21551 * options, SH64: SH64 Options. (line 6) 21552 * options, TIC54X: TIC54X-Opts. (line 6) 21553 * options, Z8000: Z8000 Options. (line 6) 21554 * org directive: Org. (line 6) 21555 * other attribute, of a.out symbol: Symbol Other. (line 6) 21556 * output file: Object. (line 6) 21557 * p2align directive: P2align. (line 6) 21558 * p2alignl directive: P2align. (line 28) 21559 * p2alignw directive: P2align. (line 28) 21560 * padding the location counter: Align. (line 6) 21561 * padding the location counter given a power of two: P2align. (line 6) 21562 * padding the location counter given number of bytes: Balign. (line 6) 21563 * page, in listings: Eject. (line 6) 21564 * paper size, for listings: Psize. (line 6) 21565 * paths for .include: I. (line 6) 21566 * patterns, writing in memory: Fill. (line 6) 21567 * PDP-11 comments: PDP-11-Syntax. (line 16) 21568 * PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 21569 * PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 21570 * PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 21571 * PDP-11 support: PDP-11-Dependent. (line 6) 21572 * PDP-11 syntax: PDP-11-Syntax. (line 6) 21573 * PIC code generation for ARM: ARM Options. (line 161) 21574 * PIC code generation for M32R: M32R-Opts. (line 42) 21575 * PIC selection, MIPS: MIPS Opts. (line 21) 21576 * PJ endianness: Overview. (line 590) 21577 * PJ options: PJ Options. (line 6) 21578 * PJ support: PJ-Dependent. (line 6) 21579 * plus, permitted arguments: Infix Ops. (line 44) 21580 * popsection directive: PopSection. (line 6) 21581 * Position-independent code, CRIS: CRIS-Opts. (line 27) 21582 * Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 21583 * PowerPC architectures: PowerPC-Opts. (line 6) 21584 * PowerPC directives: PowerPC-Pseudo. (line 6) 21585 * PowerPC options: PowerPC-Opts. (line 6) 21586 * PowerPC support: PPC-Dependent. (line 6) 21587 * precedence of operators: Infix Ops. (line 11) 21588 * precision, floating point: Flonums. (line 6) 21589 * prefix operators: Prefix Ops. (line 6) 21590 * prefixes, i386: i386-Prefixes. (line 6) 21591 * preprocessing: Preprocessing. (line 6) 21592 * preprocessing, turning on and off: Preprocessing. (line 26) 21593 * previous directive: Previous. (line 6) 21594 * primary attributes, COFF symbols: COFF Symbols. (line 13) 21595 * print directive: Print. (line 6) 21596 * proc directive, SPARC: Sparc-Directives. (line 25) 21597 * profiler directive, MSP 430: MSP430 Directives. (line 22) 21598 * profiling capability for MSP 430: MSP430 Profiling Capability. 21599 (line 6) 21600 * protected directive: Protected. (line 6) 21601 * pseudo-op .arch, CRIS: CRIS-Pseudos. (line 45) 21602 * pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 21603 * pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 17) 21604 * pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 131) 21605 * pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 97) 21606 * pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 131) 21607 * pseudo-op GREG, MMIX: MMIX-Pseudos. (line 50) 21608 * pseudo-op IS, MMIX: MMIX-Pseudos. (line 42) 21609 * pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 21610 * pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 28) 21611 * pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 108) 21612 * pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 120) 21613 * pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 108) 21614 * pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 108) 21615 * pseudo-opcodes, M680x0: M68K-Branch. (line 6) 21616 * pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 21617 * pseudo-ops for branch, VAX: VAX-branch. (line 6) 21618 * pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 21619 * pseudo-ops, machine independent: Pseudo Ops. (line 6) 21620 * pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 21621 * psize directive: Psize. (line 6) 21622 * PSR bits: IA-64-Bits. (line 6) 21623 * pstring directive, TIC54X: TIC54X-Directives. (line 208) 21624 * psw register, V850: V850-Regs. (line 116) 21625 * purgem directive: Purgem. (line 6) 21626 * purpose of GNU assembler: GNU Assembler. (line 12) 21627 * pushsection directive: PushSection. (line 6) 21628 * quad directive: Quad. (line 6) 21629 * quad directive, i386: i386-Float. (line 21) 21630 * quad directive, x86-64: i386-Float. (line 21) 21631 * real-mode code, i386: i386-16bit. (line 6) 21632 * ref directive, TIC54X: TIC54X-Directives. (line 103) 21633 * register directive, SPARC: Sparc-Directives. (line 29) 21634 * register names, Alpha: Alpha-Regs. (line 6) 21635 * register names, ARC: ARC-Regs. (line 6) 21636 * register names, ARM: ARM-Regs. (line 6) 21637 * register names, AVR: AVR-Regs. (line 6) 21638 * register names, CRIS: CRIS-Regs. (line 6) 21639 * register names, H8/300: H8/300-Regs. (line 6) 21640 * register names, IA-64: IA-64-Regs. (line 6) 21641 * register names, LM32: LM32-Regs. (line 6) 21642 * register names, MMIX: MMIX-Regs. (line 6) 21643 * register names, MSP 430: MSP430-Regs. (line 6) 21644 * register names, Sparc: Sparc-Regs. (line 6) 21645 * register names, V850: V850-Regs. (line 6) 21646 * register names, VAX: VAX-operands. (line 17) 21647 * register names, Xtensa: Xtensa Registers. (line 6) 21648 * register names, Z80: Z80-Regs. (line 6) 21649 * register naming, s390: s390 Register. (line 6) 21650 * register operands, i386: i386-Syntax. (line 15) 21651 * register operands, x86-64: i386-Syntax. (line 15) 21652 * registers, D10V: D10V-Regs. (line 6) 21653 * registers, D30V: D30V-Regs. (line 6) 21654 * registers, i386: i386-Regs. (line 6) 21655 * registers, SH: SH-Regs. (line 6) 21656 * registers, SH64: SH64-Regs. (line 6) 21657 * registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 21658 * registers, x86-64: i386-Regs. (line 6) 21659 * registers, Z8000: Z8000-Regs. (line 6) 21660 * relaxation: Xtensa Relaxation. (line 6) 21661 * relaxation of ADDI instructions: Xtensa Immediate Relaxation. 21662 (line 43) 21663 * relaxation of branch instructions: Xtensa Branch Relaxation. 21664 (line 6) 21665 * relaxation of call instructions: Xtensa Call Relaxation. 21666 (line 6) 21667 * relaxation of immediate fields: Xtensa Immediate Relaxation. 21668 (line 6) 21669 * relaxation of L16SI instructions: Xtensa Immediate Relaxation. 21670 (line 23) 21671 * relaxation of L16UI instructions: Xtensa Immediate Relaxation. 21672 (line 23) 21673 * relaxation of L32I instructions: Xtensa Immediate Relaxation. 21674 (line 23) 21675 * relaxation of L8UI instructions: Xtensa Immediate Relaxation. 21676 (line 23) 21677 * relaxation of MOVI instructions: Xtensa Immediate Relaxation. 21678 (line 12) 21679 * reloc directive: Reloc. (line 6) 21680 * relocation: Sections. (line 6) 21681 * relocation example: Ld Sections. (line 40) 21682 * relocations, Alpha: Alpha-Relocs. (line 6) 21683 * relocations, Sparc: Sparc-Relocs. (line 6) 21684 * repeat prefixes, i386: i386-Prefixes. (line 44) 21685 * reporting bugs in assembler: Reporting Bugs. (line 6) 21686 * rept directive: Rept. (line 6) 21687 * reserve directive, SPARC: Sparc-Directives. (line 39) 21688 * return instructions, i386: i386-Syntax. (line 41) 21689 * return instructions, x86-64: i386-Syntax. (line 41) 21690 * REX prefixes, i386: i386-Prefixes. (line 46) 21691 * rsect: Z8000 Directives. (line 52) 21692 * RX assembler directive .3byte: RX-Directives. (line 9) 21693 * RX assembler directives: RX-Directives. (line 6) 21694 * RX floating point: RX-Float. (line 6) 21695 * RX modifiers: RX-Modifiers. (line 6) 21696 * RX options: RX-Opts. (line 6) 21697 * RX support: RX-Dependent. (line 6) 21698 * s390 floating point: s390 Floating Point. (line 6) 21699 * s390 instruction aliases: s390 Aliases. (line 6) 21700 * s390 instruction formats: s390 Formats. (line 6) 21701 * s390 instruction marker: s390 Instruction Marker. 21702 (line 6) 21703 * s390 instruction mnemonics: s390 Mnemonics. (line 6) 21704 * s390 instruction operand modifier: s390 Operand Modifier. 21705 (line 6) 21706 * s390 instruction operands: s390 Operands. (line 6) 21707 * s390 instruction syntax: s390 Syntax. (line 6) 21708 * s390 line comment character: s390 Characters. (line 6) 21709 * s390 literal pool entries: s390 Literal Pool Entries. 21710 (line 6) 21711 * s390 options: s390 Options. (line 6) 21712 * s390 register naming: s390 Register. (line 6) 21713 * s390 support: S/390-Dependent. (line 6) 21714 * sblock directive, TIC54X: TIC54X-Directives. (line 182) 21715 * sbttl directive: Sbttl. (line 6) 21716 * schedule directive: Schedule Directive. (line 6) 21717 * scl directive: Scl. (line 6) 21718 * SCORE architectures: SCORE-Opts. (line 6) 21719 * SCORE directives: SCORE-Pseudo. (line 6) 21720 * SCORE options: SCORE-Opts. (line 6) 21721 * SCORE processor: SCORE-Dependent. (line 6) 21722 * sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 21723 * search path for .include: I. (line 6) 21724 * sect directive, MSP 430: MSP430 Directives. (line 18) 21725 * sect directive, TIC54X: TIC54X-Directives. (line 188) 21726 * section directive (COFF version): Section. (line 16) 21727 * section directive (ELF version): Section. (line 73) 21728 * section directive, V850: V850 Directives. (line 9) 21729 * section override prefixes, i386: i386-Prefixes. (line 23) 21730 * Section Stack <1>: SubSection. (line 6) 21731 * Section Stack <2>: PopSection. (line 6) 21732 * Section Stack <3>: Section. (line 68) 21733 * Section Stack <4>: Previous. (line 6) 21734 * Section Stack: PushSection. (line 6) 21735 * section-relative addressing: Secs Background. (line 68) 21736 * sections: Sections. (line 6) 21737 * sections in messages, internal: As Sections. (line 6) 21738 * sections, i386: i386-Syntax. (line 47) 21739 * sections, named: Ld Sections. (line 8) 21740 * sections, x86-64: i386-Syntax. (line 47) 21741 * seg directive, SPARC: Sparc-Directives. (line 44) 21742 * segm: Z8000 Directives. (line 10) 21743 * set directive: Set. (line 6) 21744 * set directive, TIC54X: TIC54X-Directives. (line 191) 21745 * SH addressing modes: SH-Addressing. (line 6) 21746 * SH floating point (IEEE): SH Floating Point. (line 6) 21747 * SH line comment character: SH-Chars. (line 6) 21748 * SH line separator: SH-Chars. (line 8) 21749 * SH machine directives: SH Directives. (line 6) 21750 * SH opcode summary: SH Opcodes. (line 6) 21751 * SH options: SH Options. (line 6) 21752 * SH registers: SH-Regs. (line 6) 21753 * SH support: SH-Dependent. (line 6) 21754 * SH64 ABI options: SH64 Options. (line 29) 21755 * SH64 addressing modes: SH64-Addressing. (line 6) 21756 * SH64 ISA options: SH64 Options. (line 6) 21757 * SH64 line comment character: SH64-Chars. (line 6) 21758 * SH64 line separator: SH64-Chars. (line 8) 21759 * SH64 machine directives: SH64 Directives. (line 9) 21760 * SH64 opcode summary: SH64 Opcodes. (line 6) 21761 * SH64 options: SH64 Options. (line 6) 21762 * SH64 registers: SH64-Regs. (line 6) 21763 * SH64 support: SH64-Dependent. (line 6) 21764 * shigh directive, M32R: M32R-Directives. (line 26) 21765 * short directive: Short. (line 6) 21766 * short directive, ARC: ARC Directives. (line 171) 21767 * short directive, TIC54X: TIC54X-Directives. (line 111) 21768 * SIMD, i386: i386-SIMD. (line 6) 21769 * SIMD, x86-64: i386-SIMD. (line 6) 21770 * single character constant: Chars. (line 6) 21771 * single directive: Single. (line 6) 21772 * single directive, i386: i386-Float. (line 14) 21773 * single directive, x86-64: i386-Float. (line 14) 21774 * single quote, Z80: Z80-Chars. (line 13) 21775 * sixteen bit integers: hword. (line 6) 21776 * sixteen byte integer: Octa. (line 6) 21777 * size directive (COFF version): Size. (line 11) 21778 * size directive (ELF version): Size. (line 19) 21779 * size modifiers, D10V: D10V-Size. (line 6) 21780 * size modifiers, D30V: D30V-Size. (line 6) 21781 * size modifiers, M680x0: M68K-Syntax. (line 8) 21782 * size prefixes, i386: i386-Prefixes. (line 27) 21783 * size suffixes, H8/300: H8/300 Opcodes. (line 163) 21784 * size, translations, Sparc: Sparc-Size-Translations. 21785 (line 6) 21786 * sizes operands, i386: i386-Syntax. (line 29) 21787 * sizes operands, x86-64: i386-Syntax. (line 29) 21788 * skip directive: Skip. (line 6) 21789 * skip directive, M680x0: M68K-Directives. (line 19) 21790 * skip directive, SPARC: Sparc-Directives. (line 48) 21791 * sleb128 directive: Sleb128. (line 6) 21792 * small objects, MIPS ECOFF: MIPS Object. (line 11) 21793 * SmartMIPS instruction generation override: MIPS ASE instruction generation overrides. 21794 (line 11) 21795 * SOM symbol attributes: SOM Symbols. (line 6) 21796 * source program: Input Files. (line 6) 21797 * source, destination operands; i386: i386-Syntax. (line 22) 21798 * source, destination operands; x86-64: i386-Syntax. (line 22) 21799 * sp register: Xtensa Registers. (line 6) 21800 * sp register, V850: V850-Regs. (line 14) 21801 * space directive: Space. (line 6) 21802 * space directive, TIC54X: TIC54X-Directives. (line 196) 21803 * space used, maximum for assembly: statistics. (line 6) 21804 * SPARC architectures: Sparc-Opts. (line 6) 21805 * Sparc constants: Sparc-Constants. (line 6) 21806 * SPARC data alignment: Sparc-Aligned-Data. (line 6) 21807 * SPARC floating point (IEEE): Sparc-Float. (line 6) 21808 * Sparc line comment character: Sparc-Chars. (line 6) 21809 * Sparc line separator: Sparc-Chars. (line 8) 21810 * SPARC machine directives: Sparc-Directives. (line 6) 21811 * SPARC options: Sparc-Opts. (line 6) 21812 * Sparc registers: Sparc-Regs. (line 6) 21813 * Sparc relocations: Sparc-Relocs. (line 6) 21814 * Sparc size translations: Sparc-Size-Translations. 21815 (line 6) 21816 * SPARC support: Sparc-Dependent. (line 6) 21817 * SPARC syntax: Sparc-Aligned-Data. (line 21) 21818 * special characters, ARC: ARC-Chars. (line 6) 21819 * special characters, M680x0: M68K-Chars. (line 6) 21820 * special purpose registers, MSP 430: MSP430-Regs. (line 11) 21821 * sslist directive, TIC54X: TIC54X-Directives. (line 203) 21822 * ssnolist directive, TIC54X: TIC54X-Directives. (line 203) 21823 * stabd directive: Stab. (line 38) 21824 * stabn directive: Stab. (line 48) 21825 * stabs directive: Stab. (line 51) 21826 * stabX directives: Stab. (line 6) 21827 * standard assembler sections: Secs Background. (line 27) 21828 * standard input, as input file: Command Line. (line 10) 21829 * statement separator character: Statements. (line 6) 21830 * statement separator, Alpha: Alpha-Chars. (line 8) 21831 * statement separator, ARM: ARM-Chars. (line 10) 21832 * statement separator, AVR: AVR-Chars. (line 10) 21833 * statement separator, H8/300: H8/300-Chars. (line 8) 21834 * statement separator, IA-64: IA-64-Chars. (line 8) 21835 * statement separator, SH: SH-Chars. (line 8) 21836 * statement separator, SH64: SH64-Chars. (line 8) 21837 * statement separator, Sparc: Sparc-Chars. (line 8) 21838 * statement separator, TIC6X: TIC6X Syntax. (line 10) 21839 * statement separator, Z8000: Z8000-Chars. (line 8) 21840 * statements, structure of: Statements. (line 6) 21841 * statistics, about assembly: statistics. (line 6) 21842 * stopping the assembly: Abort. (line 6) 21843 * string constants: Strings. (line 6) 21844 * string directive: String. (line 8) 21845 * string directive on HPPA: HPPA Directives. (line 137) 21846 * string directive, TIC54X: TIC54X-Directives. (line 208) 21847 * string literals: Ascii. (line 6) 21848 * string, copying to object file: String. (line 8) 21849 * string16 directive: String. (line 8) 21850 * string16, copying to object file: String. (line 8) 21851 * string32 directive: String. (line 8) 21852 * string32, copying to object file: String. (line 8) 21853 * string64 directive: String. (line 8) 21854 * string64, copying to object file: String. (line 8) 21855 * string8 directive: String. (line 8) 21856 * string8, copying to object file: String. (line 8) 21857 * struct directive: Struct. (line 6) 21858 * struct directive, TIC54X: TIC54X-Directives. (line 216) 21859 * structure debugging, COFF: Tag. (line 6) 21860 * sub-instruction ordering, D10V: D10V-Chars. (line 6) 21861 * sub-instruction ordering, D30V: D30V-Chars. (line 6) 21862 * sub-instructions, D10V: D10V-Subs. (line 6) 21863 * sub-instructions, D30V: D30V-Subs. (line 6) 21864 * subexpressions: Arguments. (line 24) 21865 * subsection directive: SubSection. (line 6) 21866 * subsym builtins, TIC54X: TIC54X-Macros. (line 16) 21867 * subtitles for listings: Sbttl. (line 6) 21868 * subtraction, permitted arguments: Infix Ops. (line 49) 21869 * summary of options: Overview. (line 6) 21870 * support: HPPA-Dependent. (line 6) 21871 * supporting files, including: Include. (line 6) 21872 * suppressing warnings: W. (line 11) 21873 * sval: Z8000 Directives. (line 33) 21874 * symbol attributes: Symbol Attributes. (line 6) 21875 * symbol attributes, a.out: a.out Symbols. (line 6) 21876 * symbol attributes, COFF: COFF Symbols. (line 6) 21877 * symbol attributes, SOM: SOM Symbols. (line 6) 21878 * symbol descriptor, COFF: Desc. (line 6) 21879 * symbol modifiers <1>: AVR-Modifiers. (line 12) 21880 * symbol modifiers <2>: M68HC11-Modifiers. (line 12) 21881 * symbol modifiers <3>: M32C-Modifiers. (line 11) 21882 * symbol modifiers <4>: LM32-Modifiers. (line 12) 21883 * symbol modifiers: RX-Modifiers. (line 11) 21884 * symbol names: Symbol Names. (line 6) 21885 * symbol names, $ in <1>: D30V-Chars. (line 63) 21886 * symbol names, $ in <2>: SH64-Chars. (line 10) 21887 * symbol names, $ in <3>: SH-Chars. (line 10) 21888 * symbol names, $ in: D10V-Chars. (line 46) 21889 * symbol names, local: Symbol Names. (line 22) 21890 * symbol names, temporary: Symbol Names. (line 35) 21891 * symbol storage class (COFF): Scl. (line 6) 21892 * symbol type: Symbol Type. (line 6) 21893 * symbol type, COFF: Type. (line 11) 21894 * symbol type, ELF: Type. (line 22) 21895 * symbol value: Symbol Value. (line 6) 21896 * symbol value, setting: Set. (line 6) 21897 * symbol values, assigning: Setting Symbols. (line 6) 21898 * symbol versioning: Symver. (line 6) 21899 * symbol, common: Comm. (line 6) 21900 * symbol, making visible to linker: Global. (line 6) 21901 * symbolic debuggers, information for: Stab. (line 6) 21902 * symbols: Symbols. (line 6) 21903 * Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 21904 * symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 21905 * symbols, assigning values to: Equ. (line 6) 21906 * Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 21907 * Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 21908 * symbols, local common: Lcomm. (line 6) 21909 * symver directive: Symver. (line 6) 21910 * syntax compatibility, i386: i386-Syntax. (line 6) 21911 * syntax compatibility, x86-64: i386-Syntax. (line 6) 21912 * syntax, AVR: AVR-Modifiers. (line 6) 21913 * syntax, Blackfin: Blackfin Syntax. (line 6) 21914 * syntax, D10V: D10V-Syntax. (line 6) 21915 * syntax, D30V: D30V-Syntax. (line 6) 21916 * syntax, LM32: LM32-Modifiers. (line 6) 21917 * syntax, M32C: M32C-Modifiers. (line 6) 21918 * syntax, M680x0: M68K-Syntax. (line 8) 21919 * syntax, M68HC11 <1>: M68HC11-Syntax. (line 6) 21920 * syntax, M68HC11: M68HC11-Modifiers. (line 6) 21921 * syntax, machine-independent: Syntax. (line 6) 21922 * syntax, RX: RX-Modifiers. (line 6) 21923 * syntax, SPARC: Sparc-Aligned-Data. (line 21) 21924 * syntax, Xtensa assembler: Xtensa Syntax. (line 6) 21925 * sysproc directive, i960: Directives-i960. (line 37) 21926 * tab (\t): Strings. (line 27) 21927 * tab directive, TIC54X: TIC54X-Directives. (line 247) 21928 * tag directive: Tag. (line 6) 21929 * tag directive, TIC54X: TIC54X-Directives. (line 216) 21930 * tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 21931 * temporary symbol names: Symbol Names. (line 35) 21932 * text and data sections, joining: R. (line 6) 21933 * text directive: Text. (line 6) 21934 * text section: Ld Sections. (line 9) 21935 * tfloat directive, i386: i386-Float. (line 14) 21936 * tfloat directive, x86-64: i386-Float. (line 14) 21937 * Thumb support: ARM-Dependent. (line 6) 21938 * TIC54X builtin math functions: TIC54X-Builtins. (line 6) 21939 * TIC54X machine directives: TIC54X-Directives. (line 6) 21940 * TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 21941 * TIC54X options: TIC54X-Opts. (line 6) 21942 * TIC54X subsym builtins: TIC54X-Macros. (line 16) 21943 * TIC54X support: TIC54X-Dependent. (line 6) 21944 * TIC54X-specific macros: TIC54X-Macros. (line 6) 21945 * TIC6X big-endian output: TIC6X Options. (line 58) 21946 * TIC6X line comment character: TIC6X Syntax. (line 6) 21947 * TIC6X line separator: TIC6X Syntax. (line 10) 21948 * TIC6X little-endian output: TIC6X Options. (line 58) 21949 * TIC6X machine directives: TIC6X Directives. (line 6) 21950 * TIC6X options: TIC6X Options. (line 6) 21951 * TIC6X support: TIC6X-Dependent. (line 6) 21952 * time, total for assembly: statistics. (line 6) 21953 * title directive: Title. (line 6) 21954 * TMS320C6X support: TIC6X-Dependent. (line 6) 21955 * tp register, V850: V850-Regs. (line 20) 21956 * transform directive: Transform Directive. (line 6) 21957 * trusted compiler: f. (line 6) 21958 * turning preprocessing on and off: Preprocessing. (line 26) 21959 * type directive (COFF version): Type. (line 11) 21960 * type directive (ELF version): Type. (line 22) 21961 * type of a symbol: Symbol Type. (line 6) 21962 * ualong directive, SH: SH Directives. (line 6) 21963 * uaword directive, SH: SH Directives. (line 6) 21964 * ubyte directive, TIC54X: TIC54X-Directives. (line 36) 21965 * uchar directive, TIC54X: TIC54X-Directives. (line 36) 21966 * uhalf directive, TIC54X: TIC54X-Directives. (line 111) 21967 * uint directive, TIC54X: TIC54X-Directives. (line 111) 21968 * uleb128 directive: Uleb128. (line 6) 21969 * ulong directive, TIC54X: TIC54X-Directives. (line 135) 21970 * undefined section: Ld Sections. (line 36) 21971 * union directive, TIC54X: TIC54X-Directives. (line 250) 21972 * unsegm: Z8000 Directives. (line 14) 21973 * usect directive, TIC54X: TIC54X-Directives. (line 262) 21974 * ushort directive, TIC54X: TIC54X-Directives. (line 111) 21975 * uword directive, TIC54X: TIC54X-Directives. (line 111) 21976 * V850 command line options: V850 Options. (line 9) 21977 * V850 floating point (IEEE): V850 Floating Point. (line 6) 21978 * V850 line comment character: V850-Chars. (line 6) 21979 * V850 machine directives: V850 Directives. (line 6) 21980 * V850 opcodes: V850 Opcodes. (line 6) 21981 * V850 options (none): V850 Options. (line 6) 21982 * V850 register names: V850-Regs. (line 6) 21983 * V850 support: V850-Dependent. (line 6) 21984 * val directive: Val. (line 6) 21985 * value attribute, COFF: Val. (line 6) 21986 * value of a symbol: Symbol Value. (line 6) 21987 * var directive, TIC54X: TIC54X-Directives. (line 272) 21988 * VAX bitfields not supported: VAX-no. (line 6) 21989 * VAX branch improvement: VAX-branch. (line 6) 21990 * VAX command-line options ignored: VAX-Opts. (line 6) 21991 * VAX displacement sizing character: VAX-operands. (line 12) 21992 * VAX floating point: VAX-float. (line 6) 21993 * VAX immediate character: VAX-operands. (line 6) 21994 * VAX indirect character: VAX-operands. (line 9) 21995 * VAX machine directives: VAX-directives. (line 6) 21996 * VAX opcode mnemonics: VAX-opcodes. (line 6) 21997 * VAX operand notation: VAX-operands. (line 6) 21998 * VAX register names: VAX-operands. (line 17) 21999 * VAX support: Vax-Dependent. (line 6) 22000 * Vax-11 C compatibility: VAX-Opts. (line 42) 22001 * VAX/VMS options: VAX-Opts. (line 42) 22002 * version directive: Version. (line 6) 22003 * version directive, TIC54X: TIC54X-Directives. (line 276) 22004 * version of assembler: v. (line 6) 22005 * versions of symbols: Symver. (line 6) 22006 * visibility <1>: Internal. (line 6) 22007 * visibility <2>: Hidden. (line 6) 22008 * visibility: Protected. (line 6) 22009 * VMS (VAX) options: VAX-Opts. (line 42) 22010 * vtable_entry directive: VTableEntry. (line 6) 22011 * vtable_inherit directive: VTableInherit. (line 6) 22012 * warning directive: Warning. (line 6) 22013 * warning for altered difference tables: K. (line 6) 22014 * warning messages: Errors. (line 6) 22015 * warnings, causing error: W. (line 16) 22016 * warnings, M32R: M32R-Warnings. (line 6) 22017 * warnings, suppressing: W. (line 11) 22018 * warnings, switching on: W. (line 19) 22019 * weak directive: Weak. (line 6) 22020 * weakref directive: Weakref. (line 6) 22021 * whitespace: Whitespace. (line 6) 22022 * whitespace, removed by preprocessor: Preprocessing. (line 7) 22023 * wide floating point directives, VAX: VAX-directives. (line 10) 22024 * width directive, TIC54X: TIC54X-Directives. (line 127) 22025 * Width of continuation lines of disassembly output: listing. (line 21) 22026 * Width of first line disassembly output: listing. (line 16) 22027 * Width of source line output: listing. (line 28) 22028 * wmsg directive, TIC54X: TIC54X-Directives. (line 77) 22029 * word directive: Word. (line 6) 22030 * word directive, ARC: ARC Directives. (line 174) 22031 * word directive, H8/300: H8/300 Directives. (line 6) 22032 * word directive, i386: i386-Float. (line 21) 22033 * word directive, SPARC: Sparc-Directives. (line 51) 22034 * word directive, TIC54X: TIC54X-Directives. (line 111) 22035 * word directive, x86-64: i386-Float. (line 21) 22036 * writing patterns in memory: Fill. (line 6) 22037 * wval: Z8000 Directives. (line 24) 22038 * x86 machine directives: i386-Directives. (line 6) 22039 * x86-64 arch directive: i386-Arch. (line 6) 22040 * x86-64 att_syntax pseudo op: i386-Syntax. (line 6) 22041 * x86-64 conversion instructions: i386-Mnemonics. (line 37) 22042 * x86-64 floating point: i386-Float. (line 6) 22043 * x86-64 immediate operands: i386-Syntax. (line 15) 22044 * x86-64 instruction naming: i386-Mnemonics. (line 6) 22045 * x86-64 intel_syntax pseudo op: i386-Syntax. (line 6) 22046 * x86-64 jump optimization: i386-Jumps. (line 6) 22047 * x86-64 jump, call, return: i386-Syntax. (line 41) 22048 * x86-64 jump/call operands: i386-Syntax. (line 15) 22049 * x86-64 memory references: i386-Memory. (line 6) 22050 * x86-64 options: i386-Options. (line 6) 22051 * x86-64 register operands: i386-Syntax. (line 15) 22052 * x86-64 registers: i386-Regs. (line 6) 22053 * x86-64 sections: i386-Syntax. (line 47) 22054 * x86-64 size suffixes: i386-Syntax. (line 29) 22055 * x86-64 source, destination operands: i386-Syntax. (line 22) 22056 * x86-64 support: i386-Dependent. (line 6) 22057 * x86-64 syntax compatibility: i386-Syntax. (line 6) 22058 * xfloat directive, TIC54X: TIC54X-Directives. (line 64) 22059 * xlong directive, TIC54X: TIC54X-Directives. (line 135) 22060 * Xtensa architecture: Xtensa-Dependent. (line 6) 22061 * Xtensa assembler syntax: Xtensa Syntax. (line 6) 22062 * Xtensa directives: Xtensa Directives. (line 6) 22063 * Xtensa opcode names: Xtensa Opcodes. (line 6) 22064 * Xtensa register names: Xtensa Registers. (line 6) 22065 * xword directive, SPARC: Sparc-Directives. (line 55) 22066 * Z80 $: Z80-Chars. (line 8) 22067 * Z80 ': Z80-Chars. (line 13) 22068 * Z80 floating point: Z80 Floating Point. (line 6) 22069 * Z80 line comment character: Z80-Chars. (line 6) 22070 * Z80 options: Z80 Options. (line 6) 22071 * Z80 registers: Z80-Regs. (line 6) 22072 * Z80 support: Z80-Dependent. (line 6) 22073 * Z80 Syntax: Z80 Options. (line 47) 22074 * Z80, \: Z80-Chars. (line 11) 22075 * Z80, case sensitivity: Z80-Case. (line 6) 22076 * Z80-only directives: Z80 Directives. (line 9) 22077 * Z800 addressing modes: Z8000-Addressing. (line 6) 22078 * Z8000 directives: Z8000 Directives. (line 6) 22079 * Z8000 line comment character: Z8000-Chars. (line 6) 22080 * Z8000 line separator: Z8000-Chars. (line 8) 22081 * Z8000 opcode summary: Z8000 Opcodes. (line 6) 22082 * Z8000 options: Z8000 Options. (line 6) 22083 * Z8000 registers: Z8000-Regs. (line 6) 22084 * Z8000 support: Z8000-Dependent. (line 6) 22085 * zdaoff pseudo-op, V850: V850 Opcodes. (line 99) 22086 * zero register, V850: V850-Regs. (line 7) 22087 * zero-terminated strings: Asciz. (line 6) 22088 22089 22090 22091 Tag Table: 22092 Node: Top913 22093 Node: Overview1899 22094 Node: Manual34738 22095 Node: GNU Assembler35682 22096 Node: Object Formats36853 22097 Node: Command Line37305 22098 Node: Input Files38392 22099 Node: Object40373 22100 Node: Errors41269 22101 Node: Invoking42464 22102 Node: a44419 22103 Node: alternate46330 22104 Node: D46502 22105 Node: f46735 22106 Node: I47243 22107 Node: K47787 22108 Node: L48091 22109 Node: listing48830 22110 Node: M50489 22111 Node: MD54890 22112 Node: o55316 22113 Node: R55771 22114 Node: statistics56801 22115 Node: traditional-format57208 22116 Node: v57681 22117 Node: W57956 22118 Node: Z58863 22119 Node: Syntax59385 22120 Node: Preprocessing59976 22121 Node: Whitespace61539 22122 Node: Comments61935 22123 Node: Symbol Intro64171 22124 Node: Statements64861 22125 Node: Constants66782 22126 Node: Characters67413 22127 Node: Strings67915 22128 Node: Chars70081 22129 Node: Numbers70835 22130 Node: Integers71375 22131 Node: Bignums72031 22132 Node: Flonums72387 22133 Node: Sections74134 22134 Node: Secs Background74512 22135 Node: Ld Sections79551 22136 Node: As Sections81935 22137 Node: Sub-Sections82845 22138 Node: bss85990 22139 Node: Symbols86940 22140 Node: Labels87588 22141 Node: Setting Symbols88319 22142 Node: Symbol Names88873 22143 Node: Dot93914 22144 Node: Symbol Attributes94361 22145 Node: Symbol Value95098 22146 Node: Symbol Type96143 22147 Node: a.out Symbols96531 22148 Node: Symbol Desc96793 22149 Node: Symbol Other97088 22150 Node: COFF Symbols97257 22151 Node: SOM Symbols97930 22152 Node: Expressions98372 22153 Node: Empty Exprs99121 22154 Node: Integer Exprs99468 22155 Node: Arguments99863 22156 Node: Operators100969 22157 Node: Prefix Ops101304 22158 Node: Infix Ops101632 22159 Node: Pseudo Ops104022 22160 Node: Abort109523 22161 Node: ABORT (COFF)109935 22162 Node: Align110143 22163 Node: Altmacro112425 22164 Node: Ascii113754 22165 Node: Asciz114063 22166 Node: Balign114308 22167 Node: Byte116171 22168 Node: CFI directives116419 22169 Node: Comm122046 22170 Ref: Comm-Footnote-1123647 22171 Node: Data124009 22172 Node: Def124326 22173 Node: Desc124558 22174 Node: Dim125058 22175 Node: Double125315 22176 Node: Eject125653 22177 Node: Else125828 22178 Node: Elseif126128 22179 Node: End126422 22180 Node: Endef126637 22181 Node: Endfunc126814 22182 Node: Endif126989 22183 Node: Equ127250 22184 Node: Equiv127764 22185 Node: Eqv128320 22186 Node: Err128684 22187 Node: Error128995 22188 Node: Exitm129440 22189 Node: Extern129609 22190 Node: Fail129870 22191 Node: File130315 22192 Node: Fill131644 22193 Node: Float132608 22194 Node: Func132950 22195 Node: Global133540 22196 Node: Gnu_attribute134297 22197 Node: Hidden134522 22198 Node: hword135108 22199 Node: Ident135436 22200 Node: If136010 22201 Node: Incbin139069 22202 Node: Include139826 22203 Node: Int140377 22204 Node: Internal140758 22205 Node: Irp141406 22206 Node: Irpc142285 22207 Node: Lcomm143202 22208 Node: Lflags143950 22209 Node: Line144144 22210 Node: Linkonce145057 22211 Node: List146286 22212 Node: Ln146894 22213 Node: Loc147044 22214 Node: Loc_mark_labels148430 22215 Node: Local148914 22216 Node: Long149526 22217 Node: Macro149704 22218 Node: MRI155626 22219 Node: Noaltmacro155964 22220 Node: Nolist156133 22221 Node: Octa156563 22222 Node: Org156897 22223 Node: P2align158180 22224 Node: PopSection160108 22225 Node: Previous160616 22226 Node: Print162029 22227 Node: Protected162258 22228 Node: Psize162905 22229 Node: Purgem163589 22230 Node: PushSection163810 22231 Node: Quad164553 22232 Node: Reloc165009 22233 Node: Rept165770 22234 Node: Sbttl166184 22235 Node: Scl166549 22236 Node: Section166890 22237 Node: Set173005 22238 Node: Short173576 22239 Node: Single173897 22240 Node: Size174242 22241 Node: Skip174916 22242 Node: Sleb128175240 22243 Node: Space175564 22244 Node: Stab176205 22245 Node: String178209 22246 Node: Struct179203 22247 Node: SubSection179928 22248 Node: Symver180491 22249 Node: Tag182884 22250 Node: Text183266 22251 Node: Title183587 22252 Node: Type183968 22253 Node: Uleb128186262 22254 Node: Val186586 22255 Node: Version186836 22256 Node: VTableEntry187111 22257 Node: VTableInherit187401 22258 Node: Warning187851 22259 Node: Weak188085 22260 Node: Weakref188754 22261 Node: Word189719 22262 Node: Deprecated191565 22263 Node: Object Attributes191800 22264 Node: GNU Object Attributes193520 22265 Node: Defining New Object Attributes196073 22266 Node: Machine Dependencies196870 22267 Node: Alpha-Dependent200115 22268 Node: Alpha Notes200529 22269 Node: Alpha Options200810 22270 Node: Alpha Syntax203285 22271 Node: Alpha-Chars203754 22272 Node: Alpha-Regs203985 22273 Node: Alpha-Relocs204372 22274 Node: Alpha Floating Point210630 22275 Node: Alpha Directives210852 22276 Node: Alpha Opcodes216375 22277 Node: ARC-Dependent216670 22278 Node: ARC Options217053 22279 Node: ARC Syntax218122 22280 Node: ARC-Chars218354 22281 Node: ARC-Regs218486 22282 Node: ARC Floating Point218610 22283 Node: ARC Directives218921 22284 Node: ARC Opcodes224893 22285 Node: ARM-Dependent225119 22286 Node: ARM Options225584 22287 Node: ARM Syntax233930 22288 Node: ARM-Instruction-Set234298 22289 Node: ARM-Chars235530 22290 Node: ARM-Regs236082 22291 Node: ARM-Neon-Alignment236291 22292 Node: ARM Floating Point236755 22293 Node: ARM-Relocations236954 22294 Node: ARM Directives237946 22295 Ref: arm_pad239263 22296 Ref: arm_fnend242600 22297 Ref: arm_fnstart242924 22298 Ref: arm_save245934 22299 Ref: arm_setfp246635 22300 Node: ARM Opcodes249716 22301 Node: ARM Mapping Symbols251804 22302 Node: ARM Unwinding Tutorial252614 22303 Node: AVR-Dependent258814 22304 Node: AVR Options259104 22305 Node: AVR Syntax262607 22306 Node: AVR-Chars262894 22307 Node: AVR-Regs263300 22308 Node: AVR-Modifiers263879 22309 Node: AVR Opcodes265939 22310 Node: Blackfin-Dependent271185 22311 Node: Blackfin Options271497 22312 Node: Blackfin Syntax272471 22313 Node: Blackfin Directives278204 22314 Node: CR16-Dependent278623 22315 Node: CR16 Operand Qualifiers278871 22316 Node: CRIS-Dependent281512 22317 Node: CRIS-Opts281858 22318 Ref: march-option283476 22319 Node: CRIS-Expand285293 22320 Node: CRIS-Symbols286476 22321 Node: CRIS-Syntax287645 22322 Node: CRIS-Chars287981 22323 Node: CRIS-Pic288532 22324 Ref: crispic288728 22325 Node: CRIS-Regs292268 22326 Node: CRIS-Pseudos292685 22327 Ref: crisnous293461 22328 Node: D10V-Dependent294743 22329 Node: D10V-Opts295094 22330 Node: D10V-Syntax296056 22331 Node: D10V-Size296585 22332 Node: D10V-Subs297558 22333 Node: D10V-Chars298593 22334 Node: D10V-Regs300197 22335 Node: D10V-Addressing301242 22336 Node: D10V-Word301928 22337 Node: D10V-Float302443 22338 Node: D10V-Opcodes302754 22339 Node: D30V-Dependent303147 22340 Node: D30V-Opts303500 22341 Node: D30V-Syntax304175 22342 Node: D30V-Size304707 22343 Node: D30V-Subs305678 22344 Node: D30V-Chars306713 22345 Node: D30V-Guarded309011 22346 Node: D30V-Regs309691 22347 Node: D30V-Addressing310830 22348 Node: D30V-Float311498 22349 Node: D30V-Opcodes311809 22350 Node: H8/300-Dependent312202 22351 Node: H8/300 Options312614 22352 Node: H8/300 Syntax312881 22353 Node: H8/300-Chars313182 22354 Node: H8/300-Regs313481 22355 Node: H8/300-Addressing314400 22356 Node: H8/300 Floating Point315441 22357 Node: H8/300 Directives315768 22358 Node: H8/300 Opcodes316896 22359 Node: HPPA-Dependent325218 22360 Node: HPPA Notes325653 22361 Node: HPPA Options326411 22362 Node: HPPA Syntax326606 22363 Node: HPPA Floating Point327876 22364 Node: HPPA Directives328082 22365 Node: HPPA Opcodes336768 22366 Node: ESA/390-Dependent337027 22367 Node: ESA/390 Notes337487 22368 Node: ESA/390 Options338278 22369 Node: ESA/390 Syntax338488 22370 Node: ESA/390 Floating Point340661 22371 Node: ESA/390 Directives340940 22372 Node: ESA/390 Opcodes344229 22373 Node: i386-Dependent344491 22374 Node: i386-Options345688 22375 Node: i386-Directives350054 22376 Node: i386-Syntax350792 22377 Node: i386-Mnemonics353356 22378 Node: i386-Regs356649 22379 Node: i386-Prefixes358694 22380 Node: i386-Memory361454 22381 Node: i386-Jumps364391 22382 Node: i386-Float365512 22383 Node: i386-SIMD367343 22384 Node: i386-LWP368452 22385 Node: i386-16bit369288 22386 Node: i386-Bugs371359 22387 Node: i386-Arch372113 22388 Node: i386-Notes374774 22389 Node: i860-Dependent375632 22390 Node: Notes-i860376028 22391 Node: Options-i860376933 22392 Node: Directives-i860378296 22393 Node: Opcodes for i860379365 22394 Node: i960-Dependent381532 22395 Node: Options-i960381935 22396 Node: Floating Point-i960385820 22397 Node: Directives-i960386088 22398 Node: Opcodes for i960388122 22399 Node: callj-i960388739 22400 Node: Compare-and-branch-i960389228 22401 Node: IA-64-Dependent391132 22402 Node: IA-64 Options391433 22403 Node: IA-64 Syntax394584 22404 Node: IA-64-Chars394990 22405 Node: IA-64-Regs395220 22406 Node: IA-64-Bits396146 22407 Node: IA-64-Relocs396676 22408 Node: IA-64 Opcodes397148 22409 Node: IP2K-Dependent397420 22410 Node: IP2K-Opts397648 22411 Node: LM32-Dependent398128 22412 Node: LM32 Options398423 22413 Node: LM32 Syntax399057 22414 Node: LM32-Regs399304 22415 Node: LM32-Modifiers400263 22416 Node: LM32 Opcodes401619 22417 Node: M32C-Dependent401923 22418 Node: M32C-Opts402447 22419 Node: M32C-Modifiers402870 22420 Node: M32R-Dependent404657 22421 Node: M32R-Opts404978 22422 Node: M32R-Directives409145 22423 Node: M32R-Warnings413120 22424 Node: M68K-Dependent416126 22425 Node: M68K-Opts416593 22426 Node: M68K-Syntax423966 22427 Node: M68K-Moto-Syntax425806 22428 Node: M68K-Float428396 22429 Node: M68K-Directives428916 22430 Node: M68K-opcodes430244 22431 Node: M68K-Branch430470 22432 Node: M68K-Chars434668 22433 Node: M68HC11-Dependent435081 22434 Node: M68HC11-Opts435618 22435 Node: M68HC11-Syntax439439 22436 Node: M68HC11-Modifiers441653 22437 Node: M68HC11-Directives443481 22438 Node: M68HC11-Float444857 22439 Node: M68HC11-opcodes445385 22440 Node: M68HC11-Branch445567 22441 Node: MicroBlaze-Dependent448016 22442 Node: MicroBlaze Directives448646 22443 Node: MIPS-Dependent450003 22444 Node: MIPS Opts451166 22445 Node: MIPS Object461678 22446 Node: MIPS Stabs463244 22447 Node: MIPS symbol sizes463966 22448 Node: MIPS ISA465635 22449 Node: MIPS autoextend467109 22450 Node: MIPS insn467839 22451 Node: MIPS option stack469109 22452 Node: MIPS ASE instruction generation overrides469883 22453 Node: MIPS floating-point471697 22454 Node: MMIX-Dependent472583 22455 Node: MMIX-Opts472963 22456 Node: MMIX-Expand476567 22457 Node: MMIX-Syntax477882 22458 Ref: mmixsite478239 22459 Node: MMIX-Chars479080 22460 Node: MMIX-Symbols479734 22461 Node: MMIX-Regs481802 22462 Node: MMIX-Pseudos482827 22463 Ref: MMIX-loc482968 22464 Ref: MMIX-local484048 22465 Ref: MMIX-is484580 22466 Ref: MMIX-greg484851 22467 Ref: GREG-base485770 22468 Ref: MMIX-byte487087 22469 Ref: MMIX-constants487558 22470 Ref: MMIX-prefix488204 22471 Ref: MMIX-spec488578 22472 Node: MMIX-mmixal488912 22473 Node: MSP430-Dependent492410 22474 Node: MSP430 Options492876 22475 Node: MSP430 Syntax493162 22476 Node: MSP430-Macros493478 22477 Node: MSP430-Chars494209 22478 Node: MSP430-Regs494522 22479 Node: MSP430-Ext495082 22480 Node: MSP430 Floating Point496903 22481 Node: MSP430 Directives497127 22482 Node: MSP430 Opcodes497918 22483 Node: MSP430 Profiling Capability498313 22484 Node: PDP-11-Dependent500642 22485 Node: PDP-11-Options501031 22486 Node: PDP-11-Pseudos506102 22487 Node: PDP-11-Syntax506447 22488 Node: PDP-11-Mnemonics507199 22489 Node: PDP-11-Synthetic507501 22490 Node: PJ-Dependent507719 22491 Node: PJ Options507944 22492 Node: PPC-Dependent508221 22493 Node: PowerPC-Opts508505 22494 Node: PowerPC-Pseudo511124 22495 Node: RX-Dependent511723 22496 Node: RX-Opts512116 22497 Node: RX-Modifiers514142 22498 Node: RX-Directives514473 22499 Node: RX-Float514789 22500 Node: S/390-Dependent515412 22501 Node: s390 Options516120 22502 Node: s390 Characters517666 22503 Node: s390 Syntax517859 22504 Node: s390 Register518760 22505 Node: s390 Mnemonics519573 22506 Node: s390 Operands522593 22507 Node: s390 Formats525212 22508 Node: s390 Aliases533058 22509 Node: s390 Operand Modifier536955 22510 Node: s390 Instruction Marker540756 22511 Node: s390 Literal Pool Entries541772 22512 Node: s390 Directives543695 22513 Node: s390 Floating Point547610 22514 Node: SCORE-Dependent548056 22515 Node: SCORE-Opts548330 22516 Node: SCORE-Pseudo549618 22517 Node: SH-Dependent551674 22518 Node: SH Options552086 22519 Node: SH Syntax553141 22520 Node: SH-Chars553414 22521 Node: SH-Regs553708 22522 Node: SH-Addressing554322 22523 Node: SH Floating Point555231 22524 Node: SH Directives556325 22525 Node: SH Opcodes556695 22526 Node: SH64-Dependent561017 22527 Node: SH64 Options561380 22528 Node: SH64 Syntax563177 22529 Node: SH64-Chars563460 22530 Node: SH64-Regs563760 22531 Node: SH64-Addressing564856 22532 Node: SH64 Directives566039 22533 Node: SH64 Opcodes567149 22534 Node: Sparc-Dependent567865 22535 Node: Sparc-Opts568277 22536 Node: Sparc-Aligned-Data570534 22537 Node: Sparc-Syntax571366 22538 Node: Sparc-Chars571940 22539 Node: Sparc-Regs572173 22540 Node: Sparc-Constants577284 22541 Node: Sparc-Relocs582044 22542 Node: Sparc-Size-Translations586724 22543 Node: Sparc-Float588373 22544 Node: Sparc-Directives588568 22545 Node: TIC54X-Dependent590528 22546 Node: TIC54X-Opts591255 22547 Node: TIC54X-Block592298 22548 Node: TIC54X-Env592658 22549 Node: TIC54X-Constants593006 22550 Node: TIC54X-Subsyms593408 22551 Node: TIC54X-Locals595317 22552 Node: TIC54X-Builtins596061 22553 Node: TIC54X-Ext598532 22554 Node: TIC54X-Directives599103 22555 Node: TIC54X-Macros610004 22556 Node: TIC54X-MMRegs612115 22557 Node: TIC6X-Dependent612331 22558 Node: TIC6X Options612631 22559 Node: TIC6X Syntax615249 22560 Node: TIC6X Directives616173 22561 Node: Z80-Dependent617242 22562 Node: Z80 Options617630 22563 Node: Z80 Syntax619053 22564 Node: Z80-Chars619725 22565 Node: Z80-Regs620259 22566 Node: Z80-Case620611 22567 Node: Z80 Floating Point621056 22568 Node: Z80 Directives621250 22569 Node: Z80 Opcodes622875 22570 Node: Z8000-Dependent624219 22571 Node: Z8000 Options625180 22572 Node: Z8000 Syntax625397 22573 Node: Z8000-Chars625687 22574 Node: Z8000-Regs625920 22575 Node: Z8000-Addressing626710 22576 Node: Z8000 Directives627827 22577 Node: Z8000 Opcodes629436 22578 Node: Vax-Dependent639378 22579 Node: VAX-Opts639895 22580 Node: VAX-float643630 22581 Node: VAX-directives644262 22582 Node: VAX-opcodes645123 22583 Node: VAX-branch645512 22584 Node: VAX-operands648019 22585 Node: VAX-no648782 22586 Node: V850-Dependent649019 22587 Node: V850 Options649416 22588 Node: V850 Syntax652267 22589 Node: V850-Chars652507 22590 Node: V850-Regs652672 22591 Node: V850 Floating Point654240 22592 Node: V850 Directives654446 22593 Node: V850 Opcodes656049 22594 Node: Xtensa-Dependent661941 22595 Node: Xtensa Options662670 22596 Node: Xtensa Syntax665480 22597 Node: Xtensa Opcodes667369 22598 Node: Xtensa Registers669163 22599 Node: Xtensa Optimizations669796 22600 Node: Density Instructions670248 22601 Node: Xtensa Automatic Alignment671350 22602 Node: Xtensa Relaxation673797 22603 Node: Xtensa Branch Relaxation674705 22604 Node: Xtensa Call Relaxation676077 22605 Node: Xtensa Immediate Relaxation677863 22606 Node: Xtensa Directives680437 22607 Node: Schedule Directive682146 22608 Node: Longcalls Directive682486 22609 Node: Transform Directive683030 22610 Node: Literal Directive683772 22611 Ref: Literal Directive-Footnote-1687311 22612 Node: Literal Position Directive687453 22613 Node: Literal Prefix Directive689152 22614 Node: Absolute Literals Directive690050 22615 Node: Reporting Bugs691357 22616 Node: Bug Criteria692083 22617 Node: Bug Reporting692850 22618 Node: Acknowledgements699499 22619 Ref: Acknowledgements-Footnote-1704465 22620 Node: GNU Free Documentation License704491 22621 Node: AS Index729660 22622 22623 End Tag Table 22624
