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      1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the LiveVariables analysis pass.  For each machine
     11 // instruction in the function, this pass calculates the set of registers that
     12 // are immediately dead after the instruction (i.e., the instruction calculates
     13 // the value, but it is never used) and the set of registers that are used by
     14 // the instruction, but are never used after the instruction (i.e., they are
     15 // killed).
     16 //
     17 // This class computes live variables using a sparse implementation based on
     18 // the machine code SSA form.  This class computes live variable information for
     19 // each virtual and _register allocatable_ physical register in a function.  It
     20 // uses the dominance properties of SSA form to efficiently compute live
     21 // variables for virtual registers, and assumes that physical registers are only
     22 // live within a single basic block (allowing it to do a single local analysis
     23 // to resolve physical register lifetimes in each basic block).  If a physical
     24 // register is not register allocatable, it is not tracked.  This is useful for
     25 // things like the stack pointer and condition codes.
     26 //
     27 //===----------------------------------------------------------------------===//
     28 
     29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
     30 #define LLVM_CODEGEN_LIVEVARIABLES_H
     31 
     32 #include "llvm/ADT/DenseMap.h"
     33 #include "llvm/ADT/IndexedMap.h"
     34 #include "llvm/ADT/SmallSet.h"
     35 #include "llvm/ADT/SmallVector.h"
     36 #include "llvm/ADT/SparseBitVector.h"
     37 #include "llvm/CodeGen/MachineFunctionPass.h"
     38 #include "llvm/CodeGen/MachineInstr.h"
     39 #include "llvm/Target/TargetRegisterInfo.h"
     40 
     41 namespace llvm {
     42 
     43 class MachineBasicBlock;
     44 class MachineRegisterInfo;
     45 
     46 class LiveVariables : public MachineFunctionPass {
     47 public:
     48   static char ID; // Pass identification, replacement for typeid
     49   LiveVariables() : MachineFunctionPass(ID) {
     50     initializeLiveVariablesPass(*PassRegistry::getPassRegistry());
     51   }
     52 
     53   /// VarInfo - This represents the regions where a virtual register is live in
     54   /// the program.  We represent this with three different pieces of
     55   /// information: the set of blocks in which the instruction is live
     56   /// throughout, the set of blocks in which the instruction is actually used,
     57   /// and the set of non-phi instructions that are the last users of the value.
     58   ///
     59   /// In the common case where a value is defined and killed in the same block,
     60   /// There is one killing instruction, and AliveBlocks is empty.
     61   ///
     62   /// Otherwise, the value is live out of the block.  If the value is live
     63   /// throughout any blocks, these blocks are listed in AliveBlocks.  Blocks
     64   /// where the liveness range ends are not included in AliveBlocks, instead
     65   /// being captured by the Kills set.  In these blocks, the value is live into
     66   /// the block (unless the value is defined and killed in the same block) and
     67   /// lives until the specified instruction.  Note that there cannot ever be a
     68   /// value whose Kills set contains two instructions from the same basic block.
     69   ///
     70   /// PHI nodes complicate things a bit.  If a PHI node is the last user of a
     71   /// value in one of its predecessor blocks, it is not listed in the kills set,
     72   /// but does include the predecessor block in the AliveBlocks set (unless that
     73   /// block also defines the value).  This leads to the (perfectly sensical)
     74   /// situation where a value is defined in a block, and the last use is a phi
     75   /// node in the successor.  In this case, AliveBlocks is empty (the value is
     76   /// not live across any  blocks) and Kills is empty (phi nodes are not
     77   /// included). This is sensical because the value must be live to the end of
     78   /// the block, but is not live in any successor blocks.
     79   struct VarInfo {
     80     /// AliveBlocks - Set of blocks in which this value is alive completely
     81     /// through.  This is a bit set which uses the basic block number as an
     82     /// index.
     83     ///
     84     SparseBitVector<> AliveBlocks;
     85 
     86     /// Kills - List of MachineInstruction's which are the last use of this
     87     /// virtual register (kill it) in their basic block.
     88     ///
     89     std::vector<MachineInstr*> Kills;
     90 
     91     /// removeKill - Delete a kill corresponding to the specified
     92     /// machine instruction. Returns true if there was a kill
     93     /// corresponding to this instruction, false otherwise.
     94     bool removeKill(MachineInstr *MI) {
     95       std::vector<MachineInstr*>::iterator
     96         I = std::find(Kills.begin(), Kills.end(), MI);
     97       if (I == Kills.end())
     98         return false;
     99       Kills.erase(I);
    100       return true;
    101     }
    102 
    103     /// findKill - Find a kill instruction in MBB. Return NULL if none is found.
    104     MachineInstr *findKill(const MachineBasicBlock *MBB) const;
    105 
    106     /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
    107     /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
    108     /// MBB, it is not considered live in.
    109     bool isLiveIn(const MachineBasicBlock &MBB,
    110                   unsigned Reg,
    111                   MachineRegisterInfo &MRI);
    112 
    113     void dump() const;
    114   };
    115 
    116 private:
    117   /// VirtRegInfo - This list is a mapping from virtual register number to
    118   /// variable information.
    119   ///
    120   IndexedMap<VarInfo, VirtReg2IndexFunctor> VirtRegInfo;
    121 
    122   /// PHIJoins - list of virtual registers that are PHI joins. These registers
    123   /// may have multiple definitions, and they require special handling when
    124   /// building live intervals.
    125   SparseBitVector<> PHIJoins;
    126 
    127 private:   // Intermediate data structures
    128   MachineFunction *MF;
    129 
    130   MachineRegisterInfo* MRI;
    131 
    132   const TargetRegisterInfo *TRI;
    133 
    134   // PhysRegInfo - Keep track of which instruction was the last def of a
    135   // physical register. This is a purely local property, because all physical
    136   // register references are presumed dead across basic blocks.
    137   MachineInstr **PhysRegDef;
    138 
    139   // PhysRegInfo - Keep track of which instruction was the last use of a
    140   // physical register. This is a purely local property, because all physical
    141   // register references are presumed dead across basic blocks.
    142   MachineInstr **PhysRegUse;
    143 
    144   SmallVector<unsigned, 4> *PHIVarInfo;
    145 
    146   // DistanceMap - Keep track the distance of a MI from the start of the
    147   // current basic block.
    148   DenseMap<MachineInstr*, unsigned> DistanceMap;
    149 
    150   /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
    151   /// uses. Pay special attention to the sub-register uses which may come below
    152   /// the last use of the whole register.
    153   bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
    154 
    155   /// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
    156   void HandleRegMask(const MachineOperand&);
    157 
    158   void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
    159   void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
    160                         SmallVectorImpl<unsigned> &Defs);
    161   void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
    162 
    163   /// FindLastRefOrPartRef - Return the last reference or partial reference of
    164   /// the specified register.
    165   MachineInstr *FindLastRefOrPartRef(unsigned Reg);
    166 
    167   /// FindLastPartialDef - Return the last partial def of the specified
    168   /// register. Also returns the sub-registers that're defined by the
    169   /// instruction.
    170   MachineInstr *FindLastPartialDef(unsigned Reg,
    171                                    SmallSet<unsigned,4> &PartDefRegs);
    172 
    173   /// analyzePHINodes - Gather information about the PHI nodes in here. In
    174   /// particular, we want to map the variable information of a virtual
    175   /// register which is used in a PHI node. We map that to the BB the vreg
    176   /// is coming from.
    177   void analyzePHINodes(const MachineFunction& Fn);
    178 public:
    179 
    180   virtual bool runOnMachineFunction(MachineFunction &MF);
    181 
    182   /// RegisterDefIsDead - Return true if the specified instruction defines the
    183   /// specified register, but that definition is dead.
    184   bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
    185 
    186   //===--------------------------------------------------------------------===//
    187   //  API to update live variable information
    188 
    189   /// replaceKillInstruction - Update register kill info by replacing a kill
    190   /// instruction with a new one.
    191   void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
    192                               MachineInstr *NewMI);
    193 
    194   /// addVirtualRegisterKilled - Add information about the fact that the
    195   /// specified register is killed after being used by the specified
    196   /// instruction. If AddIfNotFound is true, add a implicit operand if it's
    197   /// not found.
    198   void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
    199                                 bool AddIfNotFound = false) {
    200     if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
    201       getVarInfo(IncomingReg).Kills.push_back(MI);
    202   }
    203 
    204   /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
    205   /// register from the live variable information. Returns true if the
    206   /// variable was marked as killed by the specified instruction,
    207   /// false otherwise.
    208   bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
    209     if (!getVarInfo(reg).removeKill(MI))
    210       return false;
    211 
    212     bool Removed = false;
    213     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    214       MachineOperand &MO = MI->getOperand(i);
    215       if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
    216         MO.setIsKill(false);
    217         Removed = true;
    218         break;
    219       }
    220     }
    221 
    222     assert(Removed && "Register is not used by this instruction!");
    223     (void)Removed;
    224     return true;
    225   }
    226 
    227   /// removeVirtualRegistersKilled - Remove all killed info for the specified
    228   /// instruction.
    229   void removeVirtualRegistersKilled(MachineInstr *MI);
    230 
    231   /// addVirtualRegisterDead - Add information about the fact that the specified
    232   /// register is dead after being used by the specified instruction. If
    233   /// AddIfNotFound is true, add a implicit operand if it's not found.
    234   void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
    235                               bool AddIfNotFound = false) {
    236     if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
    237       getVarInfo(IncomingReg).Kills.push_back(MI);
    238   }
    239 
    240   /// removeVirtualRegisterDead - Remove the specified kill of the virtual
    241   /// register from the live variable information. Returns true if the
    242   /// variable was marked dead at the specified instruction, false
    243   /// otherwise.
    244   bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
    245     if (!getVarInfo(reg).removeKill(MI))
    246       return false;
    247 
    248     bool Removed = false;
    249     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    250       MachineOperand &MO = MI->getOperand(i);
    251       if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
    252         MO.setIsDead(false);
    253         Removed = true;
    254         break;
    255       }
    256     }
    257     assert(Removed && "Register is not defined by this instruction!");
    258     (void)Removed;
    259     return true;
    260   }
    261 
    262   void getAnalysisUsage(AnalysisUsage &AU) const;
    263 
    264   virtual void releaseMemory() {
    265     VirtRegInfo.clear();
    266   }
    267 
    268   /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
    269   /// register.
    270   VarInfo &getVarInfo(unsigned RegIdx);
    271 
    272   void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
    273                                MachineBasicBlock *BB);
    274   void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
    275                                MachineBasicBlock *BB,
    276                                std::vector<MachineBasicBlock*> &WorkList);
    277   void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
    278   void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
    279                         MachineInstr *MI);
    280 
    281   bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) {
    282     return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI);
    283   }
    284 
    285   /// isLiveOut - Determine if Reg is live out from MBB, when not considering
    286   /// PHI nodes. This means that Reg is either killed by a successor block or
    287   /// passed through one.
    288   bool isLiveOut(unsigned Reg, const MachineBasicBlock &MBB);
    289 
    290   /// addNewBlock - Add a new basic block BB between DomBB and SuccBB. All
    291   /// variables that are live out of DomBB and live into SuccBB will be marked
    292   /// as passing live through BB. This method assumes that the machine code is
    293   /// still in SSA form.
    294   void addNewBlock(MachineBasicBlock *BB,
    295                    MachineBasicBlock *DomBB,
    296                    MachineBasicBlock *SuccBB);
    297 
    298   /// isPHIJoin - Return true if Reg is a phi join register.
    299   bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
    300 
    301   /// setPHIJoin - Mark Reg as a phi join register.
    302   void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
    303 };
    304 
    305 } // End llvm namespace
    306 
    307 #endif
    308