| /external/llvm/lib/CodeGen/ |
| AllocationOrder.h | 52 unsigned Reg = Order[Pos++];
53 if (!isHint(Reg))
54 return Reg;
|
| RegAllocBase.cpp | 71 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
72 if (MRI->reg_nodbg_empty(Reg))
74 enqueue(&LIS->getInterval(Reg));
85 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
88 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
90 LIS->removeInterval(VirtReg->reg);
101 << MRI->getRegClass(VirtReg->reg)->getName()
102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n');
112 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg);
121 VRM->assignVirt2Phys(VirtReg->reg,
[all...] |
| DeadMachineInstructionElim.cpp | 69 unsigned Reg = MO.getReg();
70 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
72 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
75 if (!MRI->use_nodbg_empty(Reg))
127 unsigned Reg = MO.getReg();
128 if (!TargetRegisterInfo::isVirtualRegister(Reg))
131 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
155 unsigned Reg = MO.getReg();
156 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
[all...] |
| ProcessImplicitDefs.cpp | 78 unsigned Reg = MI->getOperand(0).getReg();
80 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
84 MRI->use_nodbg_begin(Reg),
110 !TRI->regsOverlap(Reg, UserReg))
112 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
|
| AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
61 unsigned Node = GroupNodeIndices[Reg];
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
75 Regs.push_back(Reg);
82 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
[all...] |
| CalcSpillWeights.cpp | 53 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
54 if (MRI.reg_nodbg_empty(Reg))
56 VRAI.CalculateWeightAndHint(LIS.getInterval(Reg));
61 // Return the preferred allocation register for reg, given a COPY instruction.
62 static unsigned copyHint(const MachineInstr *mi, unsigned reg,
66 if (mi->getOperand(0).getReg() == reg) {
82 const TargetRegisterClass *rc = mri.getRegClass(reg);
88 // reg:sub should match the physreg hreg.
128 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
133 for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
[all...] |
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 84 unsigned Reg = Op.getReg();
85 printRegName(O, Reg);
|
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 84 unsigned Reg) const;
106 /// \p Reg until it finds an Instruction that isn't a COPY returns
111 unsigned Reg) const {
112 // The Reg parameter to the function must always be defined by either a PHI
114 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
115 "Reg cannot be a physical register");
117 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
118 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
144 unsigned Reg = MI.getOperand(0).getReg();
145 const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
80 if (Reg == 0) {
83 Reg = State.AllocateReg(GPRArgRegs, 4);
84 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
99 if (HiRegList[i] == Reg)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 57 void Hexagon_CCState::MarkAllocated(unsigned Reg) {
59 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
101 unsigned Reg = Hexagon::R0;
102 addLoc(CCValAssign::getReg(0, MVT::i32, Reg, MVT::i32,
107 unsigned Reg = Hexagon::D0;
108 addLoc(CCValAssign::getReg(0, MVT::i64, Reg, MVT::i64,
|
| HexagonCallingConvLower.h | 73 bool isAllocated(unsigned Reg) const {
74 return UsedRegs[Reg/32] & (1 << (Reg&31));
120 unsigned AllocateReg(unsigned Reg) {
121 if (isAllocated(Reg)) return 0;
122 MarkAllocated(Reg);
123 return Reg;
127 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
128 if (isAllocated(Reg)) return 0;
129 MarkAllocated(Reg);
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 74 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
76 MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(Reg, true), 0);
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 125 unsigned Reg = MO.getReg();
126 if (!Reg)
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
167 unsigned Reg = isSub
170 if (Reg) {
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL
[all...] |
| X86FloatingPoint.cpp | 1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
118 unsigned Reg = *I;
119 if (Reg < X86::FP0 || Reg > X86::FP6)
121 Mask |= 1 << (Reg - X86::FP0);
228 void pushReg(unsigned Reg) {
229 assert(Reg < NumFPRegs && "Register number out of range!");
232 Stack[StackTop] = Reg;
233 RegMap[Reg] = StackTop++;
289 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
[all...] |
| X86InstrBuilder.h | 44 unsigned Reg;
56 Base.Reg = 0;
64 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
92 // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
103 /// [Reg + Offset], i.e., one with no scale or index, but with a
108 unsigned Reg, bool isKill, int Offset) {
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
113 /// [Reg + Reg]
[all...] |
| /external/qemu/target-i386/ |
| ops_sse_header.h | 21 #define Reg MMXReg
24 #define Reg XMMReg
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg)
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg)
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg)
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg
[all...] |
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/distutils/tests/ |
| test_msvc9compiler.py | 124 from distutils.msvc9compiler import Reg
125 self.assertRaises(KeyError, Reg.get_value, 'xxx', 'xxx')
130 v = Reg.get_value(path, u'dragfullwindows')
135 keys = Reg.read_keys(HKCU, 'xxxx')
138 keys = Reg.read_keys(HKCU, r'Control Panel')
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/distutils/tests/ |
| test_msvc9compiler.py | 124 from distutils.msvc9compiler import Reg
125 self.assertRaises(KeyError, Reg.get_value, 'xxx', 'xxx')
130 v = Reg.get_value(path, u'dragfullwindows')
135 keys = Reg.read_keys(HKCU, 'xxxx')
138 keys = Reg.read_keys(HKCU, r'Control Panel')
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 65 unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
66 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0);
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 70 OS << markup("<reg:")
248 // a single GPRPair reg operand is used in the .td file to replace the two
255 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
256 if (MRC.contains(Reg)) {
263 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
283 unsigned Reg = Op.getReg();
284 printRegName(O, Reg);
336 // REG 0 0 - e.g. R5
337 // REG REG 0,SH_OPC - e.g. R5, ROR R
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 117 unsigned Reg = CSI[i].getReg();
118 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
121 EntryBlock->addLiveIn(Reg);
|
| MipsSERegisterInfo.cpp | 124 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
125 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
126 .addReg(Reg, RegState::Kill);
128 FrameReg = Reg;
|
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 153 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
154 if (!LiveOutRegInfo.inBounds(Reg))
157 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
169 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
172 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
178 LiveOutRegInfo.grow(Reg);
179 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
197 unsigned Reg = It->second;
198 LiveOutRegInfo.grow(Reg);
199 LiveOutRegInfo[Reg].IsValid = false
[all...] |
| RegisterScavenging.h | 45 ScavengedInfo(int FI = -1) : FrameIndex(FI), Reg(0), Restore(NULL) {}
52 unsigned Reg;
162 void setUsed(unsigned Reg);
165 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
171 bool isUsed(unsigned Reg, bool CheckReserved = true) const {
172 return !RegsAvailable.test(Reg) || (CheckReserved && isReserved(Reg));
175 /// isAliasUsed - Is Reg or an alias currently in use?
176 bool isAliasUsed(unsigned Reg) const
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 42 unsigned Reg;
|
