| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 82 /// BasePtr - ARM physical register used as a base ptr in complex stack
85 unsigned BasePtr;
150 unsigned getBaseRegister() const { return BasePtr; }
|
| Thumb1FrameLowering.cpp | 97 unsigned BasePtr = RegInfo->getBaseRegister();
206 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 52 /// BasePtr - X86 physical register used as a base ptr in complex stack
55 unsigned BasePtr;
126 unsigned getBaseRegister() const { return BasePtr; }
|
| X86RegisterInfo.cpp | 84 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
428 return MRI->canReserveReg(BasePtr);
469 unsigned BasePtr;
474 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
476 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
478 BasePtr = StackPtr;
480 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
484 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 116 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 71 unsigned BasePtr = getFrameRegister(MF);
77 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
87 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
109 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
117 .addReg(BasePtr).addImm(HighOffset).addReg(0);
123 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 348 ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
349 assert(BasePtr);
364 uint64_t Index = BasePtr->getZExtValue();
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 348 ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
349 assert(BasePtr);
364 uint64_t Index = BasePtr->getZExtValue();
|
| /external/clang/lib/AST/ |
| CXXInheritance.cpp | 109 const void *BasePtr = static_cast<const void*>(Base->getCanonicalDecl());
111 const_cast<void *>(BasePtr),
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 116 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
118 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | [all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 390 SDValue BasePtr = LD->getBasePtr();
396 if (DAG.isBaseWithConstantOffset(BasePtr) &&
397 isWordAligned(BasePtr->getOperand(0), DAG)) {
398 SDValue NewBasePtr = BasePtr->getOperand(0);
399 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
403 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
406 BasePtr->getValueType(0));
414 BasePtr, LD->getPointerInfo(), MVT::i16,
416 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
432 // Lower to a call to __misaligned_load(BasePtr)
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGClass.cpp | 617 llvm::Type *BasePtr = ConvertType(BaseElementTy);
618 BasePtr = llvm::PointerType::getUnqual(BasePtr);
620 BasePtr);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
