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      1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the X86 implementation of the TargetRegisterInfo class.
     11 // This file is responsible for the frame pointer elimination optimization
     12 // on X86.
     13 //
     14 //===----------------------------------------------------------------------===//
     15 
     16 #include "X86RegisterInfo.h"
     17 #include "X86.h"
     18 #include "X86InstrBuilder.h"
     19 #include "X86MachineFunctionInfo.h"
     20 #include "X86Subtarget.h"
     21 #include "X86TargetMachine.h"
     22 #include "llvm/ADT/BitVector.h"
     23 #include "llvm/ADT/STLExtras.h"
     24 #include "llvm/CodeGen/MachineFrameInfo.h"
     25 #include "llvm/CodeGen/MachineFunction.h"
     26 #include "llvm/CodeGen/MachineFunctionPass.h"
     27 #include "llvm/CodeGen/MachineInstrBuilder.h"
     28 #include "llvm/CodeGen/MachineModuleInfo.h"
     29 #include "llvm/CodeGen/MachineRegisterInfo.h"
     30 #include "llvm/CodeGen/ValueTypes.h"
     31 #include "llvm/IR/Constants.h"
     32 #include "llvm/IR/Function.h"
     33 #include "llvm/IR/Type.h"
     34 #include "llvm/MC/MCAsmInfo.h"
     35 #include "llvm/Support/CommandLine.h"
     36 #include "llvm/Support/ErrorHandling.h"
     37 #include "llvm/Target/TargetFrameLowering.h"
     38 #include "llvm/Target/TargetInstrInfo.h"
     39 #include "llvm/Target/TargetMachine.h"
     40 #include "llvm/Target/TargetOptions.h"
     41 
     42 #define GET_REGINFO_TARGET_DESC
     43 #include "X86GenRegisterInfo.inc"
     44 
     45 using namespace llvm;
     46 
     47 cl::opt<bool>
     48 ForceStackAlign("force-align-stack",
     49                  cl::desc("Force align the stack to the minimum alignment"
     50                            " needed for the function."),
     51                  cl::init(false), cl::Hidden);
     52 
     53 static cl::opt<bool>
     54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
     55           cl::desc("Enable use of a base pointer for complex stack frames"));
     56 
     57 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm)
     58   : X86GenRegisterInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
     59                          ? X86::RIP : X86::EIP),
     60                        X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
     61                        X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true),
     62                        (tm.getSubtarget<X86Subtarget>().is64Bit()
     63                          ? X86::RIP : X86::EIP)),
     64                        TM(tm) {
     65   X86_MC::InitLLVM2SEHRegisterMapping(this);
     66 
     67   // Cache some information.
     68   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
     69   Is64Bit = Subtarget->is64Bit();
     70   IsWin64 = Subtarget->isTargetWin64();
     71 
     72   if (Is64Bit) {
     73     SlotSize = 8;
     74     StackPtr = X86::RSP;
     75     FramePtr = X86::RBP;
     76   } else {
     77     SlotSize = 4;
     78     StackPtr = X86::ESP;
     79     FramePtr = X86::EBP;
     80   }
     81   // Use a callee-saved register as the base pointer.  These registers must
     82   // not conflict with any ABI requirements.  For example, in 32-bit mode PIC
     83   // requires GOT in the EBX register before function calls via PLT GOT pointer.
     84   BasePtr = Is64Bit ? X86::RBX : X86::ESI;
     85 }
     86 
     87 /// getCompactUnwindRegNum - This function maps the register to the number for
     88 /// compact unwind encoding. Return -1 if the register isn't valid.
     89 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
     90   switch (getLLVMRegNum(RegNum, isEH)) {
     91   case X86::EBX: case X86::RBX: return 1;
     92   case X86::ECX: case X86::R12: return 2;
     93   case X86::EDX: case X86::R13: return 3;
     94   case X86::EDI: case X86::R14: return 4;
     95   case X86::ESI: case X86::R15: return 5;
     96   case X86::EBP: case X86::RBP: return 6;
     97   }
     98 
     99   return -1;
    100 }
    101 
    102 bool
    103 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
    104   // Only enable when post-RA scheduling is enabled and this is needed.
    105   return TM.getSubtargetImpl()->postRAScheduler();
    106 }
    107 
    108 int
    109 X86RegisterInfo::getSEHRegNum(unsigned i) const {
    110   return getEncodingValue(i);
    111 }
    112 
    113 const TargetRegisterClass *
    114 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
    115                                        unsigned Idx) const {
    116   // The sub_8bit sub-register index is more constrained in 32-bit mode.
    117   // It behaves just like the sub_8bit_hi index.
    118   if (!Is64Bit && Idx == X86::sub_8bit)
    119     Idx = X86::sub_8bit_hi;
    120 
    121   // Forward to TableGen's default version.
    122   return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
    123 }
    124 
    125 const TargetRegisterClass *
    126 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
    127                                           const TargetRegisterClass *B,
    128                                           unsigned SubIdx) const {
    129   // The sub_8bit sub-register index is more constrained in 32-bit mode.
    130   if (!Is64Bit && SubIdx == X86::sub_8bit) {
    131     A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
    132     if (!A)
    133       return 0;
    134   }
    135   return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
    136 }
    137 
    138 const TargetRegisterClass*
    139 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
    140   // Don't allow super-classes of GR8_NOREX.  This class is only used after
    141   // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
    142   // to the full GR8 register class in 64-bit mode, so we cannot allow the
    143   // reigster class inflation.
    144   //
    145   // The GR8_NOREX class is always used in a way that won't be constrained to a
    146   // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
    147   // full GR8 class.
    148   if (RC == &X86::GR8_NOREXRegClass)
    149     return RC;
    150 
    151   const TargetRegisterClass *Super = RC;
    152   TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
    153   do {
    154     switch (Super->getID()) {
    155     case X86::GR8RegClassID:
    156     case X86::GR16RegClassID:
    157     case X86::GR32RegClassID:
    158     case X86::GR64RegClassID:
    159     case X86::FR32RegClassID:
    160     case X86::FR64RegClassID:
    161     case X86::RFP32RegClassID:
    162     case X86::RFP64RegClassID:
    163     case X86::RFP80RegClassID:
    164     case X86::VR128RegClassID:
    165     case X86::VR256RegClassID:
    166       // Don't return a super-class that would shrink the spill size.
    167       // That can happen with the vector and float classes.
    168       if (Super->getSize() == RC->getSize())
    169         return Super;
    170     }
    171     Super = *I++;
    172   } while (Super);
    173   return RC;
    174 }
    175 
    176 const TargetRegisterClass *
    177 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
    178                                                                          const {
    179   const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
    180   switch (Kind) {
    181   default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
    182   case 0: // Normal GPRs.
    183     if (Subtarget.isTarget64BitLP64())
    184       return &X86::GR64RegClass;
    185     return &X86::GR32RegClass;
    186   case 1: // Normal GPRs except the stack pointer (for encoding reasons).
    187     if (Subtarget.isTarget64BitLP64())
    188       return &X86::GR64_NOSPRegClass;
    189     return &X86::GR32_NOSPRegClass;
    190   case 2: // Available for tailcall (not callee-saved GPRs).
    191     if (Subtarget.isTargetWin64())
    192       return &X86::GR64_TCW64RegClass;
    193     else if (Subtarget.is64Bit())
    194       return &X86::GR64_TCRegClass;
    195 
    196     const Function *F = MF.getFunction();
    197     bool hasHipeCC = (F ? F->getCallingConv() == CallingConv::HiPE : false);
    198     if (hasHipeCC)
    199       return &X86::GR32RegClass;
    200     return &X86::GR32_TCRegClass;
    201   }
    202 }
    203 
    204 const TargetRegisterClass *
    205 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
    206   if (RC == &X86::CCRRegClass) {
    207     if (Is64Bit)
    208       return &X86::GR64RegClass;
    209     else
    210       return &X86::GR32RegClass;
    211   }
    212   return RC;
    213 }
    214 
    215 unsigned
    216 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
    217                                      MachineFunction &MF) const {
    218   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    219 
    220   unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
    221   switch (RC->getID()) {
    222   default:
    223     return 0;
    224   case X86::GR32RegClassID:
    225     return 4 - FPDiff;
    226   case X86::GR64RegClassID:
    227     return 12 - FPDiff;
    228   case X86::VR128RegClassID:
    229     return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
    230   case X86::VR64RegClassID:
    231     return 4;
    232   }
    233 }
    234 
    235 const uint16_t *
    236 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
    237   switch (MF->getFunction()->getCallingConv()) {
    238   case CallingConv::GHC:
    239   case CallingConv::HiPE:
    240     return CSR_NoRegs_SaveList;
    241 
    242   case CallingConv::Intel_OCL_BI: {
    243     bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
    244     bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
    245     if (HasAVX512 && IsWin64)
    246       return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
    247     if (HasAVX512 && Is64Bit)
    248       return CSR_64_Intel_OCL_BI_AVX512_SaveList;
    249     if (HasAVX && IsWin64)
    250       return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
    251     if (HasAVX && Is64Bit)
    252       return CSR_64_Intel_OCL_BI_AVX_SaveList;
    253     if (!HasAVX && !IsWin64 && Is64Bit)
    254       return CSR_64_Intel_OCL_BI_SaveList;
    255     break;
    256   }
    257 
    258   case CallingConv::Cold:
    259     if (Is64Bit)
    260       return CSR_MostRegs_64_SaveList;
    261     break;
    262 
    263   default:
    264     break;
    265   }
    266 
    267   bool CallsEHReturn = MF->getMMI().callsEHReturn();
    268   if (Is64Bit) {
    269     if (IsWin64)
    270       return CSR_Win64_SaveList;
    271     if (CallsEHReturn)
    272       return CSR_64EHRet_SaveList;
    273     return CSR_64_SaveList;
    274   }
    275   if (CallsEHReturn)
    276     return CSR_32EHRet_SaveList;
    277   return CSR_32_SaveList;
    278 }
    279 
    280 const uint32_t*
    281 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
    282   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
    283   bool HasAVX512 = TM.getSubtarget<X86Subtarget>().hasAVX512();
    284 
    285   if (CC == CallingConv::Intel_OCL_BI) {
    286     if (IsWin64 && HasAVX512)
    287       return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
    288     if (Is64Bit && HasAVX512)
    289       return CSR_64_Intel_OCL_BI_AVX512_RegMask;
    290     if (IsWin64 && HasAVX)
    291       return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
    292     if (Is64Bit && HasAVX)
    293       return CSR_64_Intel_OCL_BI_AVX_RegMask;
    294     if (!HasAVX && !IsWin64 && Is64Bit)
    295       return CSR_64_Intel_OCL_BI_RegMask;
    296   }
    297   if (CC == CallingConv::GHC || CC == CallingConv::HiPE)
    298     return CSR_NoRegs_RegMask;
    299   if (!Is64Bit)
    300     return CSR_32_RegMask;
    301   if (CC == CallingConv::Cold)
    302     return CSR_MostRegs_64_RegMask;
    303   if (IsWin64)
    304     return CSR_Win64_RegMask;
    305   return CSR_64_RegMask;
    306 }
    307 
    308 const uint32_t*
    309 X86RegisterInfo::getNoPreservedMask() const {
    310   return CSR_NoRegs_RegMask;
    311 }
    312 
    313 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
    314   BitVector Reserved(getNumRegs());
    315   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    316 
    317   // Set the stack-pointer register and its aliases as reserved.
    318   for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
    319        ++I)
    320     Reserved.set(*I);
    321 
    322   // Set the instruction pointer register and its aliases as reserved.
    323   for (MCSubRegIterator I(X86::RIP, this, /*IncludeSelf=*/true); I.isValid();
    324        ++I)
    325     Reserved.set(*I);
    326 
    327   // Set the frame-pointer register and its aliases as reserved if needed.
    328   if (TFI->hasFP(MF)) {
    329     for (MCSubRegIterator I(X86::RBP, this, /*IncludeSelf=*/true); I.isValid();
    330          ++I)
    331       Reserved.set(*I);
    332   }
    333 
    334   // Set the base-pointer register and its aliases as reserved if needed.
    335   if (hasBasePointer(MF)) {
    336     CallingConv::ID CC = MF.getFunction()->getCallingConv();
    337     const uint32_t* RegMask = getCallPreservedMask(CC);
    338     if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
    339       report_fatal_error(
    340         "Stack realignment in presence of dynamic allocas is not supported with"
    341         "this calling convention.");
    342 
    343     for (MCSubRegIterator I(getBaseRegister(), this, /*IncludeSelf=*/true);
    344          I.isValid(); ++I)
    345       Reserved.set(*I);
    346   }
    347 
    348   // Mark the segment registers as reserved.
    349   Reserved.set(X86::CS);
    350   Reserved.set(X86::SS);
    351   Reserved.set(X86::DS);
    352   Reserved.set(X86::ES);
    353   Reserved.set(X86::FS);
    354   Reserved.set(X86::GS);
    355 
    356   // Mark the floating point stack registers as reserved.
    357   for (unsigned n = 0; n != 8; ++n)
    358     Reserved.set(X86::ST0 + n);
    359 
    360   // Reserve the registers that only exist in 64-bit mode.
    361   if (!Is64Bit) {
    362     // These 8-bit registers are part of the x86-64 extension even though their
    363     // super-registers are old 32-bits.
    364     Reserved.set(X86::SIL);
    365     Reserved.set(X86::DIL);
    366     Reserved.set(X86::BPL);
    367     Reserved.set(X86::SPL);
    368 
    369     for (unsigned n = 0; n != 8; ++n) {
    370       // R8, R9, ...
    371       for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
    372         Reserved.set(*AI);
    373 
    374       // XMM8, XMM9, ...
    375       for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
    376         Reserved.set(*AI);
    377     }
    378   }
    379   if (!Is64Bit || !TM.getSubtarget<X86Subtarget>().hasAVX512()) {
    380     for (unsigned n = 16; n != 32; ++n) {
    381       for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
    382         Reserved.set(*AI);
    383     }
    384   }
    385 
    386   return Reserved;
    387 }
    388 
    389 //===----------------------------------------------------------------------===//
    390 // Stack Frame Processing methods
    391 //===----------------------------------------------------------------------===//
    392 
    393 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
    394    const MachineFrameInfo *MFI = MF.getFrameInfo();
    395 
    396    if (!EnableBasePointer)
    397      return false;
    398 
    399    // When we need stack realignment and there are dynamic allocas, we can't
    400    // reference off of the stack pointer, so we reserve a base pointer.
    401    //
    402    // This is also true if the function contain MS-style inline assembly.  We
    403    // do this because if any stack changes occur in the inline assembly, e.g.,
    404    // "pusha", then any C local variable or C argument references in the
    405    // inline assembly will be wrong because the SP is not properly tracked.
    406    if ((needsStackRealignment(MF) && MFI->hasVarSizedObjects()) ||
    407        MF.hasMSInlineAsm())
    408      return true;
    409 
    410    return false;
    411 }
    412 
    413 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
    414   if (MF.getFunction()->hasFnAttribute("no-realign-stack"))
    415     return false;
    416 
    417   const MachineFrameInfo *MFI = MF.getFrameInfo();
    418   const MachineRegisterInfo *MRI = &MF.getRegInfo();
    419 
    420   // Stack realignment requires a frame pointer.  If we already started
    421   // register allocation with frame pointer elimination, it is too late now.
    422   if (!MRI->canReserveReg(FramePtr))
    423     return false;
    424 
    425   // If a base pointer is necessary.  Check that it isn't too late to reserve
    426   // it.
    427   if (MFI->hasVarSizedObjects())
    428     return MRI->canReserveReg(BasePtr);
    429   return true;
    430 }
    431 
    432 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
    433   const MachineFrameInfo *MFI = MF.getFrameInfo();
    434   const Function *F = MF.getFunction();
    435   unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
    436   bool requiresRealignment =
    437     ((MFI->getMaxAlignment() > StackAlign) ||
    438      F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
    439                                      Attribute::StackAlignment));
    440 
    441   // If we've requested that we force align the stack do so now.
    442   if (ForceStackAlign)
    443     return canRealignStack(MF);
    444 
    445   return requiresRealignment && canRealignStack(MF);
    446 }
    447 
    448 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
    449                                            unsigned Reg, int &FrameIdx) const {
    450   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    451 
    452   if (Reg == FramePtr && TFI->hasFP(MF)) {
    453     FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
    454     return true;
    455   }
    456   return false;
    457 }
    458 
    459 void
    460 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
    461                                      int SPAdj, unsigned FIOperandNum,
    462                                      RegScavenger *RS) const {
    463   assert(SPAdj == 0 && "Unexpected");
    464 
    465   MachineInstr &MI = *II;
    466   MachineFunction &MF = *MI.getParent()->getParent();
    467   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    468   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
    469   unsigned BasePtr;
    470 
    471   unsigned Opc = MI.getOpcode();
    472   bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
    473   if (hasBasePointer(MF))
    474     BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
    475   else if (needsStackRealignment(MF))
    476     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
    477   else if (AfterFPPop)
    478     BasePtr = StackPtr;
    479   else
    480     BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
    481 
    482   // This must be part of a four operand memory reference.  Replace the
    483   // FrameIndex with base register with EBP.  Add an offset to the offset.
    484   MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
    485 
    486   // Now add the frame object offset to the offset from EBP.
    487   int FIOffset;
    488   if (AfterFPPop) {
    489     // Tail call jmp happens after FP is popped.
    490     const MachineFrameInfo *MFI = MF.getFrameInfo();
    491     FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
    492   } else
    493     FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
    494 
    495   if (MI.getOperand(FIOperandNum+3).isImm()) {
    496     // Offset is a 32-bit integer.
    497     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
    498     int Offset = FIOffset + Imm;
    499     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
    500            "Requesting 64-bit offset in 32-bit immediate!");
    501     MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
    502   } else {
    503     // Offset is symbolic. This is extremely rare.
    504     uint64_t Offset = FIOffset +
    505       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
    506     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
    507   }
    508 }
    509 
    510 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    511   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
    512   return TFI->hasFP(MF) ? FramePtr : StackPtr;
    513 }
    514 
    515 unsigned X86RegisterInfo::getEHExceptionRegister() const {
    516   llvm_unreachable("What is the exception register");
    517 }
    518 
    519 unsigned X86RegisterInfo::getEHHandlerRegister() const {
    520   llvm_unreachable("What is the exception handler register");
    521 }
    522 
    523 namespace llvm {
    524 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
    525                                 bool High) {
    526   switch (VT) {
    527   default: llvm_unreachable("Unexpected VT");
    528   case MVT::i8:
    529     if (High) {
    530       switch (Reg) {
    531       default: return getX86SubSuperRegister(Reg, MVT::i64);
    532       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
    533         return X86::SI;
    534       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
    535         return X86::DI;
    536       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
    537         return X86::BP;
    538       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
    539         return X86::SP;
    540       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
    541         return X86::AH;
    542       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
    543         return X86::DH;
    544       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
    545         return X86::CH;
    546       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
    547         return X86::BH;
    548       }
    549     } else {
    550       switch (Reg) {
    551       default: llvm_unreachable("Unexpected register");
    552       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
    553         return X86::AL;
    554       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
    555         return X86::DL;
    556       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
    557         return X86::CL;
    558       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
    559         return X86::BL;
    560       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
    561         return X86::SIL;
    562       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
    563         return X86::DIL;
    564       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
    565         return X86::BPL;
    566       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
    567         return X86::SPL;
    568       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
    569         return X86::R8B;
    570       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
    571         return X86::R9B;
    572       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
    573         return X86::R10B;
    574       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
    575         return X86::R11B;
    576       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
    577         return X86::R12B;
    578       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
    579         return X86::R13B;
    580       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
    581         return X86::R14B;
    582       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
    583         return X86::R15B;
    584       }
    585     }
    586   case MVT::i16:
    587     switch (Reg) {
    588     default: llvm_unreachable("Unexpected register");
    589     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
    590       return X86::AX;
    591     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
    592       return X86::DX;
    593     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
    594       return X86::CX;
    595     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
    596       return X86::BX;
    597     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
    598       return X86::SI;
    599     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
    600       return X86::DI;
    601     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
    602       return X86::BP;
    603     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
    604       return X86::SP;
    605     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
    606       return X86::R8W;
    607     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
    608       return X86::R9W;
    609     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
    610       return X86::R10W;
    611     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
    612       return X86::R11W;
    613     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
    614       return X86::R12W;
    615     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
    616       return X86::R13W;
    617     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
    618       return X86::R14W;
    619     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
    620       return X86::R15W;
    621     }
    622   case MVT::i32:
    623     switch (Reg) {
    624     default: llvm_unreachable("Unexpected register");
    625     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
    626       return X86::EAX;
    627     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
    628       return X86::EDX;
    629     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
    630       return X86::ECX;
    631     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
    632       return X86::EBX;
    633     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
    634       return X86::ESI;
    635     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
    636       return X86::EDI;
    637     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
    638       return X86::EBP;
    639     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
    640       return X86::ESP;
    641     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
    642       return X86::R8D;
    643     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
    644       return X86::R9D;
    645     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
    646       return X86::R10D;
    647     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
    648       return X86::R11D;
    649     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
    650       return X86::R12D;
    651     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
    652       return X86::R13D;
    653     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
    654       return X86::R14D;
    655     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
    656       return X86::R15D;
    657     }
    658   case MVT::i64:
    659     switch (Reg) {
    660     default: llvm_unreachable("Unexpected register");
    661     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
    662       return X86::RAX;
    663     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
    664       return X86::RDX;
    665     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
    666       return X86::RCX;
    667     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
    668       return X86::RBX;
    669     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
    670       return X86::RSI;
    671     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
    672       return X86::RDI;
    673     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
    674       return X86::RBP;
    675     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
    676       return X86::RSP;
    677     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
    678       return X86::R8;
    679     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
    680       return X86::R9;
    681     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
    682       return X86::R10;
    683     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
    684       return X86::R11;
    685     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
    686       return X86::R12;
    687     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
    688       return X86::R13;
    689     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
    690       return X86::R14;
    691     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
    692       return X86::R15;
    693     }
    694   }
    695 }
    696 
    697 unsigned get512BitSuperRegister(unsigned Reg) {
    698   if (Reg >= X86::XMM0 && Reg <= X86::XMM31)
    699     return X86::ZMM0 + (Reg - X86::XMM0);
    700   if (Reg >= X86::YMM0 && Reg <= X86::YMM31)
    701     return X86::ZMM0 + (Reg - X86::YMM0);
    702   if (Reg >= X86::ZMM0 && Reg <= X86::ZMM31)
    703     return Reg;
    704   llvm_unreachable("Unexpected SIMD register");
    705 }
    706 
    707 }
    708