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      1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines an instruction selector for the SPARC target.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SparcTargetMachine.h"
     15 #include "llvm/CodeGen/SelectionDAGISel.h"
     16 #include "llvm/IR/Intrinsics.h"
     17 #include "llvm/Support/Compiler.h"
     18 #include "llvm/Support/Debug.h"
     19 #include "llvm/Support/ErrorHandling.h"
     20 #include "llvm/Support/raw_ostream.h"
     21 using namespace llvm;
     22 
     23 //===----------------------------------------------------------------------===//
     24 // Instruction Selector Implementation
     25 //===----------------------------------------------------------------------===//
     26 
     27 //===--------------------------------------------------------------------===//
     28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
     29 /// instructions for SelectionDAG operations.
     30 ///
     31 namespace {
     32 class SparcDAGToDAGISel : public SelectionDAGISel {
     33   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
     34   /// make the right decision when generating code for different targets.
     35   const SparcSubtarget &Subtarget;
     36   SparcTargetMachine &TM;
     37 public:
     38   explicit SparcDAGToDAGISel(SparcTargetMachine &tm)
     39     : SelectionDAGISel(tm),
     40       Subtarget(tm.getSubtarget<SparcSubtarget>()),
     41       TM(tm) {
     42   }
     43 
     44   SDNode *Select(SDNode *N);
     45 
     46   // Complex Pattern Selectors.
     47   bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
     48   bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
     49 
     50   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     51   /// inline asm expressions.
     52   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
     53                                             char ConstraintCode,
     54                                             std::vector<SDValue> &OutOps);
     55 
     56   virtual const char *getPassName() const {
     57     return "SPARC DAG->DAG Pattern Instruction Selection";
     58   }
     59 
     60   // Include the pieces autogenerated from the target description.
     61 #include "SparcGenDAGISel.inc"
     62 
     63 private:
     64   SDNode* getGlobalBaseReg();
     65 };
     66 }  // end anonymous namespace
     67 
     68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
     69   unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
     70   return CurDAG->getRegister(GlobalBaseReg,
     71                              getTargetLowering()->getPointerTy()).getNode();
     72 }
     73 
     74 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
     75                                      SDValue &Base, SDValue &Offset) {
     76   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
     77     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
     78                                        getTargetLowering()->getPointerTy());
     79     Offset = CurDAG->getTargetConstant(0, MVT::i32);
     80     return true;
     81   }
     82   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
     83       Addr.getOpcode() == ISD::TargetGlobalAddress)
     84     return false;  // direct calls.
     85 
     86   if (Addr.getOpcode() == ISD::ADD) {
     87     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
     88       if (isInt<13>(CN->getSExtValue())) {
     89         if (FrameIndexSDNode *FIN =
     90                 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
     91           // Constant offset from frame ref.
     92           Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
     93                                            getTargetLowering()->getPointerTy());
     94         } else {
     95           Base = Addr.getOperand(0);
     96         }
     97         Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
     98         return true;
     99       }
    100     }
    101     if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
    102       Base = Addr.getOperand(1);
    103       Offset = Addr.getOperand(0).getOperand(0);
    104       return true;
    105     }
    106     if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
    107       Base = Addr.getOperand(0);
    108       Offset = Addr.getOperand(1).getOperand(0);
    109       return true;
    110     }
    111   }
    112   Base = Addr;
    113   Offset = CurDAG->getTargetConstant(0, MVT::i32);
    114   return true;
    115 }
    116 
    117 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
    118   if (Addr.getOpcode() == ISD::FrameIndex) return false;
    119   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
    120       Addr.getOpcode() == ISD::TargetGlobalAddress)
    121     return false;  // direct calls.
    122 
    123   if (Addr.getOpcode() == ISD::ADD) {
    124     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
    125       if (isInt<13>(CN->getSExtValue()))
    126         return false;  // Let the reg+imm pattern catch this!
    127     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
    128         Addr.getOperand(1).getOpcode() == SPISD::Lo)
    129       return false;  // Let the reg+imm pattern catch this!
    130     R1 = Addr.getOperand(0);
    131     R2 = Addr.getOperand(1);
    132     return true;
    133   }
    134 
    135   R1 = Addr;
    136   R2 = CurDAG->getRegister(SP::G0, getTargetLowering()->getPointerTy());
    137   return true;
    138 }
    139 
    140 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
    141   SDLoc dl(N);
    142   if (N->isMachineOpcode())
    143     return NULL;   // Already selected.
    144 
    145   switch (N->getOpcode()) {
    146   default: break;
    147   case SPISD::GLOBAL_BASE_REG:
    148     return getGlobalBaseReg();
    149 
    150   case ISD::SDIV:
    151   case ISD::UDIV: {
    152     // sdivx / udivx handle 64-bit divides.
    153     if (N->getValueType(0) == MVT::i64)
    154       break;
    155     // FIXME: should use a custom expander to expose the SRA to the dag.
    156     SDValue DivLHS = N->getOperand(0);
    157     SDValue DivRHS = N->getOperand(1);
    158 
    159     // Set the Y register to the high-part.
    160     SDValue TopPart;
    161     if (N->getOpcode() == ISD::SDIV) {
    162       TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
    163                                    CurDAG->getTargetConstant(31, MVT::i32)), 0);
    164     } else {
    165       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
    166     }
    167     TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
    168                                      CurDAG->getRegister(SP::G0, MVT::i32)), 0);
    169 
    170     // FIXME: Handle div by immediate.
    171     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
    172     return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
    173                                 TopPart);
    174   }
    175   case ISD::MULHU:
    176   case ISD::MULHS: {
    177     // FIXME: Handle mul by immediate.
    178     SDValue MulLHS = N->getOperand(0);
    179     SDValue MulRHS = N->getOperand(1);
    180     unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
    181     SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
    182                                          MulLHS, MulRHS);
    183     // The high part is in the Y register.
    184     return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
    185   }
    186   }
    187 
    188   return SelectCode(N);
    189 }
    190 
    191 
    192 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
    193 /// inline asm expressions.
    194 bool
    195 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
    196                                                 char ConstraintCode,
    197                                                 std::vector<SDValue> &OutOps) {
    198   SDValue Op0, Op1;
    199   switch (ConstraintCode) {
    200   default: return true;
    201   case 'm':   // memory
    202    if (!SelectADDRrr(Op, Op0, Op1))
    203      SelectADDRri(Op, Op0, Op1);
    204    break;
    205   }
    206 
    207   OutOps.push_back(Op0);
    208   OutOps.push_back(Op1);
    209   return false;
    210 }
    211 
    212 /// createSparcISelDag - This pass converts a legalized DAG into a
    213 /// SPARC-specific DAG, ready for instruction scheduling.
    214 ///
    215 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
    216   return new SparcDAGToDAGISel(TM);
    217 }
    218