| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 36 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| SparcISelLowering.cpp | 785 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
793 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
800 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsJITInfo.cpp | 172 // addiu $t9, $t9, %lo(NewVal)
179 int Lo = (int)(NewVal & 0xffff);
182 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo;
219 int Lo = (int)(EmittedAddr & 0xffff);
222 // addiu $t9, $t9, %lo(EmittedAddr)
227 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
232 JCE.emitWordBE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
|
| Mips16ISelDAGToDAG.cpp | 47 SDNode *Lo = 0, *Hi = 0;
54 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
55 InFlag = SDValue(Lo, 1);
61 return std::make_pair(Lo, Hi);
207 // addiu $2, $2, %lo($CPI1_0)
211 // lwc1 $f0, %lo($CPI1_0)($2)
212 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
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| MipsLongBranch.cpp | 268 int64_t Lo = SignExtend64<16>(Offset & 0xffff);
278 // addiu $at, $at, %lo($tgt - $baltgt)
300 .addReg(Mips::AT).addImm(Lo);
321 // daddiu $at, $at, %lo($tgt - $baltgt)
356 .addReg(Mips::AT_64).addImm(Lo);
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| MipsSEFrameLowering.cpp | 155 // copy lo, $vr0
170 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
176 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
183 // copy $vr0, lo
200 unsigned Lo = RegInfo.getSubReg(Src, Mips::sub_lo);
204 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR0).addReg(Lo, SrcKill);
|
| MipsISelLowering.h | 44 // No relation with Mips Lo register
45 Lo,
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| MipsSEISelLowering.cpp | 164 // multHi/Lo: product of multiplication
165 // Lo0: initial value of Lo register
240 // multHi/Lo: product of multiplication
241 // Lo0: initial value of Lo register
574 SDValue Lo, Hi;
577 Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, Ty, Mult,
584 return HasLo ? Lo : Hi;
586 SDValue Vals[] = { Lo, Hi };
600 SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
604 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi)
[all...] |
| /external/chromium_org/third_party/jinja2/ |
| _stringdefs.py | [all...] |
| /external/llvm/include/llvm/Support/ |
| GCOV.h | 138 uint64_t Lo = readInt();
140 uint64_t Result = Lo | (Hi << 32);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 43 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 140 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
158 unsigned Lo = Imm & 0xFFFF;
168 else if (Lo) {
169 // Both Lo and Hi have nonzero bits.
176 .addReg(TmpReg).addImm(Lo);
224 unsigned TmpReg3, Hi, Lo;
232 if ((Lo = Remainder & 0xFFFF)) {
235 ResultReg).addReg(TmpReg3).addImm(Lo);
|
| PPCISelLowering.h | 65 /// Hi/Lo - These represent the high and low 16-bit parts of a global
70 Hi, Lo,
|
| PPCISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
30 // These routines assume that the Lo/Hi part is stored first in memory on
31 // little/big-endian machines, followed by the Hi/Lo part. This means that
32 // they cannot be used as is on vectors, for which Lo is always stored first.
34 SDValue &Lo, SDValue &Hi) {
36 GetExpandedOp(Op, Lo, Hi);
39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
53 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
[all...] |
| LegalizeDAG.cpp | 403 SDValue Lo = Val;
408 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
414 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
535 SDValue Lo, Hi;
537 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
552 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
562 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
683 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
685 if (TLI.isBigEndian()) std::swap(Lo, Hi)
[all...] |
| LegalizeVectorOps.cpp | 450 SDValue Lo, Hi, ShAmt;
454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
455 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
471 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
476 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
479 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT)
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 237 SDValue Lo, Hi;
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
243 std::swap(Lo, Hi);
248 JoinIntegers(Lo, Hi));
[all...] |
| LegalizeVectorTypes.cpp | 480 SDValue Lo, Hi;
496 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
498 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
499 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
500 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
501 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
502 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
503 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
504 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
505 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break
[all...] |
| /external/chromium_org/third_party/skia/src/core/ |
| SkMath.cpp | 82 uint32_t lo = C + (B << 16); local
83 int32_t hi = A + (B >> 16) + (lo < C);
86 hi = -hi - Sk32ToBool(lo);
87 lo = 0 - lo;
92 SkASSERT(((int32_t)lo >> 31) == hi);
94 return lo;
102 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
103 int roundBit = (lo >> (shift - 1)) & 1;
104 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit
[all...] |
| /external/skia/src/core/ |
| SkMath.cpp | 82 uint32_t lo = C + (B << 16); local
83 int32_t hi = A + (B >> 16) + (lo < C);
86 hi = -hi - Sk32ToBool(lo);
87 lo = 0 - lo;
92 SkASSERT(((int32_t)lo >> 31) == hi);
94 return lo;
102 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
103 int roundBit = (lo >> (shift - 1)) & 1;
104 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 526 SDValue Lo(Hi.getNode(), 1);
527 SDValue Ops[] = { Lo, Hi };
543 SDValue Lo(Hi.getNode(), 1);
544 SDValue Ops[] = { Lo, Hi };
640 SDValue Lo(Hi.getNode(), 1);
641 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
648 SDValue Lo(Hi.getNode(), 1);
649 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
659 SDValue Lo(Hi.getNode(), 1);
664 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi)
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_mips_isel.c | 349 // store hi,lo as Ity_I32's
1345 HReg hi, lo; local
[all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | 750 Expr *Lo = CS->getLHS();
752 if (Lo->isTypeDependent() || Lo->isValueDependent()) {
763 CheckConvertedConstantExpression(Lo, CondType, LoVal, CCEK_CaseValue);
768 Lo = ConvLo.take();
772 LoVal = Lo->EvaluateKnownConstInt(Context);
776 Lo = DefaultLvalueConversion(Lo).take();
777 Lo = ImpCastExprToType(Lo, CondType, CK_IntegralCast).take()
[all...] |
