1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Sparc uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef SPARC_ISELLOWERING_H 16 #define SPARC_ISELLOWERING_H 17 18 #include "Sparc.h" 19 #include "llvm/Target/TargetLowering.h" 20 21 namespace llvm { 22 class SparcSubtarget; 23 24 namespace SPISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 CMPICC, // Compare two GPR operands, set icc+xcc. 28 CMPFCC, // Compare two FP operands, set fcc. 29 BRICC, // Branch to dest on icc condition 30 BRXCC, // Branch to dest on xcc condition (64-bit only). 31 BRFCC, // Branch to dest on fcc condition 32 SELECT_ICC, // Select between two values using the current ICC flags. 33 SELECT_XCC, // Select between two values using the current XCC flags. 34 SELECT_FCC, // Select between two values using the current FCC flags. 35 36 Hi, Lo, // Hi/Lo operations, typically on a global address. 37 38 FTOI, // FP to Int within a FP register. 39 ITOF, // Int to FP within a FP register. 40 41 CALL, // A call instruction. 42 RET_FLAG, // Return with a flag operand. 43 GLOBAL_BASE_REG, // Global base reg for PIC 44 FLUSHW // FLUSH register windows to stack 45 }; 46 } 47 48 class SparcTargetLowering : public TargetLowering { 49 const SparcSubtarget *Subtarget; 50 public: 51 SparcTargetLowering(TargetMachine &TM); 52 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 53 54 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 55 /// in Mask are known to be either zero or one and return them in the 56 /// KnownZero/KnownOne bitsets. 57 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 58 APInt &KnownZero, 59 APInt &KnownOne, 60 const SelectionDAG &DAG, 61 unsigned Depth = 0) const; 62 63 virtual MachineBasicBlock * 64 EmitInstrWithCustomInserter(MachineInstr *MI, 65 MachineBasicBlock *MBB) const; 66 67 virtual const char *getTargetNodeName(unsigned Opcode) const; 68 69 ConstraintType getConstraintType(const std::string &Constraint) const; 70 std::pair<unsigned, const TargetRegisterClass*> 71 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; 72 73 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 74 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 75 76 virtual SDValue 77 LowerFormalArguments(SDValue Chain, 78 CallingConv::ID CallConv, 79 bool isVarArg, 80 const SmallVectorImpl<ISD::InputArg> &Ins, 81 SDLoc dl, SelectionDAG &DAG, 82 SmallVectorImpl<SDValue> &InVals) const; 83 SDValue LowerFormalArguments_32(SDValue Chain, 84 CallingConv::ID CallConv, 85 bool isVarArg, 86 const SmallVectorImpl<ISD::InputArg> &Ins, 87 SDLoc dl, SelectionDAG &DAG, 88 SmallVectorImpl<SDValue> &InVals) const; 89 SDValue LowerFormalArguments_64(SDValue Chain, 90 CallingConv::ID CallConv, 91 bool isVarArg, 92 const SmallVectorImpl<ISD::InputArg> &Ins, 93 SDLoc dl, SelectionDAG &DAG, 94 SmallVectorImpl<SDValue> &InVals) const; 95 96 virtual SDValue 97 LowerCall(TargetLowering::CallLoweringInfo &CLI, 98 SmallVectorImpl<SDValue> &InVals) const; 99 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 100 SmallVectorImpl<SDValue> &InVals) const; 101 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 102 SmallVectorImpl<SDValue> &InVals) const; 103 104 virtual SDValue 105 LowerReturn(SDValue Chain, 106 CallingConv::ID CallConv, bool isVarArg, 107 const SmallVectorImpl<ISD::OutputArg> &Outs, 108 const SmallVectorImpl<SDValue> &OutVals, 109 SDLoc dl, SelectionDAG &DAG) const; 110 SDValue LowerReturn_32(SDValue Chain, 111 CallingConv::ID CallConv, bool IsVarArg, 112 const SmallVectorImpl<ISD::OutputArg> &Outs, 113 const SmallVectorImpl<SDValue> &OutVals, 114 SDLoc DL, SelectionDAG &DAG) const; 115 SDValue LowerReturn_64(SDValue Chain, 116 CallingConv::ID CallConv, bool IsVarArg, 117 const SmallVectorImpl<ISD::OutputArg> &Outs, 118 const SmallVectorImpl<SDValue> &OutVals, 119 SDLoc DL, SelectionDAG &DAG) const; 120 121 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 122 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 123 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 124 125 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; 126 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 127 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 128 SelectionDAG &DAG) const; 129 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 130 }; 131 } // end namespace llvm 132 133 #endif // SPARC_ISELLOWERING_H 134
