1 // Copyright 2011 the V8 project authors. All rights reserved. 2 // Redistribution and use in source and binary forms, with or without 3 // modification, are permitted provided that the following conditions are 4 // met: 5 // 6 // * Redistributions of source code must retain the above copyright 7 // notice, this list of conditions and the following disclaimer. 8 // * Redistributions in binary form must reproduce the above 9 // copyright notice, this list of conditions and the following 10 // disclaimer in the documentation and/or other materials provided 11 // with the distribution. 12 // * Neither the name of Google Inc. nor the names of its 13 // contributors may be used to endorse or promote products derived 14 // from this software without specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 28 #ifndef V8_ARM_CONSTANTS_ARM_H_ 29 #define V8_ARM_CONSTANTS_ARM_H_ 30 31 // ARM EABI is required. 32 #if defined(__arm__) && !defined(__ARM_EABI__) 33 #error ARM EABI support is required. 34 #endif 35 36 namespace v8 { 37 namespace internal { 38 39 // Constant pool marker. 40 // Use UDF, the permanently undefined instruction. 41 const int kConstantPoolMarkerMask = 0xfff000f0; 42 const int kConstantPoolMarker = 0xe7f000f0; 43 const int kConstantPoolLengthMaxMask = 0xffff; 44 inline int EncodeConstantPoolLength(int length) { 45 ASSERT((length & kConstantPoolLengthMaxMask) == length); 46 return ((length & 0xfff0) << 4) | (length & 0xf); 47 } 48 inline int DecodeConstantPoolLength(int instr) { 49 ASSERT((instr & kConstantPoolMarkerMask) == kConstantPoolMarker); 50 return ((instr >> 4) & 0xfff0) | (instr & 0xf); 51 } 52 53 // Number of registers in normal ARM mode. 54 const int kNumRegisters = 16; 55 56 // VFP support. 57 const int kNumVFPSingleRegisters = 32; 58 const int kNumVFPDoubleRegisters = 32; 59 const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters; 60 61 // PC is register 15. 62 const int kPCRegister = 15; 63 const int kNoRegister = -1; 64 65 // ----------------------------------------------------------------------------- 66 // Conditions. 67 68 // Defines constants and accessor classes to assemble, disassemble and 69 // simulate ARM instructions. 70 // 71 // Section references in the code refer to the "ARM Architecture Reference 72 // Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) 73 // 74 // Constants for specific fields are defined in their respective named enums. 75 // General constants are in an anonymous enum in class Instr. 76 77 // Values for the condition field as defined in section A3.2 78 enum Condition { 79 kNoCondition = -1, 80 81 eq = 0 << 28, // Z set Equal. 82 ne = 1 << 28, // Z clear Not equal. 83 cs = 2 << 28, // C set Unsigned higher or same. 84 cc = 3 << 28, // C clear Unsigned lower. 85 mi = 4 << 28, // N set Negative. 86 pl = 5 << 28, // N clear Positive or zero. 87 vs = 6 << 28, // V set Overflow. 88 vc = 7 << 28, // V clear No overflow. 89 hi = 8 << 28, // C set, Z clear Unsigned higher. 90 ls = 9 << 28, // C clear or Z set Unsigned lower or same. 91 ge = 10 << 28, // N == V Greater or equal. 92 lt = 11 << 28, // N != V Less than. 93 gt = 12 << 28, // Z clear, N == V Greater than. 94 le = 13 << 28, // Z set or N != V Less then or equal 95 al = 14 << 28, // Always. 96 97 kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). 98 kNumberOfConditions = 16, 99 100 // Aliases. 101 hs = cs, // C set Unsigned higher or same. 102 lo = cc // C clear Unsigned lower. 103 }; 104 105 106 inline Condition NegateCondition(Condition cond) { 107 ASSERT(cond != al); 108 return static_cast<Condition>(cond ^ ne); 109 } 110 111 112 // Corresponds to transposing the operands of a comparison. 113 inline Condition ReverseCondition(Condition cond) { 114 switch (cond) { 115 case lo: 116 return hi; 117 case hi: 118 return lo; 119 case hs: 120 return ls; 121 case ls: 122 return hs; 123 case lt: 124 return gt; 125 case gt: 126 return lt; 127 case ge: 128 return le; 129 case le: 130 return ge; 131 default: 132 return cond; 133 }; 134 } 135 136 137 // ----------------------------------------------------------------------------- 138 // Instructions encoding. 139 140 // Instr is merely used by the Assembler to distinguish 32bit integers 141 // representing instructions from usual 32 bit values. 142 // Instruction objects are pointers to 32bit values, and provide methods to 143 // access the various ISA fields. 144 typedef int32_t Instr; 145 146 147 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 148 // as defined in section A3.4 149 enum Opcode { 150 AND = 0 << 21, // Logical AND. 151 EOR = 1 << 21, // Logical Exclusive OR. 152 SUB = 2 << 21, // Subtract. 153 RSB = 3 << 21, // Reverse Subtract. 154 ADD = 4 << 21, // Add. 155 ADC = 5 << 21, // Add with Carry. 156 SBC = 6 << 21, // Subtract with Carry. 157 RSC = 7 << 21, // Reverse Subtract with Carry. 158 TST = 8 << 21, // Test. 159 TEQ = 9 << 21, // Test Equivalence. 160 CMP = 10 << 21, // Compare. 161 CMN = 11 << 21, // Compare Negated. 162 ORR = 12 << 21, // Logical (inclusive) OR. 163 MOV = 13 << 21, // Move. 164 BIC = 14 << 21, // Bit Clear. 165 MVN = 15 << 21 // Move Not. 166 }; 167 168 169 // The bits for bit 7-4 for some type 0 miscellaneous instructions. 170 enum MiscInstructionsBits74 { 171 // With bits 22-21 01. 172 BX = 1 << 4, 173 BXJ = 2 << 4, 174 BLX = 3 << 4, 175 BKPT = 7 << 4, 176 177 // With bits 22-21 11. 178 CLZ = 1 << 4 179 }; 180 181 182 // Instruction encoding bits and masks. 183 enum { 184 H = 1 << 5, // Halfword (or byte). 185 S6 = 1 << 6, // Signed (or unsigned). 186 L = 1 << 20, // Load (or store). 187 S = 1 << 20, // Set condition code (or leave unchanged). 188 W = 1 << 21, // Writeback base register (or leave unchanged). 189 A = 1 << 21, // Accumulate in multiply instruction (or not). 190 B = 1 << 22, // Unsigned byte (or word). 191 N = 1 << 22, // Long (or short). 192 U = 1 << 23, // Positive (or negative) offset/index. 193 P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). 194 I = 1 << 25, // Immediate shifter operand (or not). 195 196 B4 = 1 << 4, 197 B5 = 1 << 5, 198 B6 = 1 << 6, 199 B7 = 1 << 7, 200 B8 = 1 << 8, 201 B9 = 1 << 9, 202 B12 = 1 << 12, 203 B16 = 1 << 16, 204 B18 = 1 << 18, 205 B19 = 1 << 19, 206 B20 = 1 << 20, 207 B21 = 1 << 21, 208 B22 = 1 << 22, 209 B23 = 1 << 23, 210 B24 = 1 << 24, 211 B25 = 1 << 25, 212 B26 = 1 << 26, 213 B27 = 1 << 27, 214 B28 = 1 << 28, 215 216 // Instruction bit masks. 217 kCondMask = 15 << 28, 218 kALUMask = 0x6f << 21, 219 kRdMask = 15 << 12, // In str instruction. 220 kCoprocessorMask = 15 << 8, 221 kOpCodeMask = 15 << 21, // In data-processing instructions. 222 kImm24Mask = (1 << 24) - 1, 223 kOff12Mask = (1 << 12) - 1, 224 kOff8Mask = (1 << 8) - 1 225 }; 226 227 228 // ----------------------------------------------------------------------------- 229 // Addressing modes and instruction variants. 230 231 // Condition code updating mode. 232 enum SBit { 233 SetCC = 1 << 20, // Set condition code. 234 LeaveCC = 0 << 20 // Leave condition code unchanged. 235 }; 236 237 238 // Status register selection. 239 enum SRegister { 240 CPSR = 0 << 22, 241 SPSR = 1 << 22 242 }; 243 244 245 // Shifter types for Data-processing operands as defined in section A5.1.2. 246 enum ShiftOp { 247 LSL = 0 << 5, // Logical shift left. 248 LSR = 1 << 5, // Logical shift right. 249 ASR = 2 << 5, // Arithmetic shift right. 250 ROR = 3 << 5, // Rotate right. 251 252 // RRX is encoded as ROR with shift_imm == 0. 253 // Use a special code to make the distinction. The RRX ShiftOp is only used 254 // as an argument, and will never actually be encoded. The Assembler will 255 // detect it and emit the correct ROR shift operand with shift_imm == 0. 256 RRX = -1, 257 kNumberOfShifts = 4 258 }; 259 260 261 // Status register fields. 262 enum SRegisterField { 263 CPSR_c = CPSR | 1 << 16, 264 CPSR_x = CPSR | 1 << 17, 265 CPSR_s = CPSR | 1 << 18, 266 CPSR_f = CPSR | 1 << 19, 267 SPSR_c = SPSR | 1 << 16, 268 SPSR_x = SPSR | 1 << 17, 269 SPSR_s = SPSR | 1 << 18, 270 SPSR_f = SPSR | 1 << 19 271 }; 272 273 // Status register field mask (or'ed SRegisterField enum values). 274 typedef uint32_t SRegisterFieldMask; 275 276 277 // Memory operand addressing mode. 278 enum AddrMode { 279 // Bit encoding P U W. 280 Offset = (8|4|0) << 21, // Offset (without writeback to base). 281 PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback. 282 PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback. 283 NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base). 284 NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback. 285 NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback. 286 }; 287 288 289 // Load/store multiple addressing mode. 290 enum BlockAddrMode { 291 // Bit encoding P U W . 292 da = (0|0|0) << 21, // Decrement after. 293 ia = (0|4|0) << 21, // Increment after. 294 db = (8|0|0) << 21, // Decrement before. 295 ib = (8|4|0) << 21, // Increment before. 296 da_w = (0|0|1) << 21, // Decrement after with writeback to base. 297 ia_w = (0|4|1) << 21, // Increment after with writeback to base. 298 db_w = (8|0|1) << 21, // Decrement before with writeback to base. 299 ib_w = (8|4|1) << 21, // Increment before with writeback to base. 300 301 // Alias modes for comparison when writeback does not matter. 302 da_x = (0|0|0) << 21, // Decrement after. 303 ia_x = (0|4|0) << 21, // Increment after. 304 db_x = (8|0|0) << 21, // Decrement before. 305 ib_x = (8|4|0) << 21, // Increment before. 306 307 kBlockAddrModeMask = (8|4|1) << 21 308 }; 309 310 311 // Coprocessor load/store operand size. 312 enum LFlag { 313 Long = 1 << 22, // Long load/store coprocessor. 314 Short = 0 << 22 // Short load/store coprocessor. 315 }; 316 317 318 // NEON data type 319 enum NeonDataType { 320 NeonS8 = 0x1, // U = 0, imm3 = 0b001 321 NeonS16 = 0x2, // U = 0, imm3 = 0b010 322 NeonS32 = 0x4, // U = 0, imm3 = 0b100 323 NeonU8 = 1 << 24 | 0x1, // U = 1, imm3 = 0b001 324 NeonU16 = 1 << 24 | 0x2, // U = 1, imm3 = 0b010 325 NeonU32 = 1 << 24 | 0x4, // U = 1, imm3 = 0b100 326 NeonDataTypeSizeMask = 0x7, 327 NeonDataTypeUMask = 1 << 24 328 }; 329 330 enum NeonListType { 331 nlt_1 = 0x7, 332 nlt_2 = 0xA, 333 nlt_3 = 0x6, 334 nlt_4 = 0x2 335 }; 336 337 enum NeonSize { 338 Neon8 = 0x0, 339 Neon16 = 0x1, 340 Neon32 = 0x2, 341 Neon64 = 0x4 342 }; 343 344 // ----------------------------------------------------------------------------- 345 // Supervisor Call (svc) specific support. 346 347 // Special Software Interrupt codes when used in the presence of the ARM 348 // simulator. 349 // svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for 350 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. 351 enum SoftwareInterruptCodes { 352 // transition to C code 353 kCallRtRedirected= 0x10, 354 // break point 355 kBreakpoint= 0x20, 356 // stop 357 kStopCode = 1 << 23 358 }; 359 const uint32_t kStopCodeMask = kStopCode - 1; 360 const uint32_t kMaxStopCode = kStopCode - 1; 361 const int32_t kDefaultStopCode = -1; 362 363 364 // Type of VFP register. Determines register encoding. 365 enum VFPRegPrecision { 366 kSinglePrecision = 0, 367 kDoublePrecision = 1 368 }; 369 370 371 // VFP FPSCR constants. 372 enum VFPConversionMode { 373 kFPSCRRounding = 0, 374 kDefaultRoundToZero = 1 375 }; 376 377 // This mask does not include the "inexact" or "input denormal" cumulative 378 // exceptions flags, because we usually don't want to check for it. 379 const uint32_t kVFPExceptionMask = 0xf; 380 const uint32_t kVFPInvalidOpExceptionBit = 1 << 0; 381 const uint32_t kVFPOverflowExceptionBit = 1 << 2; 382 const uint32_t kVFPUnderflowExceptionBit = 1 << 3; 383 const uint32_t kVFPInexactExceptionBit = 1 << 4; 384 const uint32_t kVFPFlushToZeroMask = 1 << 24; 385 const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25; 386 387 const uint32_t kVFPNConditionFlagBit = 1 << 31; 388 const uint32_t kVFPZConditionFlagBit = 1 << 30; 389 const uint32_t kVFPCConditionFlagBit = 1 << 29; 390 const uint32_t kVFPVConditionFlagBit = 1 << 28; 391 392 393 // VFP rounding modes. See ARM DDI 0406B Page A2-29. 394 enum VFPRoundingMode { 395 RN = 0 << 22, // Round to Nearest. 396 RP = 1 << 22, // Round towards Plus Infinity. 397 RM = 2 << 22, // Round towards Minus Infinity. 398 RZ = 3 << 22, // Round towards zero. 399 400 // Aliases. 401 kRoundToNearest = RN, 402 kRoundToPlusInf = RP, 403 kRoundToMinusInf = RM, 404 kRoundToZero = RZ 405 }; 406 407 const uint32_t kVFPRoundingModeMask = 3 << 22; 408 409 enum CheckForInexactConversion { 410 kCheckForInexactConversion, 411 kDontCheckForInexactConversion 412 }; 413 414 // ----------------------------------------------------------------------------- 415 // Hints. 416 417 // Branch hints are not used on the ARM. They are defined so that they can 418 // appear in shared function signatures, but will be ignored in ARM 419 // implementations. 420 enum Hint { no_hint }; 421 422 // Hints are not used on the arm. Negating is trivial. 423 inline Hint NegateHint(Hint ignored) { return no_hint; } 424 425 426 // ----------------------------------------------------------------------------- 427 // Specific instructions, constants, and masks. 428 // These constants are declared in assembler-arm.cc, as they use named registers 429 // and other constants. 430 431 432 // add(sp, sp, 4) instruction (aka Pop()) 433 extern const Instr kPopInstruction; 434 435 // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) 436 // register r is not encoded. 437 extern const Instr kPushRegPattern; 438 439 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) 440 // register r is not encoded. 441 extern const Instr kPopRegPattern; 442 443 // mov lr, pc 444 extern const Instr kMovLrPc; 445 // ldr rd, [pc, #offset] 446 extern const Instr kLdrPCMask; 447 extern const Instr kLdrPCPattern; 448 // vldr dd, [pc, #offset] 449 extern const Instr kVldrDPCMask; 450 extern const Instr kVldrDPCPattern; 451 // blxcc rm 452 extern const Instr kBlxRegMask; 453 454 extern const Instr kBlxRegPattern; 455 456 extern const Instr kMovMvnMask; 457 extern const Instr kMovMvnPattern; 458 extern const Instr kMovMvnFlip; 459 extern const Instr kMovLeaveCCMask; 460 extern const Instr kMovLeaveCCPattern; 461 extern const Instr kMovwMask; 462 extern const Instr kMovwPattern; 463 extern const Instr kMovwLeaveCCFlip; 464 extern const Instr kCmpCmnMask; 465 extern const Instr kCmpCmnPattern; 466 extern const Instr kCmpCmnFlip; 467 extern const Instr kAddSubFlip; 468 extern const Instr kAndBicFlip; 469 470 // A mask for the Rd register for push, pop, ldr, str instructions. 471 extern const Instr kLdrRegFpOffsetPattern; 472 473 extern const Instr kStrRegFpOffsetPattern; 474 475 extern const Instr kLdrRegFpNegOffsetPattern; 476 477 extern const Instr kStrRegFpNegOffsetPattern; 478 479 extern const Instr kLdrStrInstrTypeMask; 480 extern const Instr kLdrStrInstrArgumentMask; 481 extern const Instr kLdrStrOffsetMask; 482 483 484 // ----------------------------------------------------------------------------- 485 // Instruction abstraction. 486 487 // The class Instruction enables access to individual fields defined in the ARM 488 // architecture instruction set encoding as described in figure A3-1. 489 // Note that the Assembler uses typedef int32_t Instr. 490 // 491 // Example: Test whether the instruction at ptr does set the condition code 492 // bits. 493 // 494 // bool InstructionSetsConditionCodes(byte* ptr) { 495 // Instruction* instr = Instruction::At(ptr); 496 // int type = instr->TypeValue(); 497 // return ((type == 0) || (type == 1)) && instr->HasS(); 498 // } 499 // 500 class Instruction { 501 public: 502 enum { 503 kInstrSize = 4, 504 kInstrSizeLog2 = 2, 505 kPCReadOffset = 8 506 }; 507 508 // Helper macro to define static accessors. 509 // We use the cast to char* trick to bypass the strict anti-aliasing rules. 510 #define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ 511 static inline return_type Name(Instr instr) { \ 512 char* temp = reinterpret_cast<char*>(&instr); \ 513 return reinterpret_cast<Instruction*>(temp)->Name(); \ 514 } 515 516 #define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) 517 518 // Get the raw instruction bits. 519 inline Instr InstructionBits() const { 520 return *reinterpret_cast<const Instr*>(this); 521 } 522 523 // Set the raw instruction bits to value. 524 inline void SetInstructionBits(Instr value) { 525 *reinterpret_cast<Instr*>(this) = value; 526 } 527 528 // Read one particular bit out of the instruction bits. 529 inline int Bit(int nr) const { 530 return (InstructionBits() >> nr) & 1; 531 } 532 533 // Read a bit field's value out of the instruction bits. 534 inline int Bits(int hi, int lo) const { 535 return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); 536 } 537 538 // Read a bit field out of the instruction bits. 539 inline int BitField(int hi, int lo) const { 540 return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); 541 } 542 543 // Static support. 544 545 // Read one particular bit out of the instruction bits. 546 static inline int Bit(Instr instr, int nr) { 547 return (instr >> nr) & 1; 548 } 549 550 // Read the value of a bit field out of the instruction bits. 551 static inline int Bits(Instr instr, int hi, int lo) { 552 return (instr >> lo) & ((2 << (hi - lo)) - 1); 553 } 554 555 556 // Read a bit field out of the instruction bits. 557 static inline int BitField(Instr instr, int hi, int lo) { 558 return instr & (((2 << (hi - lo)) - 1) << lo); 559 } 560 561 562 // Accessors for the different named fields used in the ARM encoding. 563 // The naming of these accessor corresponds to figure A3-1. 564 // 565 // Two kind of accessors are declared: 566 // - <Name>Field() will return the raw field, i.e. the field's bits at their 567 // original place in the instruction encoding. 568 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 569 // 0xC0810002 ConditionField(instr) will return 0xC0000000. 570 // - <Name>Value() will return the field value, shifted back to bit 0. 571 // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as 572 // 0xC0810002 ConditionField(instr) will return 0xC. 573 574 575 // Generally applicable fields 576 inline Condition ConditionValue() const { 577 return static_cast<Condition>(Bits(31, 28)); 578 } 579 inline Condition ConditionField() const { 580 return static_cast<Condition>(BitField(31, 28)); 581 } 582 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); 583 DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); 584 585 inline int TypeValue() const { return Bits(27, 25); } 586 inline int SpecialValue() const { return Bits(27, 23); } 587 588 inline int RnValue() const { return Bits(19, 16); } 589 DECLARE_STATIC_ACCESSOR(RnValue); 590 inline int RdValue() const { return Bits(15, 12); } 591 DECLARE_STATIC_ACCESSOR(RdValue); 592 593 inline int CoprocessorValue() const { return Bits(11, 8); } 594 // Support for VFP. 595 // Vn(19-16) | Vd(15-12) | Vm(3-0) 596 inline int VnValue() const { return Bits(19, 16); } 597 inline int VmValue() const { return Bits(3, 0); } 598 inline int VdValue() const { return Bits(15, 12); } 599 inline int NValue() const { return Bit(7); } 600 inline int MValue() const { return Bit(5); } 601 inline int DValue() const { return Bit(22); } 602 inline int RtValue() const { return Bits(15, 12); } 603 inline int PValue() const { return Bit(24); } 604 inline int UValue() const { return Bit(23); } 605 inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } 606 inline int Opc2Value() const { return Bits(19, 16); } 607 inline int Opc3Value() const { return Bits(7, 6); } 608 inline int SzValue() const { return Bit(8); } 609 inline int VLValue() const { return Bit(20); } 610 inline int VCValue() const { return Bit(8); } 611 inline int VAValue() const { return Bits(23, 21); } 612 inline int VBValue() const { return Bits(6, 5); } 613 inline int VFPNRegValue(VFPRegPrecision pre) { 614 return VFPGlueRegValue(pre, 16, 7); 615 } 616 inline int VFPMRegValue(VFPRegPrecision pre) { 617 return VFPGlueRegValue(pre, 0, 5); 618 } 619 inline int VFPDRegValue(VFPRegPrecision pre) { 620 return VFPGlueRegValue(pre, 12, 22); 621 } 622 623 // Fields used in Data processing instructions 624 inline int OpcodeValue() const { 625 return static_cast<Opcode>(Bits(24, 21)); 626 } 627 inline Opcode OpcodeField() const { 628 return static_cast<Opcode>(BitField(24, 21)); 629 } 630 inline int SValue() const { return Bit(20); } 631 // with register 632 inline int RmValue() const { return Bits(3, 0); } 633 DECLARE_STATIC_ACCESSOR(RmValue); 634 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } 635 inline ShiftOp ShiftField() const { 636 return static_cast<ShiftOp>(BitField(6, 5)); 637 } 638 inline int RegShiftValue() const { return Bit(4); } 639 inline int RsValue() const { return Bits(11, 8); } 640 inline int ShiftAmountValue() const { return Bits(11, 7); } 641 // with immediate 642 inline int RotateValue() const { return Bits(11, 8); } 643 inline int Immed8Value() const { return Bits(7, 0); } 644 inline int Immed4Value() const { return Bits(19, 16); } 645 inline int ImmedMovwMovtValue() const { 646 return Immed4Value() << 12 | Offset12Value(); } 647 648 // Fields used in Load/Store instructions 649 inline int PUValue() const { return Bits(24, 23); } 650 inline int PUField() const { return BitField(24, 23); } 651 inline int BValue() const { return Bit(22); } 652 inline int WValue() const { return Bit(21); } 653 inline int LValue() const { return Bit(20); } 654 // with register uses same fields as Data processing instructions above 655 // with immediate 656 inline int Offset12Value() const { return Bits(11, 0); } 657 // multiple 658 inline int RlistValue() const { return Bits(15, 0); } 659 // extra loads and stores 660 inline int SignValue() const { return Bit(6); } 661 inline int HValue() const { return Bit(5); } 662 inline int ImmedHValue() const { return Bits(11, 8); } 663 inline int ImmedLValue() const { return Bits(3, 0); } 664 665 // Fields used in Branch instructions 666 inline int LinkValue() const { return Bit(24); } 667 inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } 668 669 // Fields used in Software interrupt instructions 670 inline SoftwareInterruptCodes SvcValue() const { 671 return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); 672 } 673 674 // Test for special encodings of type 0 instructions (extra loads and stores, 675 // as well as multiplications). 676 inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } 677 678 // Test for miscellaneous instructions encodings of type 0 instructions. 679 inline bool IsMiscType0() const { return (Bit(24) == 1) 680 && (Bit(23) == 0) 681 && (Bit(20) == 0) 682 && ((Bit(7) == 0)); } 683 684 // Test for a nop instruction, which falls under type 1. 685 inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; } 686 687 // Test for a stop instruction. 688 inline bool IsStop() const { 689 return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); 690 } 691 692 // Special accessors that test for existence of a value. 693 inline bool HasS() const { return SValue() == 1; } 694 inline bool HasB() const { return BValue() == 1; } 695 inline bool HasW() const { return WValue() == 1; } 696 inline bool HasL() const { return LValue() == 1; } 697 inline bool HasU() const { return UValue() == 1; } 698 inline bool HasSign() const { return SignValue() == 1; } 699 inline bool HasH() const { return HValue() == 1; } 700 inline bool HasLink() const { return LinkValue() == 1; } 701 702 // Decoding the double immediate in the vmov instruction. 703 double DoubleImmedVmov() const; 704 705 // Instructions are read of out a code stream. The only way to get a 706 // reference to an instruction is to convert a pointer. There is no way 707 // to allocate or create instances of class Instruction. 708 // Use the At(pc) function to create references to Instruction. 709 static Instruction* At(byte* pc) { 710 return reinterpret_cast<Instruction*>(pc); 711 } 712 713 714 private: 715 // Join split register codes, depending on single or double precision. 716 // four_bit is the position of the least-significant bit of the four 717 // bit specifier. one_bit is the position of the additional single bit 718 // specifier. 719 inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { 720 if (pre == kSinglePrecision) { 721 return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); 722 } 723 return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); 724 } 725 726 // We need to prevent the creation of instances of class Instruction. 727 DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); 728 }; 729 730 731 // Helper functions for converting between register numbers and names. 732 class Registers { 733 public: 734 // Return the name of the register. 735 static const char* Name(int reg); 736 737 // Lookup the register number for the name provided. 738 static int Number(const char* name); 739 740 struct RegisterAlias { 741 int reg; 742 const char* name; 743 }; 744 745 private: 746 static const char* names_[kNumRegisters]; 747 static const RegisterAlias aliases_[]; 748 }; 749 750 // Helper functions for converting between VFP register numbers and names. 751 class VFPRegisters { 752 public: 753 // Return the name of the register. 754 static const char* Name(int reg, bool is_double); 755 756 // Lookup the register number for the name provided. 757 // Set flag pointed by is_double to true if register 758 // is double-precision. 759 static int Number(const char* name, bool* is_double); 760 761 private: 762 static const char* names_[kNumVFPRegisters]; 763 }; 764 765 766 } } // namespace v8::internal 767 768 #endif // V8_ARM_CONSTANTS_ARM_H_ 769
