1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI implementation of the TargetRegisterInfo class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 #include "SIRegisterInfo.h" 17 #include "AMDGPUTargetMachine.h" 18 19 using namespace llvm; 20 21 SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm) 22 : AMDGPURegisterInfo(tm), 23 TM(tm) 24 { } 25 26 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 27 BitVector Reserved(getNumRegs()); 28 return Reserved; 29 } 30 31 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 32 MachineFunction &MF) const { 33 return RC->getNumRegs(); 34 } 35 36 const TargetRegisterClass * 37 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const { 38 switch (rc->getID()) { 39 case AMDGPU::GPRF32RegClassID: 40 return &AMDGPU::VReg_32RegClass; 41 default: return rc; 42 } 43 } 44 45 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( 46 MVT VT) const { 47 switch(VT.SimpleTy) { 48 default: 49 case MVT::i32: return &AMDGPU::VReg_32RegClass; 50 } 51 } 52 53 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { 54 assert(!TargetRegisterInfo::isVirtualRegister(Reg)); 55 56 const TargetRegisterClass *BaseClasses[] = { 57 &AMDGPU::VReg_32RegClass, 58 &AMDGPU::SReg_32RegClass, 59 &AMDGPU::VReg_64RegClass, 60 &AMDGPU::SReg_64RegClass, 61 &AMDGPU::SReg_128RegClass, 62 &AMDGPU::SReg_256RegClass 63 }; 64 65 for (unsigned i = 0, e = sizeof(BaseClasses) / 66 sizeof(const TargetRegisterClass*); i != e; ++i) { 67 if (BaseClasses[i]->contains(Reg)) { 68 return BaseClasses[i]; 69 } 70 } 71 return NULL; 72 } 73
