| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 68 /// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
69 DBG_VALUE = 11,
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| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 215 case TargetOpcode::DBG_VALUE:
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| LiveDebugVariables.cpp | 12 // Remove all DBG_VALUE instructions referencing virtual registers and replace
17 // are moved between registers and stack slots. Finally emit new DBG_VALUE
99 /// A DBG_VALUE instruction notes that (a sub-register of) a virtual register
128 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo.
212 // A later DBG_VALUE at the same SlotIndex overrides the old location.
260 /// emitDebugValues - Recreate DBG_VALUE instruction from data structures.
264 /// findDebugLoc - Return DebugLoc used for this DBG_VALUE instruction. A
265 /// variable may have more than one corresponding DBG_VALUE instructions.
310 /// handleDebugValue - Add DBG_VALUE instruction to our maps.
311 /// @param MI DBG_VALUE instructio
[all...] |
| RegAllocFast.cpp | 293 // If this register is used by DBG_VALUE then insert new DBG_VALUE to
312 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
317 // Now this register is spilled there is should not be any DBG_VALUE
854 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
858 // Modify DBG_VALUE now that the value is in a spill slot.
866 TII->get(TargetOpcode::DBG_VALUE))
[all...] |
| InlineSpiller.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 209 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||
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| /external/llvm/lib/Target/XCore/ |
| XCoreAsmPrinter.cpp | 261 case XCore::DBG_VALUE:
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| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 639 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
700 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 303 case TargetOpcode::DBG_VALUE:
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| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 489 case TargetOpcode::DBG_VALUE:
572 case TargetOpcode::DBG_VALUE:
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 636 assert(OpC != PPC::DBG_VALUE &&
841 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
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| PPCAsmPrinter.cpp | 331 case TargetOpcode::DBG_VALUE:
[all...] |
| PPCInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 654 TII.get(TargetOpcode::DBG_VALUE),
658 TII.get(TargetOpcode::DBG_VALUE)).addOperand(*Op).addImm(0)
666 case Intrinsic::dbg_value: {
667 // This form of DBG_VALUE is target-independent.
669 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
[all...] |
| InstrEmitter.cpp | 630 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
642 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
646 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
[all...] |
| SelectionDAGISel.cpp | 402 // Insert DBG_VALUE instructions for function arguments to the entry block.
429 TII.get(TargetOpcode::DBG_VALUE),
434 // that COPY instructions also need DBG_VALUE, if it is the only
450 TII.get(TargetOpcode::DBG_VALUE),
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 691 case TargetOpcode::DBG_VALUE:
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| X86FrameLowering.cpp | [all...] |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 563 case TargetOpcode::DBG_VALUE:
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 554 /// of DBG_VALUE, returning true if it was able to do so. A false return
720 case TargetOpcode::DBG_VALUE:
[all...] |
