1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains code to lower X86 MachineInstrs to their corresponding 11 // MCInst records. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "X86AsmPrinter.h" 16 #include "InstPrinter/X86ATTInstPrinter.h" 17 #include "X86COFFMachineModuleInfo.h" 18 #include "llvm/ADT/SmallString.h" 19 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 20 #include "llvm/IR/Type.h" 21 #include "llvm/MC/MCAsmInfo.h" 22 #include "llvm/MC/MCContext.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/MC/MCInst.h" 25 #include "llvm/MC/MCInstBuilder.h" 26 #include "llvm/MC/MCStreamer.h" 27 #include "llvm/MC/MCSymbol.h" 28 #include "llvm/Support/FormattedStream.h" 29 #include "llvm/Target/Mangler.h" 30 using namespace llvm; 31 32 namespace { 33 34 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst. 35 class X86MCInstLower { 36 MCContext &Ctx; 37 Mangler *Mang; 38 const MachineFunction &MF; 39 const TargetMachine &TM; 40 const MCAsmInfo &MAI; 41 X86AsmPrinter &AsmPrinter; 42 public: 43 X86MCInstLower(Mangler *mang, const MachineFunction &MF, 44 X86AsmPrinter &asmprinter); 45 46 void Lower(const MachineInstr *MI, MCInst &OutMI) const; 47 48 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const; 49 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; 50 51 private: 52 MachineModuleInfoMachO &getMachOMMI() const; 53 }; 54 55 } // end anonymous namespace 56 57 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf, 58 X86AsmPrinter &asmprinter) 59 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()), 60 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {} 61 62 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const { 63 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>(); 64 } 65 66 67 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol 68 /// operand to an MCSymbol. 69 MCSymbol *X86MCInstLower:: 70 GetSymbolFromOperand(const MachineOperand &MO) const { 71 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference"); 72 73 SmallString<128> Name; 74 75 if (MO.isGlobal()) { 76 const GlobalValue *GV = MO.getGlobal(); 77 bool isImplicitlyPrivate = false; 78 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB || 79 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY || 80 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE || 81 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE) 82 isImplicitlyPrivate = true; 83 84 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate); 85 } else if (MO.isSymbol()) { 86 Name += MAI.getGlobalPrefix(); 87 Name += MO.getSymbolName(); 88 } else if (MO.isMBB()) { 89 Name += MO.getMBB()->getSymbol()->getName(); 90 } 91 92 // If the target flags on the operand changes the name of the symbol, do that 93 // before we return the symbol. 94 switch (MO.getTargetFlags()) { 95 default: break; 96 case X86II::MO_DLLIMPORT: { 97 // Handle dllimport linkage. 98 const char *Prefix = "__imp_"; 99 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix)); 100 break; 101 } 102 case X86II::MO_DARWIN_NONLAZY: 103 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: { 104 Name += "$non_lazy_ptr"; 105 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 106 107 MachineModuleInfoImpl::StubValueTy &StubSym = 108 getMachOMMI().getGVStubEntry(Sym); 109 if (StubSym.getPointer() == 0) { 110 assert(MO.isGlobal() && "Extern symbol not handled yet"); 111 StubSym = 112 MachineModuleInfoImpl:: 113 StubValueTy(Mang->getSymbol(MO.getGlobal()), 114 !MO.getGlobal()->hasInternalLinkage()); 115 } 116 return Sym; 117 } 118 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: { 119 Name += "$non_lazy_ptr"; 120 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 121 MachineModuleInfoImpl::StubValueTy &StubSym = 122 getMachOMMI().getHiddenGVStubEntry(Sym); 123 if (StubSym.getPointer() == 0) { 124 assert(MO.isGlobal() && "Extern symbol not handled yet"); 125 StubSym = 126 MachineModuleInfoImpl:: 127 StubValueTy(Mang->getSymbol(MO.getGlobal()), 128 !MO.getGlobal()->hasInternalLinkage()); 129 } 130 return Sym; 131 } 132 case X86II::MO_DARWIN_STUB: { 133 Name += "$stub"; 134 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str()); 135 MachineModuleInfoImpl::StubValueTy &StubSym = 136 getMachOMMI().getFnStubEntry(Sym); 137 if (StubSym.getPointer()) 138 return Sym; 139 140 if (MO.isGlobal()) { 141 StubSym = 142 MachineModuleInfoImpl:: 143 StubValueTy(Mang->getSymbol(MO.getGlobal()), 144 !MO.getGlobal()->hasInternalLinkage()); 145 } else { 146 Name.erase(Name.end()-5, Name.end()); 147 StubSym = 148 MachineModuleInfoImpl:: 149 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false); 150 } 151 return Sym; 152 } 153 } 154 155 return Ctx.GetOrCreateSymbol(Name.str()); 156 } 157 158 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, 159 MCSymbol *Sym) const { 160 // FIXME: We would like an efficient form for this, so we don't have to do a 161 // lot of extra uniquing. 162 const MCExpr *Expr = 0; 163 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; 164 165 switch (MO.getTargetFlags()) { 166 default: llvm_unreachable("Unknown target flag on GV operand"); 167 case X86II::MO_NO_FLAG: // No flag. 168 // These affect the name of the symbol, not any suffix. 169 case X86II::MO_DARWIN_NONLAZY: 170 case X86II::MO_DLLIMPORT: 171 case X86II::MO_DARWIN_STUB: 172 break; 173 174 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; 175 case X86II::MO_TLVP_PIC_BASE: 176 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); 177 // Subtract the pic base. 178 Expr = MCBinaryExpr::CreateSub(Expr, 179 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), 180 Ctx), 181 Ctx); 182 break; 183 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break; 184 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; 185 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break; 186 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break; 187 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; 188 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; 189 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break; 190 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break; 191 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break; 192 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break; 193 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break; 194 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break; 195 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break; 196 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break; 197 case X86II::MO_PIC_BASE_OFFSET: 198 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: 199 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: 200 Expr = MCSymbolRefExpr::Create(Sym, Ctx); 201 // Subtract the pic base. 202 Expr = MCBinaryExpr::CreateSub(Expr, 203 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx), 204 Ctx); 205 if (MO.isJTI() && MAI.hasSetDirective()) { 206 // If .set directive is supported, use it to reduce the number of 207 // relocations the assembler will generate for differences between 208 // local labels. This is only safe when the symbols are in the same 209 // section so we are restricting it to jumptable references. 210 MCSymbol *Label = Ctx.CreateTempSymbol(); 211 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr); 212 Expr = MCSymbolRefExpr::Create(Label, Ctx); 213 } 214 break; 215 } 216 217 if (Expr == 0) 218 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx); 219 220 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset()) 221 Expr = MCBinaryExpr::CreateAdd(Expr, 222 MCConstantExpr::Create(MO.getOffset(), Ctx), 223 Ctx); 224 return MCOperand::CreateExpr(Expr); 225 } 226 227 228 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R 229 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { 230 OutMI.setOpcode(NewOpc); 231 OutMI.addOperand(OutMI.getOperand(0)); 232 OutMI.addOperand(OutMI.getOperand(0)); 233 } 234 235 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with 236 /// a short fixed-register form. 237 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { 238 unsigned ImmOp = Inst.getNumOperands() - 1; 239 assert(Inst.getOperand(0).isReg() && 240 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && 241 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 242 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 243 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 244 245 // Check whether the destination register can be fixed. 246 unsigned Reg = Inst.getOperand(0).getReg(); 247 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 248 return; 249 250 // If so, rewrite the instruction. 251 MCOperand Saved = Inst.getOperand(ImmOp); 252 Inst = MCInst(); 253 Inst.setOpcode(Opcode); 254 Inst.addOperand(Saved); 255 } 256 257 /// \brief If a movsx instruction has a shorter encoding for the used register 258 /// simplify the instruction to use it instead. 259 static void SimplifyMOVSX(MCInst &Inst) { 260 unsigned NewOpcode = 0; 261 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); 262 switch (Inst.getOpcode()) { 263 default: 264 llvm_unreachable("Unexpected instruction!"); 265 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw 266 if (Op0 == X86::AX && Op1 == X86::AL) 267 NewOpcode = X86::CBW; 268 break; 269 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl 270 if (Op0 == X86::EAX && Op1 == X86::AX) 271 NewOpcode = X86::CWDE; 272 break; 273 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq 274 if (Op0 == X86::RAX && Op1 == X86::EAX) 275 NewOpcode = X86::CDQE; 276 break; 277 } 278 279 if (NewOpcode != 0) { 280 Inst = MCInst(); 281 Inst.setOpcode(NewOpcode); 282 } 283 } 284 285 /// \brief Simplify things like MOV32rm to MOV32o32a. 286 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, 287 unsigned Opcode) { 288 // Don't make these simplifications in 64-bit mode; other assemblers don't 289 // perform them because they make the code larger. 290 if (Printer.getSubtarget().is64Bit()) 291 return; 292 293 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); 294 unsigned AddrBase = IsStore; 295 unsigned RegOp = IsStore ? 0 : 5; 296 unsigned AddrOp = AddrBase + 3; 297 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && 298 Inst.getOperand(AddrBase + 0).isReg() && // base 299 Inst.getOperand(AddrBase + 1).isImm() && // scale 300 Inst.getOperand(AddrBase + 2).isReg() && // index register 301 (Inst.getOperand(AddrOp).isExpr() || // address 302 Inst.getOperand(AddrOp).isImm())&& 303 Inst.getOperand(AddrBase + 4).isReg() && // segment 304 "Unexpected instruction!"); 305 306 // Check whether the destination register can be fixed. 307 unsigned Reg = Inst.getOperand(RegOp).getReg(); 308 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) 309 return; 310 311 // Check whether this is an absolute address. 312 // FIXME: We know TLVP symbol refs aren't, but there should be a better way 313 // to do this here. 314 bool Absolute = true; 315 if (Inst.getOperand(AddrOp).isExpr()) { 316 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); 317 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE)) 318 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) 319 Absolute = false; 320 } 321 322 if (Absolute && 323 (Inst.getOperand(AddrBase + 0).getReg() != 0 || 324 Inst.getOperand(AddrBase + 2).getReg() != 0 || 325 Inst.getOperand(AddrBase + 4).getReg() != 0 || 326 Inst.getOperand(AddrBase + 1).getImm() != 1)) 327 return; 328 329 // If so, rewrite the instruction. 330 MCOperand Saved = Inst.getOperand(AddrOp); 331 Inst = MCInst(); 332 Inst.setOpcode(Opcode); 333 Inst.addOperand(Saved); 334 } 335 336 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { 337 OutMI.setOpcode(MI->getOpcode()); 338 339 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 340 const MachineOperand &MO = MI->getOperand(i); 341 342 MCOperand MCOp; 343 switch (MO.getType()) { 344 default: 345 MI->dump(); 346 llvm_unreachable("unknown operand type"); 347 case MachineOperand::MO_Register: 348 // Ignore all implicit register operands. 349 if (MO.isImplicit()) continue; 350 MCOp = MCOperand::CreateReg(MO.getReg()); 351 break; 352 case MachineOperand::MO_Immediate: 353 MCOp = MCOperand::CreateImm(MO.getImm()); 354 break; 355 case MachineOperand::MO_MachineBasicBlock: 356 case MachineOperand::MO_GlobalAddress: 357 case MachineOperand::MO_ExternalSymbol: 358 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO)); 359 break; 360 case MachineOperand::MO_JumpTableIndex: 361 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex())); 362 break; 363 case MachineOperand::MO_ConstantPoolIndex: 364 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex())); 365 break; 366 case MachineOperand::MO_BlockAddress: 367 MCOp = LowerSymbolOperand(MO, 368 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); 369 break; 370 case MachineOperand::MO_RegisterMask: 371 // Ignore call clobbers. 372 continue; 373 } 374 375 OutMI.addOperand(MCOp); 376 } 377 378 // Handle a few special cases to eliminate operand modifiers. 379 ReSimplify: 380 switch (OutMI.getOpcode()) { 381 case X86::LEA64_32r: 382 case X86::LEA64r: 383 case X86::LEA16r: 384 case X86::LEA32r: 385 // LEA should have a segment register, but it must be empty. 386 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands && 387 "Unexpected # of LEA operands"); 388 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && 389 "LEA has segment specified!"); 390 break; 391 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break; 392 393 case X86::MOV32ri64: 394 OutMI.setOpcode(X86::MOV32ri); 395 break; 396 397 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B 398 // if one of the registers is extended, but other isn't. 399 case X86::VMOVAPDrr: 400 case X86::VMOVAPDYrr: 401 case X86::VMOVAPSrr: 402 case X86::VMOVAPSYrr: 403 case X86::VMOVDQArr: 404 case X86::VMOVDQAYrr: 405 case X86::VMOVDQUrr: 406 case X86::VMOVDQUYrr: 407 case X86::VMOVUPDrr: 408 case X86::VMOVUPDYrr: 409 case X86::VMOVUPSrr: 410 case X86::VMOVUPSYrr: { 411 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 412 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) { 413 unsigned NewOpc; 414 switch (OutMI.getOpcode()) { 415 default: llvm_unreachable("Invalid opcode"); 416 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; 417 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; 418 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; 419 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; 420 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; 421 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; 422 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; 423 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break; 424 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break; 425 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break; 426 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break; 427 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break; 428 } 429 OutMI.setOpcode(NewOpc); 430 } 431 break; 432 } 433 case X86::VMOVSDrr: 434 case X86::VMOVSSrr: { 435 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) && 436 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) { 437 unsigned NewOpc; 438 switch (OutMI.getOpcode()) { 439 default: llvm_unreachable("Invalid opcode"); 440 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break; 441 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break; 442 } 443 OutMI.setOpcode(NewOpc); 444 } 445 break; 446 } 447 448 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register 449 // inputs modeled as normal uses instead of implicit uses. As such, truncate 450 // off all but the first operand (the callee). FIXME: Change isel. 451 case X86::TAILJMPr64: 452 case X86::CALL64r: 453 case X86::CALL64pcrel32: { 454 unsigned Opcode = OutMI.getOpcode(); 455 MCOperand Saved = OutMI.getOperand(0); 456 OutMI = MCInst(); 457 OutMI.setOpcode(Opcode); 458 OutMI.addOperand(Saved); 459 break; 460 } 461 462 case X86::EH_RETURN: 463 case X86::EH_RETURN64: { 464 OutMI = MCInst(); 465 OutMI.setOpcode(X86::RET); 466 break; 467 } 468 469 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions. 470 case X86::TAILJMPr: 471 case X86::TAILJMPd: 472 case X86::TAILJMPd64: { 473 unsigned Opcode; 474 switch (OutMI.getOpcode()) { 475 default: llvm_unreachable("Invalid opcode"); 476 case X86::TAILJMPr: Opcode = X86::JMP32r; break; 477 case X86::TAILJMPd: 478 case X86::TAILJMPd64: Opcode = X86::JMP_1; break; 479 } 480 481 MCOperand Saved = OutMI.getOperand(0); 482 OutMI = MCInst(); 483 OutMI.setOpcode(Opcode); 484 OutMI.addOperand(Saved); 485 break; 486 } 487 488 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do 489 // this with an ugly goto in case the resultant OR uses EAX and needs the 490 // short form. 491 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; 492 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; 493 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; 494 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; 495 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; 496 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; 497 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; 498 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; 499 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; 500 501 // The assembler backend wants to see branches in their small form and relax 502 // them to their large form. The JIT can only handle the large form because 503 // it does not do relaxation. For now, translate the large form to the 504 // small one here. 505 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break; 506 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break; 507 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break; 508 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break; 509 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break; 510 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break; 511 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break; 512 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break; 513 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break; 514 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break; 515 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break; 516 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break; 517 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break; 518 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break; 519 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break; 520 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break; 521 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break; 522 523 // Atomic load and store require a separate pseudo-inst because Acquire 524 // implies mayStore and Release implies mayLoad; fix these to regular MOV 525 // instructions here 526 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify; 527 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify; 528 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify; 529 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify; 530 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify; 531 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify; 532 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify; 533 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify; 534 535 // We don't currently select the correct instruction form for instructions 536 // which have a short %eax, etc. form. Handle this by custom lowering, for 537 // now. 538 // 539 // Note, we are currently not handling the following instructions: 540 // MOV64ao8, MOV64o8a 541 // XCHG16ar, XCHG32ar, XCHG64ar 542 case X86::MOV8mr_NOREX: 543 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break; 544 case X86::MOV8rm_NOREX: 545 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break; 546 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break; 547 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break; 548 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break; 549 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break; 550 551 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break; 552 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break; 553 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break; 554 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break; 555 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break; 556 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break; 557 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break; 558 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break; 559 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break; 560 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break; 561 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break; 562 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break; 563 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break; 564 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break; 565 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break; 566 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break; 567 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break; 568 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break; 569 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break; 570 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break; 571 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break; 572 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break; 573 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break; 574 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break; 575 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break; 576 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break; 577 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break; 578 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break; 579 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break; 580 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break; 581 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break; 582 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break; 583 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break; 584 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break; 585 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break; 586 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break; 587 588 // Try to shrink some forms of movsx. 589 case X86::MOVSX16rr8: 590 case X86::MOVSX32rr16: 591 case X86::MOVSX64rr32: 592 SimplifyMOVSX(OutMI); 593 break; 594 595 case X86::MORESTACK_RET: 596 OutMI.setOpcode(X86::RET); 597 break; 598 599 case X86::MORESTACK_RET_RESTORE_R10: 600 OutMI.setOpcode(X86::MOV64rr); 601 OutMI.addOperand(MCOperand::CreateReg(X86::R10)); 602 OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); 603 604 AsmPrinter.OutStreamer.EmitInstruction(MCInstBuilder(X86::RET)); 605 break; 606 } 607 } 608 609 static void LowerTlsAddr(MCStreamer &OutStreamer, 610 X86MCInstLower &MCInstLowering, 611 const MachineInstr &MI) { 612 613 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 || 614 MI.getOpcode() == X86::TLS_base_addr64; 615 616 bool needsPadding = MI.getOpcode() == X86::TLS_addr64; 617 618 MCContext &context = OutStreamer.getContext(); 619 620 if (needsPadding) 621 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 622 623 MCSymbolRefExpr::VariantKind SRVK; 624 switch (MI.getOpcode()) { 625 case X86::TLS_addr32: 626 case X86::TLS_addr64: 627 SRVK = MCSymbolRefExpr::VK_TLSGD; 628 break; 629 case X86::TLS_base_addr32: 630 SRVK = MCSymbolRefExpr::VK_TLSLDM; 631 break; 632 case X86::TLS_base_addr64: 633 SRVK = MCSymbolRefExpr::VK_TLSLD; 634 break; 635 default: 636 llvm_unreachable("unexpected opcode"); 637 } 638 639 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)); 640 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context); 641 642 MCInst LEA; 643 if (is64Bits) { 644 LEA.setOpcode(X86::LEA64r); 645 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest 646 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base 647 LEA.addOperand(MCOperand::CreateImm(1)); // scale 648 LEA.addOperand(MCOperand::CreateReg(0)); // index 649 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 650 LEA.addOperand(MCOperand::CreateReg(0)); // seg 651 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) { 652 LEA.setOpcode(X86::LEA32r); 653 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 654 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base 655 LEA.addOperand(MCOperand::CreateImm(1)); // scale 656 LEA.addOperand(MCOperand::CreateReg(0)); // index 657 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 658 LEA.addOperand(MCOperand::CreateReg(0)); // seg 659 } else { 660 LEA.setOpcode(X86::LEA32r); 661 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 662 LEA.addOperand(MCOperand::CreateReg(0)); // base 663 LEA.addOperand(MCOperand::CreateImm(1)); // scale 664 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index 665 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp 666 LEA.addOperand(MCOperand::CreateReg(0)); // seg 667 } 668 OutStreamer.EmitInstruction(LEA); 669 670 if (needsPadding) { 671 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 672 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX)); 673 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX)); 674 } 675 676 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr"; 677 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name); 678 const MCSymbolRefExpr *tlsRef = 679 MCSymbolRefExpr::Create(tlsGetAddr, 680 MCSymbolRefExpr::VK_PLT, 681 context); 682 683 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32 684 : X86::CALLpcrel32) 685 .addExpr(tlsRef)); 686 } 687 688 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { 689 X86MCInstLower MCInstLowering(Mang, *MF, *this); 690 switch (MI->getOpcode()) { 691 case TargetOpcode::DBG_VALUE: 692 llvm_unreachable("Should be handled target independently"); 693 694 // Emit nothing here but a comment if we can. 695 case X86::Int_MemBarrier: 696 if (OutStreamer.hasRawTextSupport()) 697 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER")); 698 return; 699 700 701 case X86::EH_RETURN: 702 case X86::EH_RETURN64: { 703 // Lower these as normal, but add some comments. 704 unsigned Reg = MI->getOperand(0).getReg(); 705 OutStreamer.AddComment(StringRef("eh_return, addr: %") + 706 X86ATTInstPrinter::getRegisterName(Reg)); 707 break; 708 } 709 case X86::TAILJMPr: 710 case X86::TAILJMPd: 711 case X86::TAILJMPd64: 712 // Lower these as normal, but add some comments. 713 OutStreamer.AddComment("TAILCALL"); 714 break; 715 716 case X86::TLS_addr32: 717 case X86::TLS_addr64: 718 case X86::TLS_base_addr32: 719 case X86::TLS_base_addr64: 720 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI); 721 722 case X86::MOVPC32r: { 723 // This is a pseudo op for a two instruction sequence with a label, which 724 // looks like: 725 // call "L1$pb" 726 // "L1$pb": 727 // popl %esi 728 729 // Emit the call. 730 MCSymbol *PICBase = MF->getPICBaseSymbol(); 731 // FIXME: We would like an efficient form for this, so we don't have to do a 732 // lot of extra uniquing. 733 OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32) 734 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext))); 735 736 // Emit the label. 737 OutStreamer.EmitLabel(PICBase); 738 739 // popl $reg 740 OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r) 741 .addReg(MI->getOperand(0).getReg())); 742 return; 743 } 744 745 case X86::ADD32ri: { 746 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. 747 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) 748 break; 749 750 // Okay, we have something like: 751 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) 752 753 // For this, we want to print something like: 754 // MYGLOBAL + (. - PICBASE) 755 // However, we can't generate a ".", so just emit a new label here and refer 756 // to it. 757 MCSymbol *DotSym = OutContext.CreateTempSymbol(); 758 OutStreamer.EmitLabel(DotSym); 759 760 // Now that we have emitted the label, lower the complex operand expression. 761 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); 762 763 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); 764 const MCExpr *PICBase = 765 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext); 766 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext); 767 768 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), 769 DotExpr, OutContext); 770 771 OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri) 772 .addReg(MI->getOperand(0).getReg()) 773 .addReg(MI->getOperand(1).getReg()) 774 .addExpr(DotExpr)); 775 return; 776 } 777 } 778 779 MCInst TmpInst; 780 MCInstLowering.Lower(MI, TmpInst); 781 OutStreamer.EmitInstruction(TmpInst); 782 } 783
