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    Searched refs:IndexReg (Results 1 - 11 of 11) sorted by null

  /external/llvm/lib/Target/X86/
X86InstrBuilder.h 49 unsigned IndexReg;
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
72 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
X86AsmPrinter.cpp 273 const MachineOperand &IndexReg = MI->getOperand(Op+2);
283 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
299 assert(IndexReg.getReg() != X86::ESP &&
306 if (IndexReg.getReg()) {
333 const MachineOperand &IndexReg = MI->getOperand(Op+2);
351 if (IndexReg.getReg()) {
364 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
X86CodeEmitter.cpp 482 const MachineOperand &IndexReg = MI.getOperand(Op+2);
489 assert(IndexReg.getReg() == 0 && Is64BitMode &&
510 IndexReg.getReg() == 0 &&
548 assert(IndexReg.getReg() != X86::ESP &&
549 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
582 if (IndexReg.getReg())
583 IndexRegNo = getX86RegNum(IndexReg.getReg());
590 if (IndexReg.getReg())
591 IndexRegNo = getX86RegNum(IndexReg.getReg());
616 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg)
    [all...]
X86ISelDAGToDAG.cpp 60 SDValue IndexReg;
72 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
82 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
110 << "IndexReg ";
111 if (IndexReg.getNode() != 0)
112 IndexReg.getNode()->dump();
235 Index = AM.IndexReg;
736 AM.Base_Reg = AM.IndexReg;
748 AM.IndexReg.getNode() == 0 &&
807 AM.IndexReg = And
    [all...]
X86FastISel.cpp 421 unsigned IndexReg = AM.IndexReg;
458 if (IndexReg == 0 &&
463 IndexReg = getRegForGEPIndex(Op).first;
464 if (IndexReg == 0)
477 AM.IndexReg = IndexReg;
516 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
535 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
597 if (AM.IndexReg == 0)
    [all...]
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/X86/InstPrinter/
X86IntelInstPrinter.cpp 156 const MCOperand &IndexReg = MI->getOperand(Op+2);
174 if (IndexReg.getReg()) {
188 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
X86ATTInstPrinter.cpp 176 const MCOperand &IndexReg = MI->getOperand(Op+2);
190 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
197 if (IndexReg.getReg() || BaseReg.getReg()) {
202 if (IndexReg.getReg()) {
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 204 unsigned BaseReg, IndexReg, TmpReg, Scale;
213 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
218 unsigned getIndexReg() { return IndexReg; }
246 // If we already have a BaseReg, then assume this is the IndexReg with
251 assert (!IndexReg && "BaseReg/IndexReg already set!");
252 IndexReg = TmpReg;
282 // If we already have a BaseReg, then assume this is the IndexReg with
287 assert (!IndexReg && "BaseReg/IndexReg already set!")
    [all...]
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 222 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
226 (IndexReg.getReg() != 0 &&
227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
237 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
241 (IndexReg.getReg() != 0 &&
242 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
252 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
256 (IndexReg.getReg() != 0 &&
257 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
373 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg)
    [all...]
  /external/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp     [all...]

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