| /external/llvm/include/llvm/MC/ |
| MCSubtargetInfo.h | 110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
117 if (I->UseIdx < UseIdx)
119 if (I->UseIdx > UseIdx)
|
| MCInstrItineraries.h | 196 /// itinerary class UseClass, operand index UseIdx.
198 unsigned UseClass, unsigned UseIdx) const {
208 if ((FirstUseIdx + UseIdx) >= LastUseIdx)
212 Forwardings[FirstUseIdx + UseIdx];
219 unsigned UseClass, unsigned UseIdx) const {
227 int UseCycle = getOperandCycle(UseClass, UseIdx);
233 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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| MCSchedule.h | 79 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
82 unsigned UseIdx;
87 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
|
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 145 unsigned UseIdx = 0;
149 ++UseIdx;
151 return UseIdx;
203 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
204 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
|
| LiveRangeEdit.cpp | 76 /// OrigIdx are also available with the same value at UseIdx.
79 SlotIndex UseIdx) const {
81 UseIdx = UseIdx.getRegSlot(true);
102 if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
105 if (OVNI != li.getVNInfoAt(UseIdx))
112 SlotIndex UseIdx,
135 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
|
| TargetInstrInfo.cpp | 576 SDNode *UseNode, unsigned UseIdx) const {
587 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
661 const MachineInstr *UseMI, unsigned UseIdx) const {
664 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
694 /// UseIdx to compute min latency.
698 const MachineInstr *UseMI, unsigned UseIdx) const {
708 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
|
| SplitKit.h | 315 /// defFromParent - Define Reg from ParentVNI at UseIdx using either
319 SlotIndex UseIdx,
|
| InlineSpiller.cpp | 839 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
840 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
849 DEBUG(dbgs() << UseIdx << '\t' << *MI);
861 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
863 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
874 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
[all...] |
| MachineVerifier.cpp | [all...] |
| RegisterCoalescer.cpp | 631 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
632 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
683 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
684 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
703 SlotIndex DefIdx = UseIdx.getRegSlot();
[all...] |
| MachineInstr.cpp | [all...] |
| TwoAddressInstructionPass.cpp | 376 SlotIndex useIdx = LIS->getInstructionIndex(MI);
377 LiveInterval::const_iterator I = LI.find(useIdx);
379 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
[all...] |
| SplitKit.cpp | 432 SlotIndex UseIdx,
445 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 224 const MachineInstr *UseMI, unsigned UseIdx) const;
228 SDNode *UseNode, unsigned UseIdx) const;
256 unsigned UseIdx, unsigned UseAlign) const;
260 unsigned UseIdx, unsigned UseAlign) const;
265 unsigned UseIdx, unsigned UseAlign) const;
277 const MachineInstr *UseMI, unsigned UseIdx) const;
|
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 86 /// OrigIdx are also available with the same value at UseIdx.
88 SlotIndex UseIdx) const;
168 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
171 SlotIndex UseIdx,
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| MachineInstr.h | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 832 unsigned UseIdx;
833 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
834 if (UseMI->getOperand(UseIdx).isReg() &&
835 UseMI->getOperand(UseIdx).getReg() == Reg)
838 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
839 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
841 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
[all...] |
| /external/llvm/utils/TableGen/ |
| SubtargetEmitter.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 386 const MachineInstr *UseMI, unsigned UseIdx) const;
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | [all...] |
