| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 38 DestName = getRegName(MI->getOperand(0).getReg());
39 Src1Name = getRegName(MI->getOperand(1).getReg());
40 Src2Name = getRegName(MI->getOperand(2).getReg());
41 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
46 Src2Name = getRegName(MI->getOperand(2).getReg());
47 Src1Name = getRegName(MI->getOperand(1).getReg());
48 DestName = getRegName(MI->getOperand(0).getReg());
54 Src2Name = getRegName(MI->getOperand(2).getReg());
55 Src1Name = getRegName(MI->getOperand(1).getReg());
56 DestName = getRegName(MI->getOperand(0).getReg())
[all...] |
| /external/llvm/unittests/IR/ |
| MDBuilderTest.cpp | 38 Value *Op = MD1->getOperand(0);
52 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0)));
53 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1)));
54 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0));
55 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1));
66 EXPECT_EQ(R0->getOperand(0), R0);
67 EXPECT_EQ(R1->getOperand(0), R1);
68 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0);
69 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0);
77 EXPECT_TRUE(isa<MDString>(R0->getOperand(0)))
[all...] |
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
65 MI->getOperand(0).setReg(NewReg);
|
| /external/llvm/lib/IR/ |
| IntrinsicInst.cpp | 37 return CE->getOperand(0);
58 return MD->getOperand(0);
68 return cast<MDNode>(getArgOperand(0))->getOperand(0);
72 return cast<MDNode>(getArgOperand(0))->getOperand(0);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 97 int DestReg = MI->getOperand(0).getReg();
98 int SrcReg1 = MI->getOperand(2).getReg();
99 int SrcReg2 = MI->getOperand(3).getReg();
115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
127 int DestReg = MI->getOperand(0).getReg();
128 int SrcReg1 = MI->getOperand(2).getReg();
135 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
140 addReg(MI->getOperand(1).getReg()).
141 addImm(MI->getOperand(3).getImm())
[all...] |
| HexagonAsmPrinter.h | 71 int value = MI->getOperand(OpNo).getImm();
77 int value = MI->getOperand(OpNo).getImm();
83 const MachineOperand &MO1 = MI->getOperand(OpNo);
84 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
93 const MachineOperand &MO1 = MI->getOperand(OpNo);
94 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
105 if (MI->getOperand(OpNo).isImm()) {
106 O << "$+" << MI->getOperand(OpNo).getImm()*4;
108 printOp(MI->getOperand(OpNo), O);
122 if (MI->getOperand(OpNo).isImm())
[all...] |
| HexagonPeephole.cpp | 139 MachineOperand &Dst = MI->getOperand(0);
140 MachineOperand &Src = MI->getOperand(1);
158 MachineOperand &Dst = MI->getOperand(0);
159 MachineOperand &Src1 = MI->getOperand(1);
160 MachineOperand &Src2 = MI->getOperand(2);
175 MachineOperand &Dst = MI->getOperand(0);
176 MachineOperand &Src1 = MI->getOperand(1);
177 MachineOperand &Src2 = MI->getOperand(2);
190 MachineOperand &Dst = MI->getOperand(0);
191 MachineOperand &Src = MI->getOperand(1)
[all...] |
| HexagonNewValueJump.cpp | 150 if (II->getOperand(i).isReg() &&
151 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
154 unsigned Reg = II->getOperand(i).getReg();
229 int64_t v = MI->getOperand(2).getImm();
239 cmpReg1 = MI->getOperand(1).getReg();
242 cmpOp2 = MI->getOperand(2).getReg();
427 predReg = MI->getOperand(0).getReg();
432 // if(!jmpInstr->getOperand(0).isKill()) break;
456 jmpTarget = MI->getOperand(1).getMBB()
[all...] |
| HexagonRegisterInfo.cpp | 127 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
149 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
151 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
172 getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
173 MI.getOperand(0).getReg();
188 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
189 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
216 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
217 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
223 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
139 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
140 N->getOperand(2) };
145 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
146 N->getOperand(2) };
151 SDValue Ops[] = { N->getOperand(0), N->getOperand(1)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI->getOperand(1))
99 int64_t RegIndex = MI->getOperand(1).getImm();
102 .addOperand(MI->getOperand(0))
109 unsigned maskedRegister = MI->getOperand(0).getReg();
135 .addOperand(MI->getOperand(1)
[all...] |
| SIISelLowering.cpp | 83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI->getOperand(1))
98 .addOperand(MI->getOperand(0))
99 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(1))
103 .addOperand(MI->getOperand(1))
113 .addOperand(MI->getOperand(0))
114 .addOperand(MI->getOperand(1)
[all...] |
| AMDGPUISelLowering.cpp | 104 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
122 Op.getOperand(2), Op.getOperand(3));
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
125 Op.getOperand(2));
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI->getOperand(1))
99 int64_t RegIndex = MI->getOperand(1).getImm();
102 .addOperand(MI->getOperand(0))
109 unsigned maskedRegister = MI->getOperand(0).getReg();
135 .addOperand(MI->getOperand(1)
[all...] |
| SIISelLowering.cpp | 83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI->getOperand(1))
98 .addOperand(MI->getOperand(0))
99 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(1))
103 .addOperand(MI->getOperand(1))
113 .addOperand(MI->getOperand(0))
114 .addOperand(MI->getOperand(1)
[all...] |
| AMDGPUISelLowering.cpp | 104 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
122 Op.getOperand(2), Op.getOperand(3));
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
125 Op.getOperand(2));
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 40 isa<ConstantInt>(I->getOperand(2)))
46 (CheapToScalarize(BO->getOperand(0), isConstant) ||
47 CheapToScalarize(BO->getOperand(1), isConstant)))
51 (CheapToScalarize(CI->getOperand(0), isConstant) ||
52 CheapToScalarize(CI->getOperand(1), isConstant)))
73 if (!isa<ConstantInt>(III->getOperand(2)))
75 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue();
80 return III->getOperand(1);
84 return FindScalarElement(III->getOperand(0), EltNo);
88 unsigned LHSWidth = SVI->getOperand(0)->getType()->getVectorNumElements()
[all...] |
| InstCombineSelect.cpp | 32 LHS = ICI->getOperand(0);
33 RHS = ICI->getOperand(1);
36 if (SI->getTrueValue() == ICI->getOperand(0) &&
37 SI->getFalseValue() == ICI->getOperand(1)) {
52 if (SI->getTrueValue() == ICI->getOperand(1) &&
53 SI->getFalseValue() == ICI->getOperand(0)) {
130 Type *FIOpndTy = FI->getOperand(0)->getType();
131 if (TI->getOperand(0)->getType() != FIOpndTy)
144 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0),
145 FI->getOperand(0), SI.getName()+".v")
[all...] |
| InstCombineCasts.cpp | 43 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
48 return I->getOperand(0);
55 return I->getOperand(0);
63 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset);
118 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset);
186 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned);
187 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned);
197 if (I->getOperand(0)->getType() == Ty)
198 return I->getOperand(0);
202 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty
[all...] |
| /external/llvm/lib/Target/SystemZ/InstPrinter/ |
| SystemZInstPrinter.cpp | 56 int64_t Value = MI->getOperand(OpNum).getImm();
63 int64_t Value = MI->getOperand(OpNum).getImm();
70 int64_t Value = MI->getOperand(OpNum).getImm();
77 int64_t Value = MI->getOperand(OpNum).getImm();
84 int64_t Value = MI->getOperand(OpNum).getImm();
91 int64_t Value = MI->getOperand(OpNum).getImm();
98 int64_t Value = MI->getOperand(OpNum).getImm();
105 int64_t Value = MI->getOperand(OpNum).getImm();
112 uint64_t Value = MI->getOperand(OpNum).getImm();
119 const MCOperand &MO = MI->getOperand(OpNum)
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 81 switch (MI->getOperand(0).getImm()) {
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
155 MI->getOperand(0).getReg() == ARM::SP &&
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 87 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
90 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
95 Base = Addr.getOperand(0);
101 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
102 Base = Addr.getOperand(1);
103 Offset = Addr.getOperand(0).getOperand(0);
106 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
107 Base = Addr.getOperand(0);
108 Offset = Addr.getOperand(1).getOperand(0)
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 55 const MCOperand &MOImm = MI->getOperand(OpNum);
65 unsigned ExtImm = MI->getOperand(OpNum).getImm();
94 const MCOperand &Imm12Op = MI->getOperand(OpNum);
118 const MCOperand &MO = MI->getOperand(OpNum);
125 const MCOperand &ImmROp = MI->getOperand(OpNum);
133 const MCOperand &ImmSOp = MI->getOperand(OpNum);
142 const MCOperand &ImmSOp = MI->getOperand(OpNum);
143 const MCOperand &ImmROp = MI->getOperand(OpNum - 1);
156 const MCOperand &CRx = MI->getOperand(OpNum);
165 const MCOperand &ScaleOp = MI->getOperand(OpNum)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 112 MI->getOperand(0).isReg() &&
113 MI->getOperand(0).isDef() &&
114 MI->getOperand(0).getReg() == Reg &&
115 MI->getOperand(0).getSubReg() == SubReg)
131 if (MI->getOperand(1).getReg() == Reg &&
132 MI->getOperand(1).getSubReg() == SubReg)
143 const MachineOperand &MO = MI->getOperand(I);
177 if (MI->getOperand(2).getImm() != -1)
185 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
186 Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_NE
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
67 unsigned char SH = MI->getOperand(2).getImm();
68 unsigned char ME = MI->getOperand(3).getImm();
89 unsigned Code = MI->getOperand(OpNo).getImm();
179 int Value = MI->getOperand(OpNo).getImm();
186 unsigned int Value = MI->getOperand(OpNo).getImm()
[all...] |
