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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
  /external/mesa3d/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
  /external/llvm/lib/CodeGen/
TargetRegisterInfo.cpp 185 if (RCI.getSubReg() == Idx)
224 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
233 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
243 *BestPreA = IA.getSubReg();
244 *BestPreB = IB.getSubReg();
CalcSpillWeights.cpp 67 sub = mi->getOperand(0).getSubReg();
69 hsub = mi->getOperand(1).getSubReg();
71 sub = mi->getOperand(1).getSubReg();
73 hsub = mi->getOperand(0).getSubReg();
OptimizePHIs.cpp 106 !SrcMI->getOperand(0).getSubReg() &&
107 !SrcMI->getOperand(1).getSubReg() &&
TargetInstrInfo.cpp 138 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
139 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
140 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
316 if (FoldOp.getSubReg() || LiveOp.getSubReg())
451 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
VirtRegMap.cpp 293 if (MO.getSubReg()) {
315 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
RegisterCoalescer.cpp 221 DstSub = MI->getOperand(0).getSubReg();
223 SrcSub = MI->getOperand(1).getSubReg();
226 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
229 SrcSub = MI->getOperand(2).getSubReg();
277 Dst = TRI.getSubReg(Dst, DstSub);
372 Dst = TRI.getSubReg(Dst, DstSub);
377 return TRI.getSubReg(DstReg, SrcSub) == Dst;
698 UseMI->getOperand(0).getSubReg())
771 if (DstOperand.getSubReg() && !DstOperand.isUndef())
780 DefMI->getOperand(0).getSubReg());
    [all...]
ExpandPostRAPseudos.cpp 87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
RegAllocFast.cpp 666 if (!MO.getSubReg()) {
672 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
703 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
741 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
    [all...]
MachineInstr.cpp 72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
81 if (getSubReg()) {
82 Reg = TRI.getSubReg(Reg, getSubReg());
83 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
178 getSubReg() == Other.getSubReg();
217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
267 OS << PrintReg(getReg(), TRI, getSubReg());
    [all...]
  /external/llvm/lib/Target/R600/
R600ExpandSpecialInstrs.cpp 160 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
260 Src0 = TRI.getSubReg(Src0, SubRegIndex);
261 Src1 = TRI.getSubReg(Src1, SubRegIndex);
266 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
267 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
275 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
SIInstrInfo.cpp 161 get(Opcode), RI.getSubReg(DestReg, SubIdx));
163 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
  /external/llvm/lib/MC/
MCRegisterInfo.cpp 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
  /external/llvm/lib/Target/Hexagon/
HexagonSplitConst32AndConst64.cpp 138 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg);
140 QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg);
HexagonHardwareLoops.cpp 259 unsigned getSubReg() const {
761 SR = Start->getSubReg();
764 SR = End->getSubReg();
779 DistSR = End->getSubReg();
789 SubIB.addReg(End->getReg(), 0, End->getSubReg())
790 .addReg(Start->getReg(), 0, Start->getSubReg());
793 .addReg(Start->getReg(), 0, Start->getSubReg());
795 SubIB.addReg(End->getReg(), 0, End->getSubReg())
    [all...]
  /external/llvm/lib/Target/Mips/
MipsSEFrameLowering.cpp 170 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
171 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
200 unsigned Lo = RegInfo.getSubReg(Src, Mips::sub_lo);
201 unsigned Hi = RegInfo.getSubReg(Src, Mips::sub_hi);
238 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
239 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
240 unsigned SrcLo = RegInfo.getSubReg(Src, Mips::sub_lo);
241 unsigned SrcHi = RegInfo.getSubReg(Src, Mips::sub_hi);
324 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
326 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true)
    [all...]
MipsSEInstrInfo.cpp 417 TmpReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
420 DstReg = getRegisterInfo().getSubReg(DstReg, SubIdx);
436 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
451 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
453 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
489 unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpeven);
490 unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_fpodd);
  /external/llvm/lib/Target/ARM/
ARMExpandPseudoInsts.cpp 354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
355 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
356 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
357 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
360 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
361 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
362 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
366 D1 = TRI->getSubReg(Reg, ARM::dsub_3)
    [all...]
ARMMCInstLower.cpp 74 assert(!MO.getSubReg() && "Subregs should be eliminated!");
Thumb2ITBlockPass.cpp 113 assert(MI->getOperand(0).getSubReg() == 0 &&
114 MI->getOperand(1).getSubReg() == 0 &&
  /external/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 51 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
52 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
359 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
360 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
361 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
362 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
493 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
527 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
SystemZElimCompare.cpp 115 MI->getOperand(0).getSubReg() == SubReg)
132 MI->getOperand(1).getSubReg() == SubReg)
330 unsigned SrcSubReg = Compare->getOperand(0).getSubReg();
  /external/llvm/include/llvm/CodeGen/
MachineInstr.h 666 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
678 getOperand(0).getSubReg() == getOperand(1).getSubReg();
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64MCInstLower.cpp 106 assert(!MO.getSubReg() && "Subregs should be eliminated!");

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