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      1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // When the compiler is invoked with no small data, for instance, with the -G0
     11 // command line option, then all CONST32_* opcodes should be broken down into
     12 // appropriate LO and HI instructions. This splitting is done by this pass.
     13 // The only reason this is not done in the DAG lowering itself is that there
     14 // is no simple way of getting the register allocator to allot the same hard
     15 // register to the result of LO and HI instructions. This pass is always
     16 // scheduled after register allocation.
     17 //
     18 //===----------------------------------------------------------------------===//
     19 #define DEBUG_TYPE "xfer"
     20 #include "llvm/CodeGen/Passes.h"
     21 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
     22 #include "llvm/CodeGen/LatencyPriorityQueue.h"
     23 #include "llvm/CodeGen/SchedulerRegistry.h"
     24 #include "llvm/CodeGen/MachineDominators.h"
     25 #include "llvm/CodeGen/MachineFunctionPass.h"
     26 #include "llvm/CodeGen/MachineLoopInfo.h"
     27 #include "llvm/CodeGen/MachineRegisterInfo.h"
     28 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
     29 #include "llvm/Target/TargetMachine.h"
     30 #include "llvm/Target/TargetInstrInfo.h"
     31 #include "llvm/Target/TargetRegisterInfo.h"
     32 #include "llvm/Support/Compiler.h"
     33 #include "llvm/Support/Debug.h"
     34 #include "llvm/ADT/Statistic.h"
     35 #include "llvm/Support/MathExtras.h"
     36 #include "llvm/CodeGen/MachineInstrBuilder.h"
     37 #include "HexagonTargetMachine.h"
     38 #include "HexagonSubtarget.h"
     39 #include "HexagonMachineFunctionInfo.h"
     40 #include <map>
     41 #include <iostream>
     42 
     43 #include "llvm/Support/CommandLine.h"
     44 #define DEBUG_TYPE "xfer"
     45 
     46 
     47 using namespace llvm;
     48 
     49 namespace {
     50 
     51 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
     52     const HexagonTargetMachine& QTM;
     53     const HexagonSubtarget &QST;
     54 
     55  public:
     56     static char ID;
     57     HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM)
     58       : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
     59 
     60     const char *getPassName() const {
     61       return "Hexagon Split Const32s and Const64s";
     62     }
     63     bool runOnMachineFunction(MachineFunction &Fn);
     64 };
     65 
     66 
     67 char HexagonSplitConst32AndConst64::ID = 0;
     68 
     69 
     70 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
     71 
     72   const TargetInstrInfo *TII = QTM.getInstrInfo();
     73 
     74   // Loop over all of the basic blocks
     75   for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
     76        MBBb != MBBe; ++MBBb) {
     77     MachineBasicBlock* MBB = MBBb;
     78     // Traverse the basic block
     79     MachineBasicBlock::iterator MII = MBB->begin();
     80     MachineBasicBlock::iterator MIE = MBB->end ();
     81     while (MII != MIE) {
     82       MachineInstr *MI = MII;
     83       int Opc = MI->getOpcode();
     84       if (Opc == Hexagon::CONST32_set) {
     85         int DestReg = MI->getOperand(0).getReg();
     86         MachineOperand &Symbol = MI->getOperand (1);
     87 
     88         BuildMI (*MBB, MII, MI->getDebugLoc(),
     89                  TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
     90         BuildMI (*MBB, MII, MI->getDebugLoc(),
     91                  TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
     92         // MBB->erase returns the iterator to the next instruction, which is the
     93         // one we want to process next
     94         MII = MBB->erase (MI);
     95         continue;
     96       }
     97       else if (Opc == Hexagon::CONST32_set_jt) {
     98         int DestReg = MI->getOperand(0).getReg();
     99         MachineOperand &Symbol = MI->getOperand (1);
    100 
    101         BuildMI (*MBB, MII, MI->getDebugLoc(),
    102                  TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
    103         BuildMI (*MBB, MII, MI->getDebugLoc(),
    104                  TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
    105         // MBB->erase returns the iterator to the next instruction, which is the
    106         // one we want to process next
    107         MII = MBB->erase (MI);
    108         continue;
    109       }
    110       else if (Opc == Hexagon::CONST32_Label) {
    111         int DestReg = MI->getOperand(0).getReg();
    112         MachineOperand &Symbol = MI->getOperand (1);
    113 
    114         BuildMI (*MBB, MII, MI->getDebugLoc(),
    115                  TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
    116         BuildMI (*MBB, MII, MI->getDebugLoc(),
    117                  TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
    118         // MBB->erase returns the iterator to the next instruction, which is the
    119         // one we want to process next
    120         MII = MBB->erase (MI);
    121         continue;
    122       }
    123       else if (Opc == Hexagon::CONST32_Int_Real) {
    124         int DestReg = MI->getOperand(0).getReg();
    125         int64_t ImmValue = MI->getOperand(1).getImm ();
    126 
    127         BuildMI (*MBB, MII, MI->getDebugLoc(),
    128                  TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
    129         BuildMI (*MBB, MII, MI->getDebugLoc(),
    130                  TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
    131         MII = MBB->erase (MI);
    132         continue;
    133       }
    134       else if (Opc == Hexagon::CONST64_Int_Real) {
    135         int DestReg = MI->getOperand(0).getReg();
    136         int64_t ImmValue = MI->getOperand(1).getImm ();
    137         unsigned DestLo =
    138           QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_loreg);
    139         unsigned DestHi =
    140           QTM.getRegisterInfo()->getSubReg (DestReg, Hexagon::subreg_hireg);
    141 
    142         int32_t LowWord = (ImmValue & 0xFFFFFFFF);
    143         int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
    144 
    145         // Lower Registers Lower Half
    146         BuildMI (*MBB, MII, MI->getDebugLoc(),
    147                  TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
    148         // Lower Registers Higher Half
    149         BuildMI (*MBB, MII, MI->getDebugLoc(),
    150                  TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
    151         // Higher Registers Lower Half
    152         BuildMI (*MBB, MII, MI->getDebugLoc(),
    153                  TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
    154         // Higher Registers Higher Half.
    155         BuildMI (*MBB, MII, MI->getDebugLoc(),
    156                  TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
    157         MII = MBB->erase (MI);
    158         continue;
    159        }
    160       ++MII;
    161     }
    162   }
    163 
    164   return true;
    165 }
    166 
    167 }
    168 
    169 //===----------------------------------------------------------------------===//
    170 //                         Public Constructor Functions
    171 //===----------------------------------------------------------------------===//
    172 
    173 FunctionPass *
    174 llvm::createHexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) {
    175   return new HexagonSplitConst32AndConst64(TM);
    176 }
    177