| /art/compiler/dex/quick/arm/ |
| int_arm.cc | 97 OpRegRegReg(kOpSub, t_reg, rl_src1.low_reg, rl_src2.low_reg);
111 rl_temp.low_reg = t_reg;
129 int32_t low_reg = rl_src1.low_reg; local
146 NewLIR4(kThumb2OrrRRRs, t_reg, low_reg, high_reg, 0);
176 OpCmpImmBranch(ccode, low_reg, val_lo, taken);
207 OpRegRegImm(kOpRsub, rl_result.low_reg, rl_src.low_reg, 1);
209 LoadConstant(rl_result.low_reg, 0)
[all...] |
| fp_arm.cc | 66 NewLIR3(op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
114 NewLIR3(op, S2d(rl_result.low_reg, rl_result.high_reg), S2d(rl_src1.low_reg, rl_src1.high_reg),
115 S2d(rl_src2.low_reg, rl_src2.high_reg));
161 src_reg = S2d(rl_src.low_reg, rl_src.high_reg);
164 src_reg = rl_src.low_reg;
168 NewLIR2(op, S2d(rl_result.low_reg, rl_result.high_reg), src_reg);
172 NewLIR2(op, rl_result.low_reg, src_reg)
[all...] |
| target_arm.cc | 84 int ArmMir2Lir::S2d(int low_reg, int high_reg) {
85 return ARM_S2D(low_reg, high_reg);
515 int low_reg; local
519 low_reg = AllocTempDouble();
520 high_reg = low_reg + 1;
522 low_reg = AllocTemp();
525 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
573 if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &
[all...] |
| call_arm.cc | 45 loc.low_reg = rARM_ARG1 + arg_num;
46 loc.high_reg = loc.low_reg + 1;
53 loc.low_reg = rARM_ARG1 + arg_num;
70 loc.low_reg = AllocTemp();
71 LoadWordDisp(rARM_SP, start, loc.low_reg);
348 OpRegReg(kOpCmp, r_key, rl_src.low_reg);
384 keyReg = rl_src.low_reg;
387 OpRegRegImm(kOpSub, keyReg, rl_src.low_reg, low_key);
530 LoadWordDisp(rARM_SELF, ex_offset, rl_result.low_reg);
|
| codegen_arm.h | 52 int S2d(int low_reg, int high_reg);
|
| /art/compiler/dex/quick/ |
| gen_loadstore.cc | 95 OpRegCopy(r_dest, rl_src.low_reg);
125 OpRegCopyWide(reg_lo, reg_hi, rl_src.low_reg, rl_src.high_reg);
153 LoadValueDirect(rl_src, rl_src.low_reg);
155 MarkLive(rl_src.low_reg, rl_src.s_reg_low);
178 if (IsLive(rl_src.low_reg) ||
179 IsPromoted(rl_src.low_reg) ||
183 OpRegCopy(rl_dest.low_reg, rl_src.low_reg);
186 rl_dest.low_reg = rl_src.low_reg;
[all...] |
| gen_common.cc | 129 OpCmpImmBranch(cond, rl_src1.low_reg, mir_graph_->ConstantValue(rl_src2), taken);
135 OpCmpBranch(cond, rl_src1.low_reg, rl_src2.low_reg, taken);
166 OpCmpImmBranch(cond, rl_src.low_reg, 0, taken);
173 OpRegCopy(rl_result.low_reg, rl_src.low_reg);
175 LoadValueDirect(rl_src, rl_result.low_reg);
177 OpRegRegImm(kOpAsr, rl_result.high_reg, rl_result.low_reg, 31);
199 OpRegReg(op, rl_result.low_reg, rl_src.low_reg);
[all...] |
| ralloc_util.cc | 527 RegisterInfo* p = GetRegInfo(rl.low_reg);
541 RegisterInfo* p = GetRegInfo(rl.low_reg);
550 RegisterInfo* info_lo = GetRegInfo(rl.low_reg);
569 RegisterInfo* p = IsTemp(rl.low_reg);
574 ResetDef(rl.low_reg);
579 RegisterInfo* p_low = IsTemp(rl.low_reg);
588 ResetDef(rl.low_reg);
670 void Mir2Lir::MarkPair(int low_reg, int high_reg) {
671 RegisterInfo* info_lo = GetRegInfo(low_reg);
675 info_hi->partner = low_reg;
838 int low_reg; local
1070 int low_reg = promotion_map_[p_map_idx].FpReg; local
[all...] |
| gen_invoke.cc | 244 rl_src.low_reg = TargetReg(kArg0);
246 MarkLive(rl_src.low_reg, rl_src.s_reg_low);
302 int low_reg = promotion_map_[lowreg_index].FpReg; local
304 if (((low_reg & 0x1) != 0) || (high_reg != (low_reg + 1))) {
698 int low_reg; local
703 low_reg = rl_arg.low_reg;
706 low_reg = TargetReg(kArg2);
709 LoadValueDirectWideFixed(rl_arg, low_reg, high_reg)
718 StoreBaseDispWide(TargetReg(kSp), outs_offset, low_reg, high_reg); local
721 StoreWordDisp(TargetReg(kSp), outs_offset, low_reg); local
[all...] |
| mir_to_lir.cc | 141 LoadConstantNoClobber(rl_result.low_reg, vB);
144 Workaround7250540(rl_dest, rl_result.low_reg);
150 LoadConstantNoClobber(rl_result.low_reg, vB << 16);
153 Workaround7250540(rl_dest, rl_result.low_reg);
160 LoadConstantWide(rl_result.low_reg, rl_result.high_reg,
167 LoadConstantWide(rl_result.low_reg, rl_result.high_reg, mir->dalvikInsn.vB_wide);
173 LoadConstantWide(rl_result.low_reg, rl_result.high_reg,
206 GenNullCheck(rl_src[0].s_reg_low, rl_src[0].low_reg, opt_flags);
208 LoadWordDisp(rl_src[0].low_reg, len_offset, rl_result.low_reg);
[all...] |
| mir_to_lir.h | 359 void MarkPair(int low_reg, int high_reg);
551 virtual int S2d(int low_reg, int high_reg) = 0;
[all...] |
| /art/compiler/dex/quick/x86/ |
| fp_x86.cc | 66 int r_dest = rl_result.low_reg;
67 int r_src1 = rl_src1.low_reg;
68 int r_src2 = rl_src2.low_reg;
121 int r_dest = S2d(rl_result.low_reg, rl_result.high_reg);
122 int r_src1 = S2d(rl_src1.low_reg, rl_src1.high_reg);
123 int r_src2 = S2d(rl_src2.low_reg, rl_src2.high_reg);
158 src_reg = rl_src.low_reg;
164 LoadConstant(rl_result.low_reg, 0x7fffffff);
165 NewLIR2(kX86Cvtsi2ssRR, temp_reg, rl_result.low_reg);
169 NewLIR2(kX86Cvttss2siRR, rl_result.low_reg, src_reg)
[all...] |
| int_x86.cc | 227 OpRegReg(kOpCmp, rl_src1.low_reg, rl_src2.low_reg);
230 OpRegReg(kOpMov, rl_result.low_reg, rl_src1.low_reg);
233 OpRegReg(kOpMov, rl_result.low_reg, rl_src2.low_reg);
271 OpRegRegImm(kOpLsl, t_reg, rl_src.low_reg, second_bit - first_bit);
272 OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, t_reg);
275 OpRegRegImm(kOpLsl, rl_result.low_reg, rl_result.low_reg, first_bit)
[all...] |
| target_x86.cc | 94 int X86Mir2Lir::S2d(int low_reg, int high_reg) {
95 return X86_S2D(low_reg, high_reg);
360 CHECK(res.low_reg == rAX);
366 MarkPair(res.low_reg, res.high_reg);
372 res.low_reg = rDX;
412 int low_reg; local
416 low_reg = AllocTempDouble();
417 high_reg = low_reg + 1;
418 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
422 low_reg = AllocTemp()
[all...] |
| call_x86.cc | 48 OpCmpImmBranch(kCondEq, rl_src.low_reg, key,
95 keyReg = rl_src.low_reg;
98 OpRegRegImm(kOpSub, keyReg, rl_src.low_reg, low_key);
193 NewLIR2(kX86Mov32RT, rl_result.low_reg, ex_offset);
|
| codegen_x86.h | 53 int S2d(int low_reg, int high_reg);
|
| /art/compiler/dex/quick/mips/ |
| int_mips.cc | 52 NewLIR3(kMipsSubu, rl_result.low_reg, t1, t0);
53 LIR* branch = OpCmpImmBranch(kCondNe, rl_result.low_reg, 0, NULL);
54 NewLIR3(kMipsSltu, t0, rl_src1.low_reg, rl_src2.low_reg);
55 NewLIR3(kMipsSltu, t1, rl_src2.low_reg, rl_src1.low_reg);
56 NewLIR3(kMipsSubu, rl_result.low_reg, t1, t0);
231 NewLIR2(kMipsMflo, rl_result.low_reg, r_LO);
233 NewLIR2(kMipsMfhi, rl_result.low_reg, r_HI);
245 NewLIR2(kMipsMflo, rl_result.low_reg, r_LO)
[all...] |
| fp_mips.cc | 67 NewLIR3(op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg);
114 NewLIR3(op, S2d(rl_result.low_reg, rl_result.high_reg), S2d(rl_src1.low_reg, rl_src1.high_reg),
115 S2d(rl_src2.low_reg, rl_src2.high_reg));
160 src_reg = S2d(rl_src.low_reg, rl_src.high_reg);
163 src_reg = rl_src.low_reg;
167 NewLIR2(op, S2d(rl_result.low_reg, rl_result.high_reg), src_reg);
171 NewLIR2(op, rl_result.low_reg, src_reg)
[all...] |
| target_mips.cc | 85 int MipsMir2Lir::S2d(int low_reg, int high_reg) {
86 return MIPS_S2D(low_reg, high_reg);
436 int low_reg; local
440 low_reg = AllocTempDouble();
441 high_reg = low_reg + 1;
442 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
446 low_reg = AllocTemp();
448 res = (low_reg & 0xff) | ((high_reg & 0xff) << 8);
493 if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &
[all...] |
| call_mips.cc | 117 OpCmpBranch(kCondNe, rl_src.low_reg, r_key, loop_label);
165 r_key = rl_src.low_reg;
182 OpRegRegReg(kOpSub, r_key, rl_src.low_reg, r_key);
184 OpRegRegImm(kOpSub, r_key, rl_src.low_reg, low_key);
298 LoadWordDisp(rMIPS_SELF, ex_offset, rl_result.low_reg);
|
| codegen_mips.h | 53 int S2d(int low_reg, int high_reg);
|
| /art/compiler/dex/ |
| vreg_analysis.cc | 346 cg->IsFpReg(table[i].low_reg) ? 's' : 'r',
347 table[i].low_reg & cg->FpRegMask(),
|
| mir_graph.h | 312 uint8_t low_reg; // First physical register. member in struct:art::RegLocation
|
