1 /* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /* This file contains codegen for the X86 ISA */ 18 19 #include "codegen_x86.h" 20 #include "dex/quick/mir_to_lir-inl.h" 21 #include "x86_lir.h" 22 23 namespace art { 24 25 void X86Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, 26 SpecialCaseHandler special_case) { 27 // TODO 28 } 29 30 /* 31 * The sparse table in the literal pool is an array of <key,displacement> 32 * pairs. 33 */ 34 void X86Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset, 35 RegLocation rl_src) { 36 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 37 if (cu_->verbose) { 38 DumpSparseSwitchTable(table); 39 } 40 int entries = table[1]; 41 const int* keys = reinterpret_cast<const int*>(&table[2]); 42 const int* targets = &keys[entries]; 43 rl_src = LoadValue(rl_src, kCoreReg); 44 for (int i = 0; i < entries; i++) { 45 int key = keys[i]; 46 BasicBlock* case_block = 47 mir_graph_->FindBlock(current_dalvik_offset_ + targets[i]); 48 OpCmpImmBranch(kCondEq, rl_src.low_reg, key, 49 &block_label_list_[case_block->id]); 50 } 51 } 52 53 /* 54 * Code pattern will look something like: 55 * 56 * mov r_val, .. 57 * call 0 58 * pop r_start_of_method 59 * sub r_start_of_method, .. 60 * mov r_key_reg, r_val 61 * sub r_key_reg, low_key 62 * cmp r_key_reg, size-1 ; bound check 63 * ja done 64 * mov r_disp, [r_start_of_method + r_key_reg * 4 + table_offset] 65 * add r_start_of_method, r_disp 66 * jmp r_start_of_method 67 * done: 68 */ 69 void X86Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset, 70 RegLocation rl_src) { 71 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 72 if (cu_->verbose) { 73 DumpPackedSwitchTable(table); 74 } 75 // Add the table to the list - we'll process it later 76 SwitchTable *tab_rec = 77 static_cast<SwitchTable *>(arena_->Alloc(sizeof(SwitchTable), ArenaAllocator::kAllocData)); 78 tab_rec->table = table; 79 tab_rec->vaddr = current_dalvik_offset_; 80 int size = table[1]; 81 tab_rec->targets = static_cast<LIR**>(arena_->Alloc(size * sizeof(LIR*), 82 ArenaAllocator::kAllocLIR)); 83 switch_tables_.Insert(tab_rec); 84 85 // Get the switch value 86 rl_src = LoadValue(rl_src, kCoreReg); 87 int start_of_method_reg = AllocTemp(); 88 // Materialize a pointer to the switch table 89 // NewLIR0(kX86Bkpt); 90 NewLIR1(kX86StartOfMethod, start_of_method_reg); 91 int low_key = s4FromSwitchData(&table[2]); 92 int keyReg; 93 // Remove the bias, if necessary 94 if (low_key == 0) { 95 keyReg = rl_src.low_reg; 96 } else { 97 keyReg = AllocTemp(); 98 OpRegRegImm(kOpSub, keyReg, rl_src.low_reg, low_key); 99 } 100 // Bounds check - if < 0 or >= size continue following switch 101 OpRegImm(kOpCmp, keyReg, size-1); 102 LIR* branch_over = OpCondBranch(kCondHi, NULL); 103 104 // Load the displacement from the switch table 105 int disp_reg = AllocTemp(); 106 NewLIR5(kX86PcRelLoadRA, disp_reg, start_of_method_reg, keyReg, 2, 107 reinterpret_cast<uintptr_t>(tab_rec)); 108 // Add displacement to start of method 109 OpRegReg(kOpAdd, start_of_method_reg, disp_reg); 110 // ..and go! 111 LIR* switch_branch = NewLIR1(kX86JmpR, start_of_method_reg); 112 tab_rec->anchor = switch_branch; 113 114 /* branch_over target here */ 115 LIR* target = NewLIR0(kPseudoTargetLabel); 116 branch_over->target = target; 117 } 118 119 /* 120 * Array data table format: 121 * ushort ident = 0x0300 magic value 122 * ushort width width of each element in the table 123 * uint size number of elements in the table 124 * ubyte data[size*width] table of data values (may contain a single-byte 125 * padding at the end) 126 * 127 * Total size is 4+(width * size + 1)/2 16-bit code units. 128 */ 129 void X86Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) { 130 const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset; 131 // Add the table to the list - we'll process it later 132 FillArrayData *tab_rec = 133 static_cast<FillArrayData*>(arena_->Alloc(sizeof(FillArrayData), ArenaAllocator::kAllocData)); 134 tab_rec->table = table; 135 tab_rec->vaddr = current_dalvik_offset_; 136 uint16_t width = tab_rec->table[1]; 137 uint32_t size = tab_rec->table[2] | ((static_cast<uint32_t>(tab_rec->table[3])) << 16); 138 tab_rec->size = (size * width) + 8; 139 140 fill_array_data_.Insert(tab_rec); 141 142 // Making a call - use explicit registers 143 FlushAllRegs(); /* Everything to home location */ 144 LoadValueDirectFixed(rl_src, rX86_ARG0); 145 // Materialize a pointer to the fill data image 146 NewLIR1(kX86StartOfMethod, rX86_ARG2); 147 NewLIR2(kX86PcRelAdr, rX86_ARG1, reinterpret_cast<uintptr_t>(tab_rec)); 148 NewLIR2(kX86Add32RR, rX86_ARG1, rX86_ARG2); 149 CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData), rX86_ARG0, 150 rX86_ARG1, true); 151 } 152 153 void X86Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 154 FlushAllRegs(); 155 LoadValueDirectFixed(rl_src, rCX); // Get obj 156 LockCallTemps(); // Prepare for explicit register usage 157 GenNullCheck(rl_src.s_reg_low, rCX, opt_flags); 158 // If lock is unheld, try to grab it quickly with compare and exchange 159 // TODO: copy and clear hash state? 160 NewLIR2(kX86Mov32RT, rDX, Thread::ThinLockIdOffset().Int32Value()); 161 NewLIR2(kX86Sal32RI, rDX, LW_LOCK_OWNER_SHIFT); 162 NewLIR2(kX86Xor32RR, rAX, rAX); 163 NewLIR3(kX86LockCmpxchgMR, rCX, mirror::Object::MonitorOffset().Int32Value(), rDX); 164 LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondEq); 165 // If lock is held, go the expensive route - artLockObjectFromCode(self, obj); 166 CallRuntimeHelperReg(QUICK_ENTRYPOINT_OFFSET(pLockObject), rCX, true); 167 branch->target = NewLIR0(kPseudoTargetLabel); 168 } 169 170 void X86Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 171 FlushAllRegs(); 172 LoadValueDirectFixed(rl_src, rAX); // Get obj 173 LockCallTemps(); // Prepare for explicit register usage 174 GenNullCheck(rl_src.s_reg_low, rAX, opt_flags); 175 // If lock is held by the current thread, clear it to quickly release it 176 // TODO: clear hash state? 177 NewLIR2(kX86Mov32RT, rDX, Thread::ThinLockIdOffset().Int32Value()); 178 NewLIR2(kX86Sal32RI, rDX, LW_LOCK_OWNER_SHIFT); 179 NewLIR3(kX86Mov32RM, rCX, rAX, mirror::Object::MonitorOffset().Int32Value()); 180 OpRegReg(kOpSub, rCX, rDX); 181 LIR* branch = NewLIR2(kX86Jcc8, 0, kX86CondNe); 182 NewLIR3(kX86Mov32MR, rAX, mirror::Object::MonitorOffset().Int32Value(), rCX); 183 LIR* branch2 = NewLIR1(kX86Jmp8, 0); 184 branch->target = NewLIR0(kPseudoTargetLabel); 185 // Otherwise, go the expensive route - UnlockObjectFromCode(obj); 186 CallRuntimeHelperReg(QUICK_ENTRYPOINT_OFFSET(pUnlockObject), rAX, true); 187 branch2->target = NewLIR0(kPseudoTargetLabel); 188 } 189 190 void X86Mir2Lir::GenMoveException(RegLocation rl_dest) { 191 int ex_offset = Thread::ExceptionOffset().Int32Value(); 192 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 193 NewLIR2(kX86Mov32RT, rl_result.low_reg, ex_offset); 194 NewLIR2(kX86Mov32TI, ex_offset, 0); 195 StoreValue(rl_dest, rl_result); 196 } 197 198 /* 199 * Mark garbage collection card. Skip if the value we're storing is null. 200 */ 201 void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) { 202 int reg_card_base = AllocTemp(); 203 int reg_card_no = AllocTemp(); 204 LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); 205 NewLIR2(kX86Mov32RT, reg_card_base, Thread::CardTableOffset().Int32Value()); 206 OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); 207 StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, 208 kUnsignedByte); 209 LIR* target = NewLIR0(kPseudoTargetLabel); 210 branch_over->target = target; 211 FreeTemp(reg_card_base); 212 FreeTemp(reg_card_no); 213 } 214 215 void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { 216 /* 217 * On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live. Let the register 218 * allocation mechanism know so it doesn't try to use any of them when 219 * expanding the frame or flushing. This leaves the utility 220 * code with no spare temps. 221 */ 222 LockTemp(rX86_ARG0); 223 LockTemp(rX86_ARG1); 224 LockTemp(rX86_ARG2); 225 226 /* Build frame, return address already on stack */ 227 OpRegImm(kOpSub, rX86_SP, frame_size_ - 4); 228 229 /* 230 * We can safely skip the stack overflow check if we're 231 * a leaf *and* our frame size < fudge factor. 232 */ 233 bool skip_overflow_check = (mir_graph_->MethodIsLeaf() && 234 (static_cast<size_t>(frame_size_) < 235 Thread::kStackOverflowReservedBytes)); 236 NewLIR0(kPseudoMethodEntry); 237 /* Spill core callee saves */ 238 SpillCoreRegs(); 239 /* NOTE: promotion of FP regs currently unsupported, thus no FP spill */ 240 DCHECK_EQ(num_fp_spills_, 0); 241 if (!skip_overflow_check) { 242 // cmp rX86_SP, fs:[stack_end_]; jcc throw_launchpad 243 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kThrowStackOverflow, 0, 0, 0, 0); 244 OpRegThreadMem(kOpCmp, rX86_SP, Thread::StackEndOffset()); 245 OpCondBranch(kCondUlt, tgt); 246 // Remember branch target - will process later 247 throw_launchpads_.Insert(tgt); 248 } 249 250 FlushIns(ArgLocs, rl_method); 251 252 FreeTemp(rX86_ARG0); 253 FreeTemp(rX86_ARG1); 254 FreeTemp(rX86_ARG2); 255 } 256 257 void X86Mir2Lir::GenExitSequence() { 258 /* 259 * In the exit path, rX86_RET0/rX86_RET1 are live - make sure they aren't 260 * allocated by the register utilities as temps. 261 */ 262 LockTemp(rX86_RET0); 263 LockTemp(rX86_RET1); 264 265 NewLIR0(kPseudoMethodExit); 266 UnSpillCoreRegs(); 267 /* Remove frame except for return address */ 268 OpRegImm(kOpAdd, rX86_SP, frame_size_ - 4); 269 NewLIR0(kX86Ret); 270 } 271 272 } // namespace art 273
