| /external/chromium_org/v8/src/arm/ |
| disasm-arm.cc | 609 if (format[1] == 'h') { // 'shift_op or 'shift_rm or 'shift_sat.
610 if (format[6] == 'o') { // 'shift_op
611 ASSERT(STRING_STARTS_WITH(format, "shift_op"));
888 Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
892 Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
896 Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
900 Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
904 Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
908 Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
912 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
[all...] |
| assembler-arm.cc | 343 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
345 ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it
348 shift_op_ = shift_op;
350 if (shift_op == RRX) {
359 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
360 ASSERT(shift_op != RRX);
363 shift_op_ = shift_op;
386 ShiftOp shift_op, int shift_imm, AddrMode am) {
390 shift_op_ = shift_op;
[all...] |
| assembler-arm.h | 536 // rm <shift_op> shift_imm
537 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
550 // rm <shift_op> rs
551 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
571 ShiftOp shift_op() const { return shift_op_; } function in class:v8::internal::BASE_EMBEDDED
600 // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset
601 // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex
602 // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex
604 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
[all...] |
| macro-assembler-arm.cc | 351 ASSERT((src.shift_op() == ASR) || (src.shift_op() == LSL));
[all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 559 if (format[1] == 'h') { // 'shift_op or 'shift_rm or 'shift_sat.
560 if (format[6] == 'o') { // 'shift_op
561 ASSERT(STRING_STARTS_WITH(format, "shift_op"));
828 Format(instr, "and'cond's 'rd, 'rn, 'shift_op");
832 Format(instr, "eor'cond's 'rd, 'rn, 'shift_op");
836 Format(instr, "sub'cond's 'rd, 'rn, 'shift_op");
840 Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op");
844 Format(instr, "add'cond's 'rd, 'rn, 'shift_op");
848 Format(instr, "adc'cond's 'rd, 'rn, 'shift_op");
852 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op");
[all...] |
| assembler-arm.h | 413 // rm <shift_op> shift_imm
414 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
416 // rm <shift_op> rs
417 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
437 ShiftOp shift_op() const { return shift_op_; } function in class:v8::internal::BASE_EMBEDDED
466 // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset
467 // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex
468 // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex
470 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
[all...] |
| assembler-arm.cc | 183 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
185 ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it
188 shift_op_ = shift_op;
190 if (shift_op == RRX) {
199 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
200 ASSERT(shift_op != RRX);
203 shift_op_ = shift_op;
225 ShiftOp shift_op, int shift_imm, AddrMode am) {
229 shift_op_ = shift_op;
[all...] |
| macro-assembler-arm.cc | 373 ASSERT((src.shift_op() == ASR) || (src.shift_op() == LSL));
[all...] |
| /art/compiler/dex/quick/ |
| gen_common.cc | 1207 bool shift_op = false; local
1455 int shift_op = false; local
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_arm_toIR.c | 3193 IROp shift_op, add_op; local
[all...] |
| /prebuilts/devtools/tools/lib/ |
| jython-standalone-2.5.3.jar | |
| /prebuilts/tools/common/m2/repository/org/python/jython/2.5.3/ |
| jython-2.5.3.jar | |
| /prebuilts/tools/common/m2/repository/org/python/jython-standalone/2.5.3/ |
| jython-standalone-2.5.3.jar | |
| /prebuilts/misc/common/jython/ |
| jython.jar | |
