| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 1 //===----- ScheduleDAGRRList.cpp - Reg pressure reduction list scheduler --===//
73 "disable-sched-reg-pressure", cl::Hidden, cl::init(false),
235 void releaseInterferences(unsigned Reg = 0);
289 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
290 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
667 // Check for phys reg copy.
[all...] |
| SelectionDAGISel.cpp | 406 unsigned Reg = hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
407 if (TargetRegisterInfo::isPhysicalRegister(Reg))
410 MachineInstr *Def = RegInfo->getVRegDef(Reg);
416 // If Reg is live-in then update debug info to track its copy in a vreg.
417 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 100 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
103 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
117 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
121 unsigned Reg);
124 unsigned Reg);
172 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
218 "Reg should not have empty live interval.");
314 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
318 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
360 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
[all...] |
| RegisterCoalescer.cpp | 151 /// the source value number is defined by a copy from the destination reg
152 /// see if we can merge these two destination reg valno# into a single
480 DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
500 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
508 CopyMI->substituteRegister(IntA.reg, IntB.reg, 0, *TRI);
600 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
617 if (NewReg != IntB.reg || !LiveRangeQuery(IntB, AValNo->def).isKill())
625 // If some of the uses of IntA.reg is already coalesced away, return false.
628 MRI->use_nodbg_begin(IntA.reg),
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 226 unsigned Reg = MLoc.getReg();
227 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
233 unsigned SReg = Reg - ARM::S0;
254 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
260 unsigned QReg = Reg - ARM::Q0;
332 unsigned Reg = MO.getReg();
333 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
335 if(ARM::GPRPairRegClass.contains(Reg)) {
[all...] |
| ARMCodeEmitter.cpp | 260 // {17-13} = reg
269 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
275 Binary |= (Reg << 13);
314 // {12-9} = reg
324 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | 81 unsigned Reg;
88 : Offset(o), Reg(r), isKill(k), Position(p), MBBI(i), Merged(false) {}
303 // VLDM/VSTM do not support DB mode without also updating the base reg.
387 unsigned Reg = memOps[i].Reg;
388 KilledRegs.insert(Reg);
389 Killer[Reg] = i;
396 unsigned Reg = memOps[i].Reg;
399 bool isKill = memOps[i].isKill || KilledRegs.count(Reg);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 177 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
178 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
191 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
202 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
203 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
248 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
249 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
263 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
264 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo))
[all...] |
| HexagonHardwareLoops.cpp | 120 /// If successful, it will return true and set the \p Reg, \p IVBump
130 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
236 unsigned Reg;
246 Contents.R.Reg = v;
257 return Contents.R.Reg;
270 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
320 unsigned &Reg,
348 // latch block, and see if is a result of an addition of form "reg+imm",
349 // where the "reg" is defined by the PHI node we are looking at.
416 Reg = F->second.first
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 109 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
220 // stackless code if all local vars are reg-allocated.
603 unsigned Reg = isPPC64 ? PPC::X31 : PPC::R31;
604 Reg = MRI->getDwarfRegNum(Reg, true);
606 MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset));
610 unsigned Reg = isPPC64 ? PPC::X30 : PPC::R30;
611 Reg = MRI->getDwarfRegNum(Reg, true);
613 MCCFIInstruction::createOffset(FrameLabel, Reg, BPOffset))
[all...] |
| PPCISelDAGToDAG.cpp | 60 // Make sure we re-emit a set of the global base reg if necessary
164 /// register can be improved, but it is wrong to substitute Reg+Reg for
165 /// Reg in an asm, because the load or store opcode would have to change.
198 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
199 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
[all...] |
| PPCInstrInfo.cpp | 548 llvm_unreachable("Impossible reg-to-reg copy");
601 unsigned Reg = 0;
604 Reg = PPC::CR0;
607 Reg = PPC::CR1;
610 Reg = PPC::CR2;
613 Reg = PPC::CR3;
616 Reg = PPC::CR4;
619 Reg = PPC::CR5;
622 Reg = PPC::CR6
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 501 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
502 MFI->LiveOuts.push_back(Reg);
503 return DAG.getCopyToReg(Chain, SDLoc(Op), Reg, Op.getOperand(2));
535 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
538 MRI.addLiveIn(Reg);
540 SDLoc(DAG.getEntryNode()), Reg, VT);
[all...] |
| SIISelLowering.cpp | 226 unsigned Reg = VA.getLocReg();
230 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
232 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
233 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
237 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
239 Reg = MF.addLiveIn(Reg, RC);
240 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT)
[all...] |
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 100 RegOp Reg;
134 Op->Reg.Kind = Kind;
135 Op->Reg.Num = Num;
177 return Kind == KindReg && Reg.Kind == RegKind;
181 return Reg.Num;
308 bool parseRegister(Register &Reg);
310 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
431 bool SystemZAsmParser::parseRegister(Register &Reg) {
432 Reg.StartLoc = Parser.getTok().getLoc();
441 return Error(Reg.StartLoc, "invalid register")
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 417 * Reg - All possible values of the reg field in the ModR/M byte.
424 } Reg;
568 Reg vvvv;
591 Reg opcodeRegister;
599 Reg regBase;
605 /* The reg field always encodes a register */
606 Reg reg; member in struct:InternalInstruction
|
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 818 /// Reg - The def for the register that we're emitting. If this is null, then
820 const CodeGenRegister *Reg;
823 EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt)
824 : Matcher(EmitRegister), Reg(reg), VT(vt) {}
826 const CodeGenRegister *getReg() const { return Reg; }
836 return cast<EmitRegisterMatcher>(M)->Reg == Reg &&
840 return ((unsigned)(intptr_t)Reg) << 4 | VT;
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngine.cpp | 224 SVal Reg = loc::MemRegionVal(TR);
229 State = State->bindLoc(Reg, V);
235 Reg = StoreMgr.evalDerivedToBase(Reg, *I);
238 State = State->BindExpr(Result, LC, Reg);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 598 unsigned Reg;
600 Reg = MI->getOperand(0).getReg();
605 MI->getOperand(0).getIndex(), Reg);
608 if (Reg == 0) {
617 OS << AP.TM.getRegisterInfo()->getName(Reg);
819 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
821 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid() && Reg < 0;
823 Reg = TRI->getDwarfRegNum(*SR, false);
833 // probably assert that Reg >= 0 once debug info generation is more mature.
836 if (Reg < 32)
[all...] |
| DwarfDebug.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 206 struct RegOp Reg;
232 return Reg.RegNum;
792 Op->Reg.RegNum = RegNum;
798 Op->Reg.RegNum = RegNum;
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 35 bool setATReg(unsigned Reg);
267 struct RegOp Reg;
317 return Reg.RegNum;
322 Reg.Kind = RegKind;
351 Op->Reg.RegNum = RegNum;
376 return Kind == k_Register && Reg.Kind == Kind_GPR32;
379 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
383 return Kind == k_Register && Reg.Kind == Kind_GPR64;
388 return Reg.Kind == Kind_HWRegs;
393 return Reg.Kind == Kind_HW64Regs
[all...] |
