| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 57 // Try to get first reg.
58 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
59 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
68 // Try to get second reg.
69 if (unsigned Reg = State.AllocateReg(RegList, 6))
70 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
87 unsigned Reg = 0;
91 Reg = SP::I0 + Offset/8;
94 Reg = SP::D0 + Offset/8;
97 Reg = SP::F1 + Offset/4
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 252 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
770 // Build a sequence of copy-to-reg nodes, chained and glued together.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 516 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
525 // FIXME: How do we know Base.Reg is free??
526 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
535 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
536 AM.Base.Reg = X86::RIP;
553 StubAM.Base.Reg = AM.Base.Reg;
565 StubAM.Base.Reg = X86::RIP;
585 AM.Base.Reg = LoadReg;
593 if (AM.Base.Reg == 0)
[all...] |
| X86ISelDAGToDAG.cpp | 95 void setBaseReg(SDValue Reg) {
97 Base_Reg = Reg;
648 // Base and index reg must be 0 in order to use %rip as base.
731 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
[all...] |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| AsmMatcherEmitter.cpp | 382 static ResOperand getRegOp(Record *Reg) {
385 X.Register = Reg;
779 if (Record *Reg = AsmOperands[i].SingletonReg)
780 SingletonRegisters.insert(Reg);
[all...] |
| CodeGenRegisters.cpp | 142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]);
143 ExplicitAliases.push_back(Reg);
144 Reg->ExplicitAliases.push_back(this);
495 // Make sure all sub-registers have been visited first, so the super-reg
586 Record *Reg = Lists[i][n];
588 Name += Reg->getName();
589 Tuple.push_back(DefInit::get(Reg));
591 unsigned(Reg->getValueAsInt("CostPerUse")));
691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
692 Members.insert(Reg);
[all...] |
| /external/qemu/target-i386/ |
| ops_sse.h | 22 #define Reg MMXReg
30 #define Reg XMMReg
39 void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s)
63 void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s)
84 void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s)
108 void glue(helper_psrld, SUFFIX)(Reg *d, Reg *s
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_mips_defs.h | 45 extern HReg hregMIPS_GPR0(Bool mode64); // scratch reg / zero reg
183 Mam_IR, /* Immediate (signed 16-bit) + Reg */
210 /* --------- Operand, which can be a reg or a u16/s16. --------- */
225 HReg reg; member in struct:__anon29070::__anon29071::__anon29073
226 } Reg;
237 HReg reg; member in struct:__anon29074
241 extern MIPSAModeV *mkMIPSAModeV(HReg reg, Int simm11);
245 /* --------- Reg or imm-8x4 operands --------- */
251 MIPSri84_R /* reg */
262 HReg reg; member in struct:__anon29076::__anon29077::__anon29079
285 HReg reg; member in struct:__anon29081::__anon29082::__anon29084
586 HReg reg; member in struct:__anon29091::__anon29092::__anon29115
[all...] |
| host_amd64_defs.h | 125 Aam_IR, /* Immediate + Reg */
136 HReg reg; member in struct:__anon28886::__anon28887::__anon28888
156 /* --------- Operand, which can be reg, immediate or memory. --------- */
174 HReg reg; member in struct:__anon28891::__anon28892::__anon28894
175 } Reg;
192 /* --------- Operand, which can be reg or immediate only. --------- */
209 HReg reg; member in struct:__anon28897::__anon28898::__anon28900
210 } Reg;
222 /* --------- Operand, which can be reg or memory only. --------- */
236 HReg reg; member in struct:__anon28902::__anon28903::__anon28904
621 HReg reg; member in struct:__anon28912::__anon28913::__anon28948
626 HReg reg; member in struct:__anon28912::__anon28913::__anon28949
[all...] |
| host_x86_defs.h | 113 Xam_IR, /* Immediate + Reg */
124 HReg reg; member in struct:__anon29269::__anon29270::__anon29271
144 /* --------- Operand, which can be reg, immediate or memory. --------- */
162 HReg reg; member in struct:__anon29274::__anon29275::__anon29277
163 } Reg;
179 /* --------- Operand, which can be reg or immediate only. --------- */
196 HReg reg; member in struct:__anon29280::__anon29281::__anon29283
197 } Reg;
209 /* --------- Operand, which can be reg or memory only. --------- */
223 HReg reg; member in struct:__anon29285::__anon29286::__anon29287
544 HReg reg; member in struct:__anon29295::__anon29296::__anon29321
553 HReg reg; member in struct:__anon29295::__anon29296::__anon29322
594 HReg reg; member in struct:__anon29295::__anon29296::__anon29329
599 HReg reg; member in struct:__anon29295::__anon29296::__anon29330
[all...] |
| host_ppc_defs.h | 51 extern HReg hregPPC_GPR0 ( Bool mode64 ); // scratch reg / zero reg
200 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */
229 /* --------- Operand, which can be a reg or a u16/s16. --------- */
247 HReg reg; member in struct:__anon29133::__anon29134::__anon29136
248 } Reg;
260 /* --------- Operand, which can be a reg or a u32/64. --------- */
274 HReg Reg;
286 /* --------- Operand, which can be a vector reg or a s6. --------- */
300 HReg Reg;
708 HReg reg; member in struct:__anon29150::__anon29151::__anon29175
761 HReg reg; member in struct:__anon29150::__anon29151::__anon29183
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 240 unsigned Reg = MO.getReg();
242 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
244 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
246 LV->addVirtualRegisterDead(Reg, NewMI);
252 if (!NewMI->readsRegister(Reg))
254 LV->addVirtualRegisterKilled(Reg, NewMI);
707 assert(Opc && "Impossible reg-to-reg copy");
712 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
745 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
[all...] |
| ARMFastISel.cpp | 63 unsigned Reg;
72 Base.Reg = 0;
514 // the combined constant into an FP reg.
551 // The extra reg is for addrmode5.
[all...] |
| ARMISelLowering.cpp | 1797 unsigned reg = State->AllocateReg(GPRArgRegs, 4); local
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 296 void onRegister(unsigned Reg) {
305 TmpReg = Reg;
313 IndexReg = Reg;
648 struct RegOp Reg;
683 return Reg.RegNo;
948 Res->Reg.RegNo = RegNo;
2060 unsigned reg = Op2->getReg(); local
2090 unsigned reg = Op1->getReg(); local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 48 // we may not actually need both reg and (-1 * reg) in registers; the
142 void CountRegister(const SCEV *Reg, size_t LUIdx);
143 void DropRegister(const SCEV *Reg, size_t LUIdx);
146 bool isRegUsedByUsesOtherThan(const SCEV *Reg, size_t LUIdx) const;
148 const SmallBitVector &getUsedByIndices(const SCEV *Reg) const;
163 RegUseTracker::CountRegister(const SCEV *Reg, size_t LUIdx) {
165 RegUsesMap.insert(std::make_pair(Reg, RegSortData()));
168 RegSequence.push_back(Reg);
174 RegUseTracker::DropRegister(const SCEV *Reg, size_t LUIdx)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 615 unsigned Reg, Type *Ty) {
623 Regs.push_back(Reg + i);
625 Reg += NumRegs;
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 436 struct RegOp Reg;
467 Reg = o.Reg;
552 return Reg.RegNum;
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
