| /external/chromium_org/v8/test/cctest/ |
| test-disasm-ia32.cc | 350 __ fsub(3);
|
| test-disasm-x64.cc | 332 __ fsub(3);
|
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 69 /// Given operands for an FSub, see if we can fold the result. If not, this
|
| TargetTransformInfo.h | 302 /// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
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| /external/llvm/test/Bindings/Ocaml/ |
| vmcore.ml | 210 * CHECK: @const_fneg = global double fsub
219 * CHECK: @const_fsub = global double fsub
[all...] |
| /external/llvm/test/CodeGen/SPARC/ |
| 64abi.ll | 186 %rv = fsub float %a0, %a1
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| /external/llvm/test/CodeGen/X86/ |
| pr3154.ll | 25 %9 = fsub double %8, 1.000000e+00 ; <double> [#uses=1]
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| sse2.ll | 177 %tmp21 = fsub <4 x float> %tmp5, %tmp ; <<4 x float>> [#uses=1]
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 168 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
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| /external/proguard/src/proguard/classfile/instruction/ |
| InstructionConstants.java | 338 "fsub",
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| /external/v8/test/cctest/ |
| test-disasm-ia32.cc | 359 __ fsub(3);
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| test-disasm-x64.cc | 339 __ fsub(3);
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| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 644 INSTKEYWORD(sub, Sub); INSTKEYWORD(fsub, FSub);
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.td | 638 defm FSUB : F3<"sub", fsub>;
642 defm FSUB_rn : F3_rn<"sub", fsub>;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.td | [all...] |
| /external/llvm/test/MC/X86/ |
| x86-32.s | 333 // CHECK: fsub %st(0)
335 fsub %st(0), %st
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| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| assyntax.h | [all...] |
| /external/llvm/docs/tutorial/ |
| OCamlLangImpl7.rst | 485 %subtmp = fsub double %x3, 1.000000e+00
488 %subtmp5 = fsub double %x4, 2.000000e+00
522 %subtmp = fsub double %x, 1.000000e+00
524 %subtmp5 = fsub double %x, 2.000000e+00
550 %subtmp = fsub double %x, 1.000000e+00
552 %subtmp5 = fsub double %x, 2.000000e+00
[all...] |
| /external/mesa3d/src/mesa/x86/ |
| assyntax.h | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrNEON.td | 190 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
259 (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
[all...] |
| /external/qemu/target-i386/ |
| ops_sse.h | 334 #define FSUB(a, b) ((a) - (b))
367 SSE_HELPER_B(helper_psubb, FSUB)
368 SSE_HELPER_W(helper_psubw, FSUB)
369 SSE_HELPER_L(helper_psubl, FSUB)
370 SSE_HELPER_Q(helper_psubq, FSUB)
[all...] |
| /external/elfutils/libcpu/defs/ |
| i386 | 209 11011000,11100{freg}:fsub {freg},%st
210 11011100,11100{freg}:fsub %st,{freg}
211 11011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m}
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| LegalizeFloatTypes.cpp | 93 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 47 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
48 setOperationAction(ISD::FSUB, MVT::v2f32, Expand);
59 setOperationAction(ISD::FSUB, MVT::f32, Expand);
[all...] |
