1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 instruction set, defining the instructions, and 11 // properties of the instructions which are needed for code generation, machine 12 // code emission, and analysis. 13 // 14 //===----------------------------------------------------------------------===// 15 16 //===----------------------------------------------------------------------===// 17 // X86 specific DAG Nodes. 18 // 19 20 def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29 def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33 // Unary and binary operator instructions that set EFLAGS as a side-effect. 34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisInt<0>, SDTCisVT<1, i32>]>; 36 37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 38 [SDTCisSameAs<0, 2>, 39 SDTCisSameAs<0, 3>, 40 SDTCisInt<0>, SDTCisVT<1, i32>]>; 41 42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 44 [SDTCisSameAs<0, 2>, 45 SDTCisSameAs<0, 3>, 46 SDTCisInt<0>, 47 SDTCisVT<1, i32>, 48 SDTCisVT<4, i32>]>; 49 // RES1, RES2, FLAGS = op LHS, RHS 50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 51 [SDTCisSameAs<0, 1>, 52 SDTCisSameAs<0, 2>, 53 SDTCisSameAs<0, 3>, 54 SDTCisInt<0>, SDTCisVT<1, i32>]>; 55 def SDTX86BrCond : SDTypeProfile<0, 3, 56 [SDTCisVT<0, OtherVT>, 57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 58 59 def SDTX86SetCC : SDTypeProfile<1, 2, 60 [SDTCisVT<0, i8>, 61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 62 def SDTX86SetCC_C : SDTypeProfile<1, 2, 63 [SDTCisInt<0>, 64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 65 66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 67 68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 69 70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 71 SDTCisVT<2, i8>]>; 72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 77 78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 80 SDTCisVT<1, i32>]>; 81 82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 83 84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 85 SDTCisVT<1, iPTR>, 86 SDTCisVT<2, iPTR>]>; 87 88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 89 SDTCisPtrTy<1>, 90 SDTCisVT<2, i32>, 91 SDTCisVT<3, i8>, 92 SDTCisVT<4, i32>]>; 93 94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 95 96 def SDTX86Void : SDTypeProfile<0, 0, []>; 97 98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 99 100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 101 102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 103 104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 105 106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 107 108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 109 110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 111 112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 113 114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 115 116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 117 [SDNPHasChain,SDNPSideEffect]>; 118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 119 [SDNPHasChain]>; 120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 121 [SDNPHasChain]>; 122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 123 [SDNPHasChain]>; 124 125 126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 130 131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 133 134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 136 [SDNPHasChain]>; 137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 139 140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 141 142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 143 [SDNPHasChain, SDNPSideEffect]>; 144 145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 146 [SDNPHasChain, SDNPSideEffect]>; 147 148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 150 SDNPMayLoad, SDNPMemOperand]>; 151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 153 SDNPMayLoad, SDNPMemOperand]>; 154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 156 SDNPMayLoad, SDNPMemOperand]>; 157 158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, 159 [SDNPHasChain, SDNPMayStore, 160 SDNPMayLoad, SDNPMemOperand]>; 161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, 162 [SDNPHasChain, SDNPMayStore, 163 SDNPMayLoad, SDNPMemOperand]>; 164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, 165 [SDNPHasChain, SDNPMayStore, 166 SDNPMayLoad, SDNPMemOperand]>; 167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, 168 [SDNPHasChain, SDNPMayStore, 169 SDNPMayLoad, SDNPMemOperand]>; 170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, 171 [SDNPHasChain, SDNPMayStore, 172 SDNPMayLoad, SDNPMemOperand]>; 173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, 174 [SDNPHasChain, SDNPMayStore, 175 SDNPMayLoad, SDNPMemOperand]>; 176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, 177 [SDNPHasChain, SDNPMayStore, 178 SDNPMayLoad, SDNPMemOperand]>; 179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 181 182 def X86vastart_save_xmm_regs : 183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 184 SDT_X86VASTART_SAVE_XMM_REGS, 185 [SDNPHasChain, SDNPVariadic]>; 186 def X86vaarg64 : 187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 189 SDNPMemOperand]>; 190 def X86callseq_start : 191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 192 [SDNPHasChain, SDNPOutGlue]>; 193 def X86callseq_end : 194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 196 197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 199 SDNPVariadic]>; 200 201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 205 SDNPMayLoad]>; 206 207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 209 210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 212 213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 215 216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 218 219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 220 [SDNPHasChain]>; 221 222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 223 SDTypeProfile<1, 1, [SDTCisInt<0>, 224 SDTCisPtrTy<1>]>, 225 [SDNPHasChain, SDNPSideEffect]>; 226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 228 [SDNPHasChain, SDNPSideEffect]>; 229 230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 232 233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 234 [SDNPCommutative]>; 235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 237 [SDNPCommutative]>; 238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 239 [SDNPCommutative]>; 240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 242 243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 246 [SDNPCommutative]>; 247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 248 [SDNPCommutative]>; 249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 250 [SDNPCommutative]>; 251 def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>; 252 253 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>; 254 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>; 255 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>; 256 257 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 258 259 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 260 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 261 262 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 263 [SDNPHasChain]>; 264 265 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 266 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 267 268 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, 269 [SDNPHasChain, SDNPOutGlue]>; 270 271 //===----------------------------------------------------------------------===// 272 // X86 Operand Definitions. 273 // 274 275 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 276 // the index operand of an address, to conform to x86 encoding restrictions. 277 def ptr_rc_nosp : PointerLikeRegClass<1>; 278 279 // *mem - Operand definitions for the funky X86 addressing mode operands. 280 // 281 def X86MemAsmOperand : AsmOperandClass { 282 let Name = "Mem"; let PredicateMethod = "isMem"; 283 } 284 def X86Mem8AsmOperand : AsmOperandClass { 285 let Name = "Mem8"; let PredicateMethod = "isMem8"; 286 } 287 def X86Mem16AsmOperand : AsmOperandClass { 288 let Name = "Mem16"; let PredicateMethod = "isMem16"; 289 } 290 def X86Mem32AsmOperand : AsmOperandClass { 291 let Name = "Mem32"; let PredicateMethod = "isMem32"; 292 } 293 def X86Mem64AsmOperand : AsmOperandClass { 294 let Name = "Mem64"; let PredicateMethod = "isMem64"; 295 } 296 def X86Mem80AsmOperand : AsmOperandClass { 297 let Name = "Mem80"; let PredicateMethod = "isMem80"; 298 } 299 def X86Mem128AsmOperand : AsmOperandClass { 300 let Name = "Mem128"; let PredicateMethod = "isMem128"; 301 } 302 def X86Mem256AsmOperand : AsmOperandClass { 303 let Name = "Mem256"; let PredicateMethod = "isMem256"; 304 } 305 306 // Gather mem operands 307 def X86MemVX32Operand : AsmOperandClass { 308 let Name = "MemVX32"; let PredicateMethod = "isMemVX32"; 309 } 310 def X86MemVY32Operand : AsmOperandClass { 311 let Name = "MemVY32"; let PredicateMethod = "isMemVY32"; 312 } 313 def X86MemVX64Operand : AsmOperandClass { 314 let Name = "MemVX64"; let PredicateMethod = "isMemVX64"; 315 } 316 def X86MemVY64Operand : AsmOperandClass { 317 let Name = "MemVY64"; let PredicateMethod = "isMemVY64"; 318 } 319 320 def X86MemVZ64Operand : AsmOperandClass { 321 let Name = "MemVZ64"; let PredicateMethod = "isMemVZ64"; 322 } 323 def X86MemVZ32Operand : AsmOperandClass { 324 let Name = "MemVZ32"; let PredicateMethod = "isMemVZ32"; 325 } 326 def X86Mem512AsmOperand : AsmOperandClass { 327 let Name = "Mem512"; let PredicateMethod = "isMem512"; 328 } 329 330 def X86AbsMemAsmOperand : AsmOperandClass { 331 let Name = "AbsMem"; 332 let SuperClasses = [X86MemAsmOperand]; 333 } 334 class X86MemOperand<string printMethod> : Operand<iPTR> { 335 let PrintMethod = printMethod; 336 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 337 let ParserMatchClass = X86MemAsmOperand; 338 } 339 340 let OperandType = "OPERAND_MEMORY" in { 341 def opaque32mem : X86MemOperand<"printopaquemem">; 342 def opaque48mem : X86MemOperand<"printopaquemem">; 343 def opaque80mem : X86MemOperand<"printopaquemem">; 344 def opaque512mem : X86MemOperand<"printopaquemem">; 345 346 def i8mem : X86MemOperand<"printi8mem"> { 347 let ParserMatchClass = X86Mem8AsmOperand; } 348 def i16mem : X86MemOperand<"printi16mem"> { 349 let ParserMatchClass = X86Mem16AsmOperand; } 350 def i32mem : X86MemOperand<"printi32mem"> { 351 let ParserMatchClass = X86Mem32AsmOperand; } 352 def i64mem : X86MemOperand<"printi64mem"> { 353 let ParserMatchClass = X86Mem64AsmOperand; } 354 def i128mem : X86MemOperand<"printi128mem"> { 355 let ParserMatchClass = X86Mem128AsmOperand; } 356 def i256mem : X86MemOperand<"printi256mem"> { 357 let ParserMatchClass = X86Mem256AsmOperand; } 358 def i512mem : X86MemOperand<"printi512mem"> { 359 let ParserMatchClass = X86Mem512AsmOperand; } 360 def f32mem : X86MemOperand<"printf32mem"> { 361 let ParserMatchClass = X86Mem32AsmOperand; } 362 def f64mem : X86MemOperand<"printf64mem"> { 363 let ParserMatchClass = X86Mem64AsmOperand; } 364 def f80mem : X86MemOperand<"printf80mem"> { 365 let ParserMatchClass = X86Mem80AsmOperand; } 366 def f128mem : X86MemOperand<"printf128mem"> { 367 let ParserMatchClass = X86Mem128AsmOperand; } 368 def f256mem : X86MemOperand<"printf256mem">{ 369 let ParserMatchClass = X86Mem256AsmOperand; } 370 def f512mem : X86MemOperand<"printf512mem">{ 371 let ParserMatchClass = X86Mem512AsmOperand; } 372 def v512mem : Operand<iPTR> { 373 let PrintMethod = "printf512mem"; 374 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); 375 let ParserMatchClass = X86Mem512AsmOperand; } 376 377 // Gather mem operands 378 def vx32mem : X86MemOperand<"printi32mem">{ 379 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 380 let ParserMatchClass = X86MemVX32Operand; } 381 def vy32mem : X86MemOperand<"printi32mem">{ 382 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 383 let ParserMatchClass = X86MemVY32Operand; } 384 def vx64mem : X86MemOperand<"printi64mem">{ 385 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 386 let ParserMatchClass = X86MemVX64Operand; } 387 def vy64mem : X86MemOperand<"printi64mem">{ 388 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 389 let ParserMatchClass = X86MemVY64Operand; } 390 def vy64xmem : X86MemOperand<"printi64mem">{ 391 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm); 392 let ParserMatchClass = X86MemVY64Operand; } 393 def vz32mem : X86MemOperand<"printi32mem">{ 394 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm); 395 let ParserMatchClass = X86MemVZ32Operand; } 396 def vz64mem : X86MemOperand<"printi64mem">{ 397 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); 398 let ParserMatchClass = X86MemVZ64Operand; } 399 } 400 401 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 402 // plain GR64, so that it doesn't potentially require a REX prefix. 403 def i8mem_NOREX : Operand<i64> { 404 let PrintMethod = "printi8mem"; 405 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 406 let ParserMatchClass = X86Mem8AsmOperand; 407 let OperandType = "OPERAND_MEMORY"; 408 } 409 410 // GPRs available for tailcall. 411 // It represents GR32_TC, GR64_TC or GR64_TCW64. 412 def ptr_rc_tailcall : PointerLikeRegClass<2>; 413 414 // Special i32mem for addresses of load folding tail calls. These are not 415 // allowed to use callee-saved registers since they must be scheduled 416 // after callee-saved register are popped. 417 def i32mem_TC : Operand<i32> { 418 let PrintMethod = "printi32mem"; 419 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 420 i32imm, i8imm); 421 let ParserMatchClass = X86Mem32AsmOperand; 422 let OperandType = "OPERAND_MEMORY"; 423 } 424 425 // Special i64mem for addresses of load folding tail calls. These are not 426 // allowed to use callee-saved registers since they must be scheduled 427 // after callee-saved register are popped. 428 def i64mem_TC : Operand<i64> { 429 let PrintMethod = "printi64mem"; 430 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 431 ptr_rc_tailcall, i32imm, i8imm); 432 let ParserMatchClass = X86Mem64AsmOperand; 433 let OperandType = "OPERAND_MEMORY"; 434 } 435 436 let OperandType = "OPERAND_PCREL", 437 ParserMatchClass = X86AbsMemAsmOperand, 438 PrintMethod = "printPCRelImm" in { 439 def i32imm_pcrel : Operand<i32>; 440 def i16imm_pcrel : Operand<i16>; 441 442 def offset8 : Operand<i64>; 443 def offset16 : Operand<i64>; 444 def offset32 : Operand<i64>; 445 def offset64 : Operand<i64>; 446 447 // Branch targets have OtherVT type and print as pc-relative values. 448 def brtarget : Operand<OtherVT>; 449 def brtarget8 : Operand<OtherVT>; 450 451 } 452 453 def SSECC : Operand<i8> { 454 let PrintMethod = "printSSECC"; 455 let OperandType = "OPERAND_IMMEDIATE"; 456 } 457 458 def AVXCC : Operand<i8> { 459 let PrintMethod = "printAVXCC"; 460 let OperandType = "OPERAND_IMMEDIATE"; 461 } 462 463 class ImmSExtAsmOperandClass : AsmOperandClass { 464 let SuperClasses = [ImmAsmOperand]; 465 let RenderMethod = "addImmOperands"; 466 } 467 468 class ImmZExtAsmOperandClass : AsmOperandClass { 469 let SuperClasses = [ImmAsmOperand]; 470 let RenderMethod = "addImmOperands"; 471 } 472 473 // Sign-extended immediate classes. We don't need to define the full lattice 474 // here because there is no instruction with an ambiguity between ImmSExti64i32 475 // and ImmSExti32i8. 476 // 477 // The strange ranges come from the fact that the assembler always works with 478 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 479 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 480 481 // [0, 0x7FFFFFFF] | 482 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 483 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 484 let Name = "ImmSExti64i32"; 485 } 486 487 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 488 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 489 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 490 let Name = "ImmSExti16i8"; 491 let SuperClasses = [ImmSExti64i32AsmOperand]; 492 } 493 494 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 495 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 496 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 497 let Name = "ImmSExti32i8"; 498 } 499 500 // [0, 0x000000FF] 501 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass { 502 let Name = "ImmZExtu32u8"; 503 } 504 505 506 // [0, 0x0000007F] | 507 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 508 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 509 let Name = "ImmSExti64i8"; 510 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 511 ImmSExti64i32AsmOperand]; 512 } 513 514 // A couple of more descriptive operand definitions. 515 // 16-bits but only 8 bits are significant. 516 def i16i8imm : Operand<i16> { 517 let ParserMatchClass = ImmSExti16i8AsmOperand; 518 let OperandType = "OPERAND_IMMEDIATE"; 519 } 520 // 32-bits but only 8 bits are significant. 521 def i32i8imm : Operand<i32> { 522 let ParserMatchClass = ImmSExti32i8AsmOperand; 523 let OperandType = "OPERAND_IMMEDIATE"; 524 } 525 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned. 526 def u32u8imm : Operand<i32> { 527 let ParserMatchClass = ImmZExtu32u8AsmOperand; 528 let OperandType = "OPERAND_IMMEDIATE"; 529 } 530 531 // 64-bits but only 32 bits are significant. 532 def i64i32imm : Operand<i64> { 533 let ParserMatchClass = ImmSExti64i32AsmOperand; 534 let OperandType = "OPERAND_IMMEDIATE"; 535 } 536 537 // 64-bits but only 32 bits are significant, and those bits are treated as being 538 // pc relative. 539 def i64i32imm_pcrel : Operand<i64> { 540 let PrintMethod = "printPCRelImm"; 541 let ParserMatchClass = X86AbsMemAsmOperand; 542 let OperandType = "OPERAND_PCREL"; 543 } 544 545 // 64-bits but only 8 bits are significant. 546 def i64i8imm : Operand<i64> { 547 let ParserMatchClass = ImmSExti64i8AsmOperand; 548 let OperandType = "OPERAND_IMMEDIATE"; 549 } 550 551 def lea64_32mem : Operand<i32> { 552 let PrintMethod = "printi32mem"; 553 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 554 let ParserMatchClass = X86MemAsmOperand; 555 } 556 557 // Memory operands that use 64-bit pointers in both ILP32 and LP64. 558 def lea64mem : Operand<i64> { 559 let PrintMethod = "printi64mem"; 560 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 561 let ParserMatchClass = X86MemAsmOperand; 562 } 563 564 565 //===----------------------------------------------------------------------===// 566 // X86 Complex Pattern Definitions. 567 // 568 569 // Define X86 specific addressing mode. 570 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 571 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 572 [add, sub, mul, X86mul_imm, shl, or, frameindex], 573 []>; 574 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 575 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr", 576 [add, sub, mul, X86mul_imm, shl, or, 577 frameindex, X86WrapperRIP], 578 []>; 579 580 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 581 [tglobaltlsaddr], []>; 582 583 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 584 [tglobaltlsaddr], []>; 585 586 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 587 [add, sub, mul, X86mul_imm, shl, or, frameindex, 588 X86WrapperRIP], []>; 589 590 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 591 [tglobaltlsaddr], []>; 592 593 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 594 [tglobaltlsaddr], []>; 595 596 //===----------------------------------------------------------------------===// 597 // X86 Instruction Predicate Definitions. 598 def HasCMov : Predicate<"Subtarget->hasCMov()">; 599 def NoCMov : Predicate<"!Subtarget->hasCMov()">; 600 601 def HasMMX : Predicate<"Subtarget->hasMMX()">; 602 def Has3DNow : Predicate<"Subtarget->has3DNow()">; 603 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 604 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 605 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 606 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 607 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 608 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 609 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 610 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 611 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 612 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 613 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 614 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 615 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 616 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 617 def HasAVX : Predicate<"Subtarget->hasAVX()">; 618 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 619 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 620 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; 621 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 622 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 623 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 624 def HasCDI : Predicate<"Subtarget->hasCDI()">; 625 def HasPFI : Predicate<"Subtarget->hasPFI()">; 626 def HasEMI : Predicate<"Subtarget->hasERI()">; 627 628 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 629 def HasAES : Predicate<"Subtarget->hasAES()">; 630 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 631 def HasFMA : Predicate<"Subtarget->hasFMA()">; 632 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; 633 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 634 def HasXOP : Predicate<"Subtarget->hasXOP()">; 635 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 636 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 637 def HasF16C : Predicate<"Subtarget->hasF16C()">; 638 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 639 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 640 def HasBMI : Predicate<"Subtarget->hasBMI()">; 641 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 642 def HasRTM : Predicate<"Subtarget->hasRTM()">; 643 def HasHLE : Predicate<"Subtarget->hasHLE()">; 644 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; 645 def HasADX : Predicate<"Subtarget->hasADX()">; 646 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 647 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 648 def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">; 649 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 650 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 651 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 652 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, 653 AssemblerPredicate<"!Mode64Bit", "32-bit mode">; 654 def In64BitMode : Predicate<"Subtarget->is64Bit()">, 655 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 656 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 657 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 658 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 659 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 660 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 661 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 662 "TM.getCodeModel() != CodeModel::Kernel">; 663 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 664 "TM.getCodeModel() == CodeModel::Kernel">; 665 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 666 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 667 def OptForSize : Predicate<"OptForSize">; 668 def OptForSpeed : Predicate<"!OptForSize">; 669 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 670 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 671 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; 672 673 //===----------------------------------------------------------------------===// 674 // X86 Instruction Format Definitions. 675 // 676 677 include "X86InstrFormats.td" 678 679 //===----------------------------------------------------------------------===// 680 // Pattern fragments. 681 // 682 683 // X86 specific condition code. These correspond to CondCode in 684 // X86InstrInfo.h. They must be kept in synch. 685 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 686 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 687 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 688 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 689 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 690 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 691 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 692 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 693 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 694 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 695 def X86_COND_NO : PatLeaf<(i8 10)>; 696 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 697 def X86_COND_NS : PatLeaf<(i8 12)>; 698 def X86_COND_O : PatLeaf<(i8 13)>; 699 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 700 def X86_COND_S : PatLeaf<(i8 15)>; 701 702 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. 703 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 704 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 705 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 706 } 707 708 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 709 710 711 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 712 // unsigned field. 713 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 714 715 def i64immZExt32SExt8 : ImmLeaf<i64, [{ 716 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 717 }]>; 718 719 // Helper fragments for loads. 720 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is 721 // known to be 32-bit aligned or better. Ditto for i8 to i16. 722 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 723 LoadSDNode *LD = cast<LoadSDNode>(N); 724 ISD::LoadExtType ExtType = LD->getExtensionType(); 725 if (ExtType == ISD::NON_EXTLOAD) 726 return true; 727 if (ExtType == ISD::EXTLOAD) 728 return LD->getAlignment() >= 2 && !LD->isVolatile(); 729 return false; 730 }]>; 731 732 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 733 LoadSDNode *LD = cast<LoadSDNode>(N); 734 ISD::LoadExtType ExtType = LD->getExtensionType(); 735 if (ExtType == ISD::EXTLOAD) 736 return LD->getAlignment() >= 2 && !LD->isVolatile(); 737 return false; 738 }]>; 739 740 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 741 LoadSDNode *LD = cast<LoadSDNode>(N); 742 ISD::LoadExtType ExtType = LD->getExtensionType(); 743 if (ExtType == ISD::NON_EXTLOAD) 744 return true; 745 if (ExtType == ISD::EXTLOAD) 746 return LD->getAlignment() >= 4 && !LD->isVolatile(); 747 return false; 748 }]>; 749 750 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 751 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 752 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 753 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 754 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 755 756 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 757 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 758 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 759 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 760 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 761 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 762 763 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 764 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 765 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 766 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 767 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 768 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 769 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 770 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 771 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 772 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 773 774 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 775 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 776 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 777 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 778 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 779 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 780 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 781 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 782 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 783 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 784 785 786 // An 'and' node with a single use. 787 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 788 return N->hasOneUse(); 789 }]>; 790 // An 'srl' node with a single use. 791 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 792 return N->hasOneUse(); 793 }]>; 794 // An 'trunc' node with a single use. 795 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 796 return N->hasOneUse(); 797 }]>; 798 799 //===----------------------------------------------------------------------===// 800 // Instruction list. 801 // 802 803 // Nop 804 let neverHasSideEffects = 1, SchedRW = [WriteZero] in { 805 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; 806 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero), 807 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize; 808 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), 809 "nop{l}\t$zero", [], IIC_NOP>, TB; 810 } 811 812 813 // Constructing a stack frame. 814 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 815 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; 816 817 let SchedRW = [WriteALU] in { 818 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in 819 def LEAVE : I<0xC9, RawFrm, 820 (outs), (ins), "leave", [], IIC_LEAVE>, 821 Requires<[In32BitMode]>; 822 823 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in 824 def LEAVE64 : I<0xC9, RawFrm, 825 (outs), (ins), "leave", [], IIC_LEAVE>, 826 Requires<[In64BitMode]>; 827 } // SchedRW 828 829 //===----------------------------------------------------------------------===// 830 // Miscellaneous Instructions. 831 // 832 833 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { 834 let mayLoad = 1, SchedRW = [WriteLoad] in { 835 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 836 IIC_POP_REG16>, OpSize; 837 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 838 IIC_POP_REG>; 839 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 840 IIC_POP_REG>, OpSize; 841 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], 842 IIC_POP_MEM>, OpSize; 843 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 844 IIC_POP_REG>; 845 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], 846 IIC_POP_MEM>; 847 848 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize; 849 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, 850 Requires<[In32BitMode]>; 851 } // mayLoad, SchedRW 852 853 let mayStore = 1, SchedRW = [WriteStore] in { 854 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 855 IIC_PUSH_REG>, OpSize; 856 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 857 IIC_PUSH_REG>; 858 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 859 IIC_PUSH_REG>, OpSize; 860 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], 861 IIC_PUSH_MEM>, 862 OpSize; 863 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 864 IIC_PUSH_REG>; 865 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], 866 IIC_PUSH_MEM>; 867 868 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 869 "push{l}\t$imm", [], IIC_PUSH_IMM>; 870 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 871 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize; 872 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 873 "push{l}\t$imm", [], IIC_PUSH_IMM>; 874 875 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, 876 OpSize; 877 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, 878 Requires<[In32BitMode]>; 879 880 } // mayStore, SchedRW 881 } 882 883 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { 884 let mayLoad = 1, SchedRW = [WriteLoad] in { 885 def POP64r : I<0x58, AddRegFrm, 886 (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>; 887 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 888 IIC_POP_REG>; 889 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], 890 IIC_POP_MEM>; 891 } // mayLoad, SchedRW 892 let mayStore = 1, SchedRW = [WriteStore] in { 893 def PUSH64r : I<0x50, AddRegFrm, 894 (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>; 895 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 896 IIC_PUSH_REG>; 897 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], 898 IIC_PUSH_MEM>; 899 } // mayStore, SchedRW 900 } 901 902 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1, 903 SchedRW = [WriteStore] in { 904 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 905 "push{q}\t$imm", [], IIC_PUSH_IMM>; 906 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 907 "push{q}\t$imm", [], IIC_PUSH_IMM>; 908 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 909 "push{q}\t$imm", [], IIC_PUSH_IMM>; 910 } 911 912 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in 913 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, 914 Requires<[In64BitMode]>, Sched<[WriteLoad]>; 915 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in 916 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, 917 Requires<[In64BitMode]>, Sched<[WriteStore]>; 918 919 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 920 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in { 921 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>, 922 Requires<[In32BitMode]>; 923 } 924 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 925 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in { 926 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>, 927 Requires<[In32BitMode]>; 928 } 929 930 let Constraints = "$src = $dst", SchedRW = [WriteALU] in { 931 // GR32 = bswap GR32 932 def BSWAP32r : I<0xC8, AddRegFrm, 933 (outs GR32:$dst), (ins GR32:$src), 934 "bswap{l}\t$dst", 935 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB; 936 937 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 938 "bswap{q}\t$dst", 939 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; 940 } // Constraints = "$src = $dst", SchedRW 941 942 // Bit scan instructions. 943 let Defs = [EFLAGS] in { 944 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 945 "bsf{w}\t{$src, $dst|$dst, $src}", 946 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], 947 IIC_BSF>, TB, OpSize, Sched<[WriteShift]>; 948 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 949 "bsf{w}\t{$src, $dst|$dst, $src}", 950 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], 951 IIC_BSF>, TB, OpSize, Sched<[WriteShiftLd]>; 952 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 953 "bsf{l}\t{$src, $dst|$dst, $src}", 954 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB, 955 Sched<[WriteShift]>; 956 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 957 "bsf{l}\t{$src, $dst|$dst, $src}", 958 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], 959 IIC_BSF>, TB, Sched<[WriteShiftLd]>; 960 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 961 "bsf{q}\t{$src, $dst|$dst, $src}", 962 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], 963 IIC_BSF>, TB, Sched<[WriteShift]>; 964 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 965 "bsf{q}\t{$src, $dst|$dst, $src}", 966 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], 967 IIC_BSF>, TB, Sched<[WriteShiftLd]>; 968 969 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 970 "bsr{w}\t{$src, $dst|$dst, $src}", 971 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>, 972 TB, OpSize, Sched<[WriteShift]>; 973 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 974 "bsr{w}\t{$src, $dst|$dst, $src}", 975 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], 976 IIC_BSR>, TB, 977 OpSize, Sched<[WriteShiftLd]>; 978 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 979 "bsr{l}\t{$src, $dst|$dst, $src}", 980 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB, 981 Sched<[WriteShift]>; 982 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 983 "bsr{l}\t{$src, $dst|$dst, $src}", 984 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], 985 IIC_BSR>, TB, Sched<[WriteShiftLd]>; 986 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 987 "bsr{q}\t{$src, $dst|$dst, $src}", 988 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB, 989 Sched<[WriteShift]>; 990 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 991 "bsr{q}\t{$src, $dst|$dst, $src}", 992 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], 993 IIC_BSR>, TB, Sched<[WriteShiftLd]>; 994 } // Defs = [EFLAGS] 995 996 let SchedRW = [WriteMicrocoded] in { 997 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 998 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 999 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>; 1000 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize; 1001 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>; 1002 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>; 1003 } 1004 1005 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1006 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 1007 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>; 1008 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 1009 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize; 1010 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 1011 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>; 1012 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 1013 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>; 1014 1015 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>; 1016 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize; 1017 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>; 1018 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>; 1019 1020 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>; 1021 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize; 1022 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>; 1023 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>; 1024 } // SchedRW 1025 1026 //===----------------------------------------------------------------------===// 1027 // Move Instructions. 1028 // 1029 let SchedRW = [WriteMove] in { 1030 let neverHasSideEffects = 1 in { 1031 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1032 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1033 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1034 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize; 1035 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1036 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1037 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1038 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1039 } 1040 1041 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1042 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1043 "mov{b}\t{$src, $dst|$dst, $src}", 1044 [(set GR8:$dst, imm:$src)], IIC_MOV>; 1045 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1046 "mov{w}\t{$src, $dst|$dst, $src}", 1047 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize; 1048 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1049 "mov{l}\t{$src, $dst|$dst, $src}", 1050 [(set GR32:$dst, imm:$src)], IIC_MOV>; 1051 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1052 "movabs{q}\t{$src, $dst|$dst, $src}", 1053 [(set GR64:$dst, imm:$src)], IIC_MOV>; 1054 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1055 "mov{q}\t{$src, $dst|$dst, $src}", 1056 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; 1057 } 1058 } // SchedRW 1059 1060 let SchedRW = [WriteStore] in { 1061 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1062 "mov{b}\t{$src, $dst|$dst, $src}", 1063 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>; 1064 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1065 "mov{w}\t{$src, $dst|$dst, $src}", 1066 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize; 1067 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1068 "mov{l}\t{$src, $dst|$dst, $src}", 1069 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>; 1070 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1071 "mov{q}\t{$src, $dst|$dst, $src}", 1072 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; 1073 } // SchedRW 1074 1075 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a 1076 /// 32-bit offset from the PC. These are only valid in x86-32 mode. 1077 let SchedRW = [WriteALU] in { 1078 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src), 1079 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1080 Requires<[In32BitMode]>; 1081 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src), 1082 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize, 1083 Requires<[In32BitMode]>; 1084 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), 1085 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1086 Requires<[In32BitMode]>; 1087 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins), 1088 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, 1089 Requires<[In32BitMode]>; 1090 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins), 1091 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize, 1092 Requires<[In32BitMode]>; 1093 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), 1094 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1095 Requires<[In32BitMode]>; 1096 } 1097 1098 // These forms all have full 64-bit absolute addresses in their instructions 1099 // and use the movabs mnemonic to indicate this specific form. 1100 def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset64:$src), 1101 "movabs{b}\t{$src, %al|al, $src}", []>, 1102 Requires<[In64BitMode]>; 1103 def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src), 1104 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize, 1105 Requires<[In64BitMode]>; 1106 def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src), 1107 "movabs{l}\t{$src, %eax|eax, $src}", []>, 1108 Requires<[In64BitMode]>; 1109 def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src), 1110 "movabs{q}\t{$src, %rax|rax, $src}", []>, 1111 Requires<[In64BitMode]>; 1112 1113 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset64:$dst), (ins), 1114 "movabs{b}\t{%al, $dst|$dst, al}", []>, 1115 Requires<[In64BitMode]>; 1116 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins), 1117 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize, 1118 Requires<[In64BitMode]>; 1119 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins), 1120 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, 1121 Requires<[In64BitMode]>; 1122 def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins), 1123 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 1124 Requires<[In64BitMode]>; 1125 1126 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in { 1127 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1128 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1129 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1130 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize; 1131 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1132 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1133 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1134 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1135 } 1136 1137 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1138 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1139 "mov{b}\t{$src, $dst|$dst, $src}", 1140 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; 1141 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1142 "mov{w}\t{$src, $dst|$dst, $src}", 1143 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize; 1144 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1145 "mov{l}\t{$src, $dst|$dst, $src}", 1146 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>; 1147 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1148 "mov{q}\t{$src, $dst|$dst, $src}", 1149 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; 1150 } 1151 1152 let SchedRW = [WriteStore] in { 1153 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1154 "mov{b}\t{$src, $dst|$dst, $src}", 1155 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; 1156 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1157 "mov{w}\t{$src, $dst|$dst, $src}", 1158 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize; 1159 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1160 "mov{l}\t{$src, $dst|$dst, $src}", 1161 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>; 1162 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1163 "mov{q}\t{$src, $dst|$dst, $src}", 1164 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; 1165 } // SchedRW 1166 1167 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1168 // that they can be used for copying and storing h registers, which can't be 1169 // encoded when a REX prefix is present. 1170 let isCodeGenOnly = 1 in { 1171 let neverHasSideEffects = 1 in 1172 def MOV8rr_NOREX : I<0x88, MRMDestReg, 1173 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1174 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, 1175 Sched<[WriteMove]>; 1176 let mayStore = 1 in 1177 def MOV8mr_NOREX : I<0x88, MRMDestMem, 1178 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1179 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1180 IIC_MOV_MEM>, Sched<[WriteStore]>; 1181 let mayLoad = 1, neverHasSideEffects = 1, 1182 canFoldAsLoad = 1, isReMaterializable = 1 in 1183 def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1184 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1185 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1186 IIC_MOV_MEM>, Sched<[WriteLoad]>; 1187 } 1188 1189 1190 // Condition code ops, incl. set if equal/not equal/... 1191 let SchedRW = [WriteALU] in { 1192 let Defs = [EFLAGS], Uses = [AH] in 1193 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1194 [(set EFLAGS, (X86sahf AH))], IIC_AHF>; 1195 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in 1196 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], 1197 IIC_AHF>; // AH = flags 1198 } // SchedRW 1199 1200 //===----------------------------------------------------------------------===// 1201 // Bit tests instructions: BT, BTS, BTR, BTC. 1202 1203 let Defs = [EFLAGS] in { 1204 let SchedRW = [WriteALU] in { 1205 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1206 "bt{w}\t{$src2, $src1|$src1, $src2}", 1207 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, 1208 OpSize, TB; 1209 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1210 "bt{l}\t{$src2, $src1|$src1, $src2}", 1211 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB; 1212 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1213 "bt{q}\t{$src2, $src1|$src1, $src2}", 1214 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; 1215 } // SchedRW 1216 1217 // Unlike with the register+register form, the memory+register form of the 1218 // bt instruction does not ignore the high bits of the index. From ISel's 1219 // perspective, this is pretty bizarre. Make these instructions disassembly 1220 // only for now. 1221 1222 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1223 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1224 "bt{w}\t{$src2, $src1|$src1, $src2}", 1225 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1226 // (implicit EFLAGS)] 1227 [], IIC_BT_MR 1228 >, OpSize, TB, Requires<[FastBTMem]>; 1229 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1230 "bt{l}\t{$src2, $src1|$src1, $src2}", 1231 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1232 // (implicit EFLAGS)] 1233 [], IIC_BT_MR 1234 >, TB, Requires<[FastBTMem]>; 1235 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1236 "bt{q}\t{$src2, $src1|$src1, $src2}", 1237 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1238 // (implicit EFLAGS)] 1239 [], IIC_BT_MR 1240 >, TB; 1241 } 1242 1243 let SchedRW = [WriteALU] in { 1244 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1245 "bt{w}\t{$src2, $src1|$src1, $src2}", 1246 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], 1247 IIC_BT_RI>, OpSize, TB; 1248 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1249 "bt{l}\t{$src2, $src1|$src1, $src2}", 1250 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], 1251 IIC_BT_RI>, TB; 1252 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1253 "bt{q}\t{$src2, $src1|$src1, $src2}", 1254 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], 1255 IIC_BT_RI>, TB; 1256 } // SchedRW 1257 1258 // Note that these instructions don't need FastBTMem because that 1259 // only applies when the other operand is in a register. When it's 1260 // an immediate, bt is still fast. 1261 let SchedRW = [WriteALU] in { 1262 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1263 "bt{w}\t{$src2, $src1|$src1, $src2}", 1264 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1265 ], IIC_BT_MI>, OpSize, TB; 1266 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1267 "bt{l}\t{$src2, $src1|$src1, $src2}", 1268 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1269 ], IIC_BT_MI>, TB; 1270 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1271 "bt{q}\t{$src2, $src1|$src1, $src2}", 1272 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1273 i64immSExt8:$src2))], IIC_BT_MI>, TB; 1274 } // SchedRW 1275 1276 let hasSideEffects = 0 in { 1277 let SchedRW = [WriteALU] in { 1278 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1279 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1280 OpSize, TB; 1281 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1282 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1283 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1284 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1285 } // SchedRW 1286 1287 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1288 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1289 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1290 OpSize, TB; 1291 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1292 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1293 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1294 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1295 } 1296 1297 let SchedRW = [WriteALU] in { 1298 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1299 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1300 OpSize, TB; 1301 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1302 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1303 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1304 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1305 } // SchedRW 1306 1307 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1308 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1309 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1310 OpSize, TB; 1311 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1312 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1313 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1314 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1315 } 1316 1317 let SchedRW = [WriteALU] in { 1318 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1319 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1320 OpSize, TB; 1321 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1322 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1323 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1324 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1325 } // SchedRW 1326 1327 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1328 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1329 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1330 OpSize, TB; 1331 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1332 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1333 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1334 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1335 } 1336 1337 let SchedRW = [WriteALU] in { 1338 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1339 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1340 OpSize, TB; 1341 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1342 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1343 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1344 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1345 } // SchedRW 1346 1347 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1348 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1349 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1350 OpSize, TB; 1351 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1352 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1353 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1354 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1355 } 1356 1357 let SchedRW = [WriteALU] in { 1358 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1359 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1360 OpSize, TB; 1361 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1362 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1363 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1364 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1365 } // SchedRW 1366 1367 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1368 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1369 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1370 OpSize, TB; 1371 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1372 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1373 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1374 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1375 } 1376 1377 let SchedRW = [WriteALU] in { 1378 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1379 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1380 OpSize, TB; 1381 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1382 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1383 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1384 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1385 } // SchedRW 1386 1387 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1388 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1389 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1390 OpSize, TB; 1391 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1392 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1393 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1394 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1395 } 1396 } // hasSideEffects = 0 1397 } // Defs = [EFLAGS] 1398 1399 1400 //===----------------------------------------------------------------------===// 1401 // Atomic support 1402 // 1403 1404 // Atomic swap. These are just normal xchg instructions. But since a memory 1405 // operand is referenced, the atomicity is ensured. 1406 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, 1407 InstrItinClass itin> { 1408 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 1409 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 1410 (ins GR8:$val, i8mem:$ptr), 1411 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1412 [(set 1413 GR8:$dst, 1414 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 1415 itin>; 1416 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 1417 (ins GR16:$val, i16mem:$ptr), 1418 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1419 [(set 1420 GR16:$dst, 1421 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 1422 itin>, OpSize; 1423 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 1424 (ins GR32:$val, i32mem:$ptr), 1425 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1426 [(set 1427 GR32:$dst, 1428 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 1429 itin>; 1430 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 1431 (ins GR64:$val, i64mem:$ptr), 1432 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1433 [(set 1434 GR64:$dst, 1435 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 1436 itin>; 1437 } 1438 } 1439 1440 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; 1441 1442 // Swap between registers. 1443 let SchedRW = [WriteALU] in { 1444 let Constraints = "$val = $dst" in { 1445 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1446 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1447 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1448 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize; 1449 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1450 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1451 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1452 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1453 } 1454 1455 // Swap between EAX and other registers. 1456 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1457 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize; 1458 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1459 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1460 Requires<[In32BitMode]>; 1461 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1462 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1463 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1464 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1465 Requires<[In64BitMode]>; 1466 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1467 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; 1468 } // SchedRW 1469 1470 let SchedRW = [WriteALU] in { 1471 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1472 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1473 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1474 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1475 OpSize; 1476 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1477 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1478 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1479 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1480 } // SchedRW 1481 1482 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1483 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1484 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1485 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1486 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1487 OpSize; 1488 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1489 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1490 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1491 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1492 1493 } 1494 1495 let SchedRW = [WriteALU] in { 1496 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1497 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1498 IIC_CMPXCHG_REG8>, TB; 1499 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1500 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1501 IIC_CMPXCHG_REG>, TB, OpSize; 1502 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1503 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1504 IIC_CMPXCHG_REG>, TB; 1505 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1506 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1507 IIC_CMPXCHG_REG>, TB; 1508 } // SchedRW 1509 1510 let SchedRW = [WriteALULd, WriteRMW] in { 1511 let mayLoad = 1, mayStore = 1 in { 1512 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1513 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1514 IIC_CMPXCHG_MEM8>, TB; 1515 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1516 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1517 IIC_CMPXCHG_MEM>, TB, OpSize; 1518 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1519 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1520 IIC_CMPXCHG_MEM>, TB; 1521 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1522 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1523 IIC_CMPXCHG_MEM>, TB; 1524 } 1525 1526 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1527 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1528 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; 1529 1530 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1531 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1532 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, 1533 TB, Requires<[HasCmpxchg16b]>; 1534 } // SchedRW 1535 1536 1537 // Lock instruction prefix 1538 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1539 1540 // Rex64 instruction prefix 1541 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>; 1542 1543 // Data16 instruction prefix 1544 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1545 1546 // Repeat string operation instruction prefixes 1547 // These uses the DF flag in the EFLAGS register to inc or dec ECX 1548 let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1549 // Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1550 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1551 // Repeat while not equal (used with CMPS and SCAS) 1552 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1553 } 1554 1555 1556 // String manipulation instructions 1557 let SchedRW = [WriteMicrocoded] in { 1558 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>; 1559 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize; 1560 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>; 1561 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>; 1562 } 1563 1564 let SchedRW = [WriteSystem] in { 1565 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>; 1566 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize; 1567 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>; 1568 } 1569 1570 // Flag instructions 1571 let SchedRW = [WriteALU] in { 1572 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; 1573 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; 1574 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; 1575 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; 1576 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; 1577 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; 1578 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; 1579 1580 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; 1581 } 1582 1583 // Table lookup instructions 1584 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, 1585 Sched<[WriteLoad]>; 1586 1587 let SchedRW = [WriteMicrocoded] in { 1588 // ASCII Adjust After Addition 1589 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1590 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, 1591 Requires<[In32BitMode]>; 1592 1593 // ASCII Adjust AX Before Division 1594 // sets AL, AH and EFLAGS and uses AL and AH 1595 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1596 "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>; 1597 1598 // ASCII Adjust AX After Multiply 1599 // sets AL, AH and EFLAGS and uses AL 1600 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1601 "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>; 1602 1603 // ASCII Adjust AL After Subtraction - sets 1604 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1605 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, 1606 Requires<[In32BitMode]>; 1607 1608 // Decimal Adjust AL after Addition 1609 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1610 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, 1611 Requires<[In32BitMode]>; 1612 1613 // Decimal Adjust AL after Subtraction 1614 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1615 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, 1616 Requires<[In32BitMode]>; 1617 } // SchedRW 1618 1619 let SchedRW = [WriteSystem] in { 1620 // Check Array Index Against Bounds 1621 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1622 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize, 1623 Requires<[In32BitMode]>; 1624 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1625 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, 1626 Requires<[In32BitMode]>; 1627 1628 // Adjust RPL Field of Segment Selector 1629 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1630 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, 1631 Requires<[In32BitMode]>; 1632 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1633 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, 1634 Requires<[In32BitMode]>; 1635 } // SchedRW 1636 1637 //===----------------------------------------------------------------------===// 1638 // MOVBE Instructions 1639 // 1640 let Predicates = [HasMOVBE] in { 1641 let SchedRW = [WriteALULd] in { 1642 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1643 "movbe{w}\t{$src, $dst|$dst, $src}", 1644 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, 1645 OpSize, T8; 1646 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1647 "movbe{l}\t{$src, $dst|$dst, $src}", 1648 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, 1649 T8; 1650 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1651 "movbe{q}\t{$src, $dst|$dst, $src}", 1652 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, 1653 T8; 1654 } 1655 let SchedRW = [WriteStore] in { 1656 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1657 "movbe{w}\t{$src, $dst|$dst, $src}", 1658 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, 1659 OpSize, T8; 1660 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1661 "movbe{l}\t{$src, $dst|$dst, $src}", 1662 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, 1663 T8; 1664 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1665 "movbe{q}\t{$src, $dst|$dst, $src}", 1666 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, 1667 T8; 1668 } 1669 } 1670 1671 //===----------------------------------------------------------------------===// 1672 // RDRAND Instruction 1673 // 1674 let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 1675 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1676 "rdrand{w}\t$dst", 1677 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB; 1678 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1679 "rdrand{l}\t$dst", 1680 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB; 1681 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1682 "rdrand{q}\t$dst", 1683 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; 1684 } 1685 1686 //===----------------------------------------------------------------------===// 1687 // RDSEED Instruction 1688 // 1689 let Predicates = [HasRDSEED], Defs = [EFLAGS] in { 1690 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), 1691 "rdseed{w}\t$dst", 1692 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB; 1693 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 1694 "rdseed{l}\t$dst", 1695 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, TB; 1696 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), 1697 "rdseed{q}\t$dst", 1698 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB; 1699 } 1700 1701 //===----------------------------------------------------------------------===// 1702 // LZCNT Instruction 1703 // 1704 let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 1705 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1706 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1707 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 1708 OpSize; 1709 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1710 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1711 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 1712 (implicit EFLAGS)]>, XS, OpSize; 1713 1714 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1715 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1716 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS; 1717 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1718 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1719 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 1720 (implicit EFLAGS)]>, XS; 1721 1722 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1723 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1724 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 1725 XS; 1726 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1727 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1728 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 1729 (implicit EFLAGS)]>, XS; 1730 } 1731 1732 //===----------------------------------------------------------------------===// 1733 // BMI Instructions 1734 // 1735 let Predicates = [HasBMI], Defs = [EFLAGS] in { 1736 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1737 "tzcnt{w}\t{$src, $dst|$dst, $src}", 1738 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 1739 OpSize; 1740 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1741 "tzcnt{w}\t{$src, $dst|$dst, $src}", 1742 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 1743 (implicit EFLAGS)]>, XS, OpSize; 1744 1745 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1746 "tzcnt{l}\t{$src, $dst|$dst, $src}", 1747 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS; 1748 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1749 "tzcnt{l}\t{$src, $dst|$dst, $src}", 1750 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 1751 (implicit EFLAGS)]>, XS; 1752 1753 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1754 "tzcnt{q}\t{$src, $dst|$dst, $src}", 1755 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 1756 XS; 1757 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1758 "tzcnt{q}\t{$src, $dst|$dst, $src}", 1759 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 1760 (implicit EFLAGS)]>, XS; 1761 } 1762 1763 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 1764 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode, 1765 PatFrag ld_frag> { 1766 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 1767 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 1768 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V; 1769 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 1770 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 1771 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>, 1772 T8, VEX_4V; 1773 } 1774 1775 let Predicates = [HasBMI], Defs = [EFLAGS] in { 1776 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, 1777 X86blsr, loadi32>; 1778 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, 1779 X86blsr, loadi64>, VEX_W; 1780 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, 1781 X86blsmsk, loadi32>; 1782 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, 1783 X86blsmsk, loadi64>, VEX_W; 1784 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, 1785 X86blsi, loadi32>; 1786 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, 1787 X86blsi, loadi64>, VEX_W; 1788 } 1789 1790 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 1791 X86MemOperand x86memop, Intrinsic Int, 1792 PatFrag ld_frag> { 1793 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1794 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1795 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 1796 T8, VEX_4VOp3; 1797 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 1798 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1799 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 1800 (implicit EFLAGS)]>, T8, VEX_4VOp3; 1801 } 1802 1803 let Predicates = [HasBMI], Defs = [EFLAGS] in { 1804 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 1805 int_x86_bmi_bextr_32, loadi32>; 1806 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 1807 int_x86_bmi_bextr_64, loadi64>, VEX_W; 1808 } 1809 1810 let Predicates = [HasBMI2], Defs = [EFLAGS] in { 1811 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 1812 int_x86_bmi_bzhi_32, loadi32>; 1813 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 1814 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 1815 } 1816 1817 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 1818 X86MemOperand x86memop, Intrinsic Int, 1819 PatFrag ld_frag> { 1820 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 1821 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1822 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 1823 VEX_4V; 1824 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 1825 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 1826 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 1827 } 1828 1829 let Predicates = [HasBMI2] in { 1830 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 1831 int_x86_bmi_pdep_32, loadi32>, T8XD; 1832 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 1833 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 1834 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 1835 int_x86_bmi_pext_32, loadi32>, T8XS; 1836 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 1837 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 1838 } 1839 1840 //===----------------------------------------------------------------------===// 1841 // Subsystems. 1842 //===----------------------------------------------------------------------===// 1843 1844 include "X86InstrArithmetic.td" 1845 include "X86InstrCMovSetCC.td" 1846 include "X86InstrExtension.td" 1847 include "X86InstrControl.td" 1848 include "X86InstrShiftRotate.td" 1849 1850 // X87 Floating Point Stack. 1851 include "X86InstrFPStack.td" 1852 1853 // SIMD support (SSE, MMX and AVX) 1854 include "X86InstrFragmentsSIMD.td" 1855 1856 // FMA - Fused Multiply-Add support (requires FMA) 1857 include "X86InstrFMA.td" 1858 1859 // XOP 1860 include "X86InstrXOP.td" 1861 1862 // SSE, MMX and 3DNow! vector support. 1863 include "X86InstrSSE.td" 1864 include "X86InstrAVX512.td" 1865 include "X86InstrMMX.td" 1866 include "X86Instr3DNow.td" 1867 1868 include "X86InstrVMX.td" 1869 include "X86InstrSVM.td" 1870 1871 include "X86InstrTSX.td" 1872 1873 // System instructions. 1874 include "X86InstrSystem.td" 1875 1876 // Compiler Pseudo Instructions and Pat Patterns 1877 include "X86InstrCompiler.td" 1878 1879 //===----------------------------------------------------------------------===// 1880 // Assembler Mnemonic Aliases 1881 //===----------------------------------------------------------------------===// 1882 1883 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 1884 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 1885 1886 def : MnemonicAlias<"cbw", "cbtw", "att">; 1887 def : MnemonicAlias<"cwde", "cwtl", "att">; 1888 def : MnemonicAlias<"cwd", "cwtd", "att">; 1889 def : MnemonicAlias<"cdq", "cltd", "att">; 1890 def : MnemonicAlias<"cdqe", "cltq", "att">; 1891 def : MnemonicAlias<"cqo", "cqto", "att">; 1892 1893 // lret maps to lretl, it is not ambiguous with lretq. 1894 def : MnemonicAlias<"lret", "lretl", "att">; 1895 1896 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[In32BitMode]>; 1897 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 1898 1899 def : MnemonicAlias<"loopz", "loope", "att">; 1900 def : MnemonicAlias<"loopnz", "loopne", "att">; 1901 1902 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 1903 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 1904 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 1905 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 1906 def : MnemonicAlias<"popfd", "popfl", "att">; 1907 1908 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 1909 // all modes. However: "push (addr)" and "push $42" should default to 1910 // pushl/pushq depending on the current mode. Similar for "pop %bx" 1911 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 1912 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 1913 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 1914 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1915 def : MnemonicAlias<"pushfd", "pushfl", "att">; 1916 1917 def : MnemonicAlias<"popad", "popa", "intel">, Requires<[In32BitMode]>; 1918 def : MnemonicAlias<"pushad", "pusha", "intel">, Requires<[In32BitMode]>; 1919 1920 def : MnemonicAlias<"repe", "rep", "att">; 1921 def : MnemonicAlias<"repz", "rep", "att">; 1922 def : MnemonicAlias<"repnz", "repne", "att">; 1923 1924 def : MnemonicAlias<"retl", "ret", "att">, Requires<[In32BitMode]>; 1925 def : MnemonicAlias<"retq", "ret", "att">, Requires<[In64BitMode]>; 1926 1927 def : MnemonicAlias<"salb", "shlb", "att">; 1928 def : MnemonicAlias<"salw", "shlw", "att">; 1929 def : MnemonicAlias<"sall", "shll", "att">; 1930 def : MnemonicAlias<"salq", "shlq", "att">; 1931 1932 def : MnemonicAlias<"smovb", "movsb", "att">; 1933 def : MnemonicAlias<"smovw", "movsw", "att">; 1934 def : MnemonicAlias<"smovl", "movsl", "att">; 1935 def : MnemonicAlias<"smovq", "movsq", "att">; 1936 1937 def : MnemonicAlias<"ud2a", "ud2", "att">; 1938 def : MnemonicAlias<"verrw", "verr", "att">; 1939 1940 // System instruction aliases. 1941 def : MnemonicAlias<"iret", "iretl", "att">; 1942 def : MnemonicAlias<"sysret", "sysretl", "att">; 1943 def : MnemonicAlias<"sysexit", "sysexitl", "att">; 1944 1945 def : MnemonicAlias<"lgdtl", "lgdt", "att">, Requires<[In32BitMode]>; 1946 def : MnemonicAlias<"lgdtq", "lgdt", "att">, Requires<[In64BitMode]>; 1947 def : MnemonicAlias<"lidtl", "lidt", "att">, Requires<[In32BitMode]>; 1948 def : MnemonicAlias<"lidtq", "lidt", "att">, Requires<[In64BitMode]>; 1949 def : MnemonicAlias<"sgdtl", "sgdt", "att">, Requires<[In32BitMode]>; 1950 def : MnemonicAlias<"sgdtq", "sgdt", "att">, Requires<[In64BitMode]>; 1951 def : MnemonicAlias<"sidtl", "sidt", "att">, Requires<[In32BitMode]>; 1952 def : MnemonicAlias<"sidtq", "sidt", "att">, Requires<[In64BitMode]>; 1953 1954 1955 // Floating point stack aliases. 1956 def : MnemonicAlias<"fcmovz", "fcmove", "att">; 1957 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 1958 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 1959 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 1960 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 1961 def : MnemonicAlias<"fcomip", "fcompi", "att">; 1962 def : MnemonicAlias<"fildq", "fildll", "att">; 1963 def : MnemonicAlias<"fistpq", "fistpll", "att">; 1964 def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 1965 def : MnemonicAlias<"fldcww", "fldcw", "att">; 1966 def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 1967 def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 1968 def : MnemonicAlias<"fucomip", "fucompi", "att">; 1969 def : MnemonicAlias<"fwait", "wait", "att">; 1970 1971 1972 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 1973 string VariantName> 1974 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 1975 !strconcat(Prefix, NewCond, Suffix), VariantName>; 1976 1977 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 1978 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 1979 /// example "setz" -> "sete". 1980 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 1981 string V = ""> { 1982 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 1983 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 1984 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 1985 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 1986 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 1987 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 1988 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 1989 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 1990 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 1991 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 1992 1993 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 1994 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 1995 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 1996 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 1997 } 1998 1999 // Aliases for set<CC> 2000 defm : IntegerCondCodeMnemonicAlias<"set", "">; 2001 // Aliases for j<CC> 2002 defm : IntegerCondCodeMnemonicAlias<"j", "">; 2003 // Aliases for cmov<CC>{w,l,q} 2004 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 2005 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 2006 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 2007 // No size suffix for intel-style asm. 2008 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 2009 2010 2011 //===----------------------------------------------------------------------===// 2012 // Assembler Instruction Aliases 2013 //===----------------------------------------------------------------------===// 2014 2015 // aad/aam default to base 10 if no operand is specified. 2016 def : InstAlias<"aad", (AAD8i8 10)>; 2017 def : InstAlias<"aam", (AAM8i8 10)>; 2018 2019 // Disambiguate the mem/imm form of bt-without-a-suffix as btl. 2020 // Likewise for btc/btr/bts. 2021 def : InstAlias<"bt {$imm, $mem|$mem, $imm}", 2022 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2023 def : InstAlias<"btc {$imm, $mem|$mem, $imm}", 2024 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2025 def : InstAlias<"btr {$imm, $mem|$mem, $imm}", 2026 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2027 def : InstAlias<"bts {$imm, $mem|$mem, $imm}", 2028 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2029 2030 // clr aliases. 2031 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 2032 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 2033 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 2034 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 2035 2036 // div and idiv aliases for explicit A register. 2037 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 2038 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 2039 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 2040 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 2041 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 2042 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 2043 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 2044 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 2045 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 2046 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 2047 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 2048 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 2049 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 2050 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 2051 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 2052 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 2053 2054 2055 2056 // Various unary fpstack operations default to operating on on ST1. 2057 // For example, "fxch" -> "fxch %st(1)" 2058 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 2059 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 2060 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 2061 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 2062 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 2063 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 2064 def : InstAlias<"fxch", (XCH_F ST1), 0>; 2065 def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 2066 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 2067 def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 2068 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 2069 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 2070 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 2071 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 2072 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 2073 2074 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 2075 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 2076 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 2077 // gas. 2078 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 2079 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 2080 (Inst RST:$op), EmitAlias>; 2081 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 2082 (Inst ST0), EmitAlias>; 2083 } 2084 2085 defm : FpUnaryAlias<"fadd", ADD_FST0r>; 2086 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 2087 defm : FpUnaryAlias<"fsub", SUB_FST0r>; 2088 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 2089 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 2090 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 2091 defm : FpUnaryAlias<"fmul", MUL_FST0r>; 2092 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 2093 defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 2094 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 2095 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 2096 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 2097 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 2098 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 2099 defm : FpUnaryAlias<"fcompi", COM_FIPr>; 2100 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 2101 2102 2103 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 2104 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 2105 // solely because gas supports it. 2106 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 2107 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 2108 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 2109 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 2110 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 2111 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 2112 2113 // We accept "fnstsw %eax" even though it only writes %ax. 2114 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>; 2115 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>; 2116 def : InstAlias<"fnstsw" , (FNSTSW16r)>; 2117 2118 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 2119 // this is compatible with what GAS does. 2120 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2121 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2122 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>; 2123 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>; 2124 2125 // "imul <imm>, B" is an alias for "imul <imm>, B, B". 2126 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; 2127 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; 2128 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; 2129 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; 2130 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; 2131 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; 2132 2133 // inb %dx -> inb %al, %dx 2134 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 2135 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 2136 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 2137 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>; 2138 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>; 2139 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>; 2140 2141 2142 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 2143 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2144 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2145 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 2146 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 2147 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2148 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2149 2150 // Force mov without a suffix with a segment and mem to prefer the 'l' form of 2151 // the move. All segment/mem forms are equivalent, this has the shortest 2152 // encoding. 2153 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>; 2154 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>; 2155 2156 // Match 'movq <largeimm>, <reg>' as an alias for movabsq. 2157 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>; 2158 2159 // Match 'movq GR64, MMX' as an alias for movd. 2160 def : InstAlias<"movq $src, $dst", 2161 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 2162 def : InstAlias<"movq $src, $dst", 2163 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 2164 2165 // movsd with no operands (as opposed to the SSE scalar move of a double) is an 2166 // alias for movsl. (as in rep; movsd) 2167 def : InstAlias<"movsd", (MOVSD), 0>; 2168 2169 // movsx aliases 2170 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 2171 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 2172 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 2173 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 2174 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 2175 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 2176 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 2177 2178 // movzx aliases 2179 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 2180 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 2181 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 2182 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 2183 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 2184 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 2185 // Note: No GR32->GR64 movzx form. 2186 2187 // outb %dx -> outb %al, %dx 2188 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 2189 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 2190 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 2191 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>; 2192 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>; 2193 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>; 2194 2195 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 2196 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 2197 // errors, since its encoding is the most compact. 2198 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; 2199 2200 // shld/shrd op,op -> shld op, op, CL 2201 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 2202 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 2203 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 2204 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 2205 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 2206 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 2207 2208 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 2209 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 2210 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 2211 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 2212 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 2213 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 2214 2215 /* FIXME: This is disabled because the asm matcher is currently incapable of 2216 * matching a fixed immediate like $1. 2217 // "shl X, $1" is an alias for "shl X". 2218 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 2219 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2220 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 2221 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2222 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 2223 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2224 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 2225 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2226 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 2227 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2228 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 2229 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2230 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 2231 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2232 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 2233 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2234 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 2235 } 2236 2237 defm : ShiftRotateByOneAlias<"rcl", "RCL">; 2238 defm : ShiftRotateByOneAlias<"rcr", "RCR">; 2239 defm : ShiftRotateByOneAlias<"rol", "ROL">; 2240 defm : ShiftRotateByOneAlias<"ror", "ROR">; 2241 FIXME */ 2242 2243 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 2244 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", (TEST8rm GR8 :$val, i8mem :$mem)>; 2245 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", (TEST16rm GR16:$val, i16mem:$mem)>; 2246 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", (TEST32rm GR32:$val, i32mem:$mem)>; 2247 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", (TEST64rm GR64:$val, i64mem:$mem)>; 2248 2249 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 2250 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", (XCHG8rm GR8 :$val, i8mem :$mem)>; 2251 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", (XCHG16rm GR16:$val, i16mem:$mem)>; 2252 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:$mem)>; 2253 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>; 2254 2255 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 2256 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>; 2257 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>; 2258 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>; 2259 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>; 2260
