| /external/chromium_org/third_party/skia/gyp/ |
| pixman_test.gyp | 95 '../../../pixman/pixman/pixman-sse2.c',
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/ |
| x86cpu.gperf | 311 sse2, x86_cpu_set, CPU_SSE2
|
| /external/chromium_org/v8/src/ |
| atomicops_internals_tsan.h | 49 bool has_sse2; // Processor has SSE2.
|
| /external/chromium_org/v8/src/ia32/ |
| macro-assembler-ia32.cc | 569 if (CpuFeatures::IsSupported(SSE2) && specialize_for_processor) {
570 CpuFeatureScope use_sse2(this, SSE2);
591 if (CpuFeatures::IsSupported(SSE2) && specialize_for_processor) {
592 CpuFeatureScope use_sse2(this, SSE2);
604 if (CpuFeatures::IsSupported(SSE2) && specialize_for_processor) {
605 CpuFeatureScope fscope(this, SSE2);
817 CpuFeatureScope scope(this, SSE2);
863 CpuFeatureScope scope(this, SSE2);
[all...] |
| /external/eigen/Eigen/src/Core/arch/SSE/ |
| MathFunctions.h | 165 /* evaluation of 4 sines at onces, using SSE2 intrinsics.
|
| /external/libvpx/libvpx/test/ |
| sixtap_predict_test.cc | 212 SSE2, SixtapPredictTest, ::testing::Values(
|
| /external/llvm/docs/HistoricalNotes/ |
| 2000-11-18-EarlyDesignIdeasResp.txt | 156 * Intel's SSE/SSE2
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 551 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
715 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
728 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
778 /// When SSE2 is available, use it for f64 operations.
[all...] |
| X86TargetTransformInfo.cpp | 201 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
333 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
|
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_screen.c | 450 /* require SSE2 due to LLVM PR6960. */
|
| /external/mesa3d/src/mesa/x86/rtasm/ |
| x86sse.h | 9 * for mmx/sse/sse2 support on the cpu.
|
| /external/qemu/target-i386/ |
| ops_sse_header.h | 2 * MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
|
| /external/skia/gyp/ |
| pixman_test.gyp | 95 '../../../pixman/pixman/pixman-sse2.c',
|
| /external/stressapptest/src/ |
| os.h | 270 bool has_sse2_; // Do we have sse2 instructions?
|
| /external/valgrind/main/ |
| NEWS | 220 273729 == 283000 (Illegal opcode for SSE2 "roundsd" instruction)
[all...] |
| /external/valgrind/main/docs/internals/ |
| release-HOWTO.txt | 61 x86, sse2 (P4)
|
| /external/chromium_org/skia/ext/ |
| convolver.cc | 434 // SSE2 can access up to 3 extra pixels past the end of the
467 // Check if we need to avoid SSE2 for this row.
|
| /external/chromium_org/third_party/mesa/src/scons/ |
| gallium.py | 424 #'/arch:SSE2', # use the SSE2 instructions
|
| /external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/gallivm/ |
| lp_bld_conv.c | 427 /* relying on clamping behavior of sse2 intrinsics here */
488 /* relying on clamping behavior of sse2 intrinsics here */
|
| /external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
| read_rgba_span_x86.S | 251 * functionality wasn't introduced until SSE2 with the MOVDQ2Q
337 * SSE2 optimized version of the BGRA8888_REV to RGBA copy routine.
|
| /external/chromium_org/third_party/openssl/openssl/crypto/rc4/asm/ |
| rc4-586.pl | 53 # is guarded by SSE2 bit (see below), not MMX/SSE.
192 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX]
|
| /external/chromium_org/third_party/skia/src/opts/ |
| SkBitmapProcState_opts_SSE2.cpp | 307 // SSE2 only support 16bit interger max & min, so only process the case
436 // SSE2 only support 16bit interger max & min, so only process the case
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/ |
| yasm_arch.xml | 123 extra general purpose registers, extra SSE2 registers, and
166 <para>In 64-bit mode, an additional 8 SSE2 registers are also
|
| /external/chromium_org/third_party/yasm/source/patched-yasm/ |
| yasm_arch.7 | 73 When an AMD64\-supporting processor is executing in 64\-bit mode, a number of additional extensions are available, including extra general purpose registers, extra SSE2 registers, and RIP\-relative addressing\&.
107 In 64\-bit mode, an additional 8 SSE2 registers are also available\&. These are named xmm8\-xmm15\&.
|
| /external/mesa3d/scons/ |
| gallium.py | 424 #'/arch:SSE2', # use the SSE2 instructions
|
