1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements a TargetTransformInfo analysis pass specific to the 11 /// X86 target machine. It uses the target's detailed information to provide 12 /// more precise answers to certain TTI queries, while letting the target 13 /// independent and default TTI implementations handle the rest. 14 /// 15 //===----------------------------------------------------------------------===// 16 17 #define DEBUG_TYPE "x86tti" 18 #include "X86.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Target/TargetLowering.h" 23 #include "llvm/Target/CostTable.h" 24 using namespace llvm; 25 26 // Declare the pass initialization routine locally as target-specific passes 27 // don't havve a target-wide initialization entry point, and so we rely on the 28 // pass constructor initialization. 29 namespace llvm { 30 void initializeX86TTIPass(PassRegistry &); 31 } 32 33 namespace { 34 35 class X86TTI : public ImmutablePass, public TargetTransformInfo { 36 const X86Subtarget *ST; 37 const X86TargetLowering *TLI; 38 39 /// Estimate the overhead of scalarizing an instruction. Insert and Extract 40 /// are set if the result needs to be inserted and/or extracted from vectors. 41 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const; 42 43 public: 44 X86TTI() : ImmutablePass(ID), ST(0), TLI(0) { 45 llvm_unreachable("This pass cannot be directly constructed"); 46 } 47 48 X86TTI(const X86TargetMachine *TM) 49 : ImmutablePass(ID), ST(TM->getSubtargetImpl()), 50 TLI(TM->getTargetLowering()) { 51 initializeX86TTIPass(*PassRegistry::getPassRegistry()); 52 } 53 54 virtual void initializePass() { 55 pushTTIStack(this); 56 } 57 58 virtual void finalizePass() { 59 popTTIStack(); 60 } 61 62 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 63 TargetTransformInfo::getAnalysisUsage(AU); 64 } 65 66 /// Pass identification. 67 static char ID; 68 69 /// Provide necessary pointer adjustments for the two base classes. 70 virtual void *getAdjustedAnalysisPointer(const void *ID) { 71 if (ID == &TargetTransformInfo::ID) 72 return (TargetTransformInfo*)this; 73 return this; 74 } 75 76 /// \name Scalar TTI Implementations 77 /// @{ 78 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const; 79 80 /// @} 81 82 /// \name Vector TTI Implementations 83 /// @{ 84 85 virtual unsigned getNumberOfRegisters(bool Vector) const; 86 virtual unsigned getRegisterBitWidth(bool Vector) const; 87 virtual unsigned getMaximumUnrollFactor() const; 88 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, 89 OperandValueKind, 90 OperandValueKind) const; 91 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp, 92 int Index, Type *SubTp) const; 93 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst, 94 Type *Src) const; 95 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 96 Type *CondTy) const; 97 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val, 98 unsigned Index) const; 99 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src, 100 unsigned Alignment, 101 unsigned AddressSpace) const; 102 103 virtual unsigned getAddressComputationCost(Type *PtrTy, bool IsComplex) const; 104 105 /// @} 106 }; 107 108 } // end anonymous namespace 109 110 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti", 111 "X86 Target Transform Info", true, true, false) 112 char X86TTI::ID = 0; 113 114 ImmutablePass * 115 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) { 116 return new X86TTI(TM); 117 } 118 119 120 //===----------------------------------------------------------------------===// 121 // 122 // X86 cost model. 123 // 124 //===----------------------------------------------------------------------===// 125 126 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const { 127 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 128 // TODO: Currently the __builtin_popcount() implementation using SSE3 129 // instructions is inefficient. Once the problem is fixed, we should 130 // call ST->hasSSE3() instead of ST->hasSSE4(). 131 return ST->hasSSE41() ? PSK_FastHardware : PSK_Software; 132 } 133 134 unsigned X86TTI::getNumberOfRegisters(bool Vector) const { 135 if (Vector && !ST->hasSSE1()) 136 return 0; 137 138 if (ST->is64Bit()) 139 return 16; 140 return 8; 141 } 142 143 unsigned X86TTI::getRegisterBitWidth(bool Vector) const { 144 if (Vector) { 145 if (ST->hasAVX()) return 256; 146 if (ST->hasSSE1()) return 128; 147 return 0; 148 } 149 150 if (ST->is64Bit()) 151 return 64; 152 return 32; 153 154 } 155 156 unsigned X86TTI::getMaximumUnrollFactor() const { 157 if (ST->isAtom()) 158 return 1; 159 160 // Sandybridge and Haswell have multiple execution ports and pipelined 161 // vector units. 162 if (ST->hasAVX()) 163 return 4; 164 165 return 2; 166 } 167 168 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty, 169 OperandValueKind Op1Info, 170 OperandValueKind Op2Info) const { 171 // Legalize the type. 172 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty); 173 174 int ISD = TLI->InstructionOpcodeToISD(Opcode); 175 assert(ISD && "Invalid opcode"); 176 177 static const CostTblEntry<MVT> AVX2CostTable[] = { 178 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to 179 // customize them to detect the cases where shift amount is a scalar one. 180 { ISD::SHL, MVT::v4i32, 1 }, 181 { ISD::SRL, MVT::v4i32, 1 }, 182 { ISD::SRA, MVT::v4i32, 1 }, 183 { ISD::SHL, MVT::v8i32, 1 }, 184 { ISD::SRL, MVT::v8i32, 1 }, 185 { ISD::SRA, MVT::v8i32, 1 }, 186 { ISD::SHL, MVT::v2i64, 1 }, 187 { ISD::SRL, MVT::v2i64, 1 }, 188 { ISD::SHL, MVT::v4i64, 1 }, 189 { ISD::SRL, MVT::v4i64, 1 }, 190 191 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence. 192 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized. 193 194 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized. 195 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized. 196 197 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized. 198 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized. 199 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized. 200 201 // Vectorizing division is a bad idea. See the SSE2 table for more comments. 202 { ISD::SDIV, MVT::v32i8, 32*20 }, 203 { ISD::SDIV, MVT::v16i16, 16*20 }, 204 { ISD::SDIV, MVT::v8i32, 8*20 }, 205 { ISD::SDIV, MVT::v4i64, 4*20 }, 206 { ISD::UDIV, MVT::v32i8, 32*20 }, 207 { ISD::UDIV, MVT::v16i16, 16*20 }, 208 { ISD::UDIV, MVT::v8i32, 8*20 }, 209 { ISD::UDIV, MVT::v4i64, 4*20 }, 210 }; 211 212 // Look for AVX2 lowering tricks. 213 if (ST->hasAVX2()) { 214 int Idx = CostTableLookup<MVT>(AVX2CostTable, array_lengthof(AVX2CostTable), 215 ISD, LT.second); 216 if (Idx != -1) 217 return LT.first * AVX2CostTable[Idx].Cost; 218 } 219 220 static const CostTblEntry<MVT> SSE2UniformConstCostTable[] = { 221 // We don't correctly identify costs of casts because they are marked as 222 // custom. 223 // Constant splats are cheaper for the following instructions. 224 { ISD::SHL, MVT::v16i8, 1 }, // psllw. 225 { ISD::SHL, MVT::v8i16, 1 }, // psllw. 226 { ISD::SHL, MVT::v4i32, 1 }, // pslld 227 { ISD::SHL, MVT::v2i64, 1 }, // psllq. 228 229 { ISD::SRL, MVT::v16i8, 1 }, // psrlw. 230 { ISD::SRL, MVT::v8i16, 1 }, // psrlw. 231 { ISD::SRL, MVT::v4i32, 1 }, // psrld. 232 { ISD::SRL, MVT::v2i64, 1 }, // psrlq. 233 234 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb. 235 { ISD::SRA, MVT::v8i16, 1 }, // psraw. 236 { ISD::SRA, MVT::v4i32, 1 }, // psrad. 237 }; 238 239 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue && 240 ST->hasSSE2()) { 241 int Idx = CostTableLookup<MVT>(SSE2UniformConstCostTable, 242 array_lengthof(SSE2UniformConstCostTable), 243 ISD, LT.second); 244 if (Idx != -1) 245 return LT.first * SSE2UniformConstCostTable[Idx].Cost; 246 } 247 248 249 static const CostTblEntry<MVT> SSE2CostTable[] = { 250 // We don't correctly identify costs of casts because they are marked as 251 // custom. 252 // For some cases, where the shift amount is a scalar we would be able 253 // to generate better code. Unfortunately, when this is the case the value 254 // (the splat) will get hoisted out of the loop, thereby making it invisible 255 // to ISel. The cost model must return worst case assumptions because it is 256 // used for vectorization and we don't want to make vectorized code worse 257 // than scalar code. 258 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence. 259 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized. 260 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul. 261 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized. 262 263 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized. 264 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized. 265 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized. 266 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized. 267 268 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized. 269 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized. 270 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized. 271 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized. 272 273 // It is not a good idea to vectorize division. We have to scalarize it and 274 // in the process we will often end up having to spilling regular 275 // registers. The overhead of division is going to dominate most kernels 276 // anyways so try hard to prevent vectorization of division - it is 277 // generally a bad idea. Assume somewhat arbitrarily that we have to be able 278 // to hide "20 cycles" for each lane. 279 { ISD::SDIV, MVT::v16i8, 16*20 }, 280 { ISD::SDIV, MVT::v8i16, 8*20 }, 281 { ISD::SDIV, MVT::v4i32, 4*20 }, 282 { ISD::SDIV, MVT::v2i64, 2*20 }, 283 { ISD::UDIV, MVT::v16i8, 16*20 }, 284 { ISD::UDIV, MVT::v8i16, 8*20 }, 285 { ISD::UDIV, MVT::v4i32, 4*20 }, 286 { ISD::UDIV, MVT::v2i64, 2*20 }, 287 }; 288 289 if (ST->hasSSE2()) { 290 int Idx = CostTableLookup<MVT>(SSE2CostTable, array_lengthof(SSE2CostTable), 291 ISD, LT.second); 292 if (Idx != -1) 293 return LT.first * SSE2CostTable[Idx].Cost; 294 } 295 296 static const CostTblEntry<MVT> AVX1CostTable[] = { 297 // We don't have to scalarize unsupported ops. We can issue two half-sized 298 // operations and we only need to extract the upper YMM half. 299 // Two ops + 1 extract + 1 insert = 4. 300 { ISD::MUL, MVT::v8i32, 4 }, 301 { ISD::SUB, MVT::v8i32, 4 }, 302 { ISD::ADD, MVT::v8i32, 4 }, 303 { ISD::SUB, MVT::v4i64, 4 }, 304 { ISD::ADD, MVT::v4i64, 4 }, 305 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then 306 // are lowered as a series of long multiplies(3), shifts(4) and adds(2) 307 // Because we believe v4i64 to be a legal type, we must also include the 308 // split factor of two in the cost table. Therefore, the cost here is 18 309 // instead of 9. 310 { ISD::MUL, MVT::v4i64, 18 }, 311 }; 312 313 // Look for AVX1 lowering tricks. 314 if (ST->hasAVX() && !ST->hasAVX2()) { 315 int Idx = CostTableLookup<MVT>(AVX1CostTable, array_lengthof(AVX1CostTable), 316 ISD, LT.second); 317 if (Idx != -1) 318 return LT.first * AVX1CostTable[Idx].Cost; 319 } 320 321 // Custom lowering of vectors. 322 static const CostTblEntry<MVT> CustomLowered[] = { 323 // A v2i64/v4i64 and multiply is custom lowered as a series of long 324 // multiplies(3), shifts(4) and adds(2). 325 { ISD::MUL, MVT::v2i64, 9 }, 326 { ISD::MUL, MVT::v4i64, 9 }, 327 }; 328 int Idx = CostTableLookup<MVT>(CustomLowered, array_lengthof(CustomLowered), 329 ISD, LT.second); 330 if (Idx != -1) 331 return LT.first * CustomLowered[Idx].Cost; 332 333 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle, 334 // 2x pmuludq, 2x shuffle. 335 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() && 336 !ST->hasSSE41()) 337 return 6; 338 339 // Fallback to the default implementation. 340 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info, 341 Op2Info); 342 } 343 344 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index, 345 Type *SubTp) const { 346 // We only estimate the cost of reverse shuffles. 347 if (Kind != SK_Reverse) 348 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp); 349 350 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp); 351 unsigned Cost = 1; 352 if (LT.second.getSizeInBits() > 128) 353 Cost = 3; // Extract + insert + copy. 354 355 // Multiple by the number of parts. 356 return Cost * LT.first; 357 } 358 359 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const { 360 int ISD = TLI->InstructionOpcodeToISD(Opcode); 361 assert(ISD && "Invalid opcode"); 362 363 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src); 364 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst); 365 366 static const TypeConversionCostTblEntry<MVT> SSE2ConvTbl[] = { 367 // These are somewhat magic numbers justified by looking at the output of 368 // Intel's IACA, running some kernels and making sure when we take 369 // legalization into account the throughput will be overestimated. 370 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 371 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 373 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 374 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, 375 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, 376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, 377 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, 378 // There are faster sequences for float conversions. 379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, 381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 382 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 383 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, 384 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, 385 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, 386 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, 387 }; 388 389 if (ST->hasSSE2() && !ST->hasAVX()) { 390 int Idx = ConvertCostTableLookup<MVT>(SSE2ConvTbl, 391 array_lengthof(SSE2ConvTbl), 392 ISD, LTDest.second, LTSrc.second); 393 if (Idx != -1) 394 return LTSrc.first * SSE2ConvTbl[Idx].Cost; 395 } 396 397 EVT SrcTy = TLI->getValueType(Src); 398 EVT DstTy = TLI->getValueType(Dst); 399 400 // The function getSimpleVT only handles simple value types. 401 if (!SrcTy.isSimple() || !DstTy.isSimple()) 402 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 403 404 static const TypeConversionCostTblEntry<MVT> AVXConversionTbl[] = { 405 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 406 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 }, 407 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 408 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 }, 409 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, 410 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 }, 411 412 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 }, 413 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 }, 414 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 415 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }, 416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, 417 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, 418 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 419 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, 420 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 }, 421 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 }, 422 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 423 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 }, 424 425 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 }, 426 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 }, 427 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 }, 428 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 }, 429 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 }, 430 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 }, 431 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 432 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 }, 433 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 }, 434 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 }, 435 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, 436 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 }, 437 438 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 }, 439 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, 440 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 }, 441 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 }, 442 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 }, 443 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 }, 444 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 445 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 }, 446 }; 447 448 if (ST->hasAVX()) { 449 int Idx = ConvertCostTableLookup<MVT>(AVXConversionTbl, 450 array_lengthof(AVXConversionTbl), 451 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT()); 452 if (Idx != -1) 453 return AVXConversionTbl[Idx].Cost; 454 } 455 456 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src); 457 } 458 459 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, 460 Type *CondTy) const { 461 // Legalize the type. 462 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy); 463 464 MVT MTy = LT.second; 465 466 int ISD = TLI->InstructionOpcodeToISD(Opcode); 467 assert(ISD && "Invalid opcode"); 468 469 static const CostTblEntry<MVT> SSE42CostTbl[] = { 470 { ISD::SETCC, MVT::v2f64, 1 }, 471 { ISD::SETCC, MVT::v4f32, 1 }, 472 { ISD::SETCC, MVT::v2i64, 1 }, 473 { ISD::SETCC, MVT::v4i32, 1 }, 474 { ISD::SETCC, MVT::v8i16, 1 }, 475 { ISD::SETCC, MVT::v16i8, 1 }, 476 }; 477 478 static const CostTblEntry<MVT> AVX1CostTbl[] = { 479 { ISD::SETCC, MVT::v4f64, 1 }, 480 { ISD::SETCC, MVT::v8f32, 1 }, 481 // AVX1 does not support 8-wide integer compare. 482 { ISD::SETCC, MVT::v4i64, 4 }, 483 { ISD::SETCC, MVT::v8i32, 4 }, 484 { ISD::SETCC, MVT::v16i16, 4 }, 485 { ISD::SETCC, MVT::v32i8, 4 }, 486 }; 487 488 static const CostTblEntry<MVT> AVX2CostTbl[] = { 489 { ISD::SETCC, MVT::v4i64, 1 }, 490 { ISD::SETCC, MVT::v8i32, 1 }, 491 { ISD::SETCC, MVT::v16i16, 1 }, 492 { ISD::SETCC, MVT::v32i8, 1 }, 493 }; 494 495 if (ST->hasAVX2()) { 496 int Idx = CostTableLookup<MVT>(AVX2CostTbl, array_lengthof(AVX2CostTbl), 497 ISD, MTy); 498 if (Idx != -1) 499 return LT.first * AVX2CostTbl[Idx].Cost; 500 } 501 502 if (ST->hasAVX()) { 503 int Idx = CostTableLookup<MVT>(AVX1CostTbl, array_lengthof(AVX1CostTbl), 504 ISD, MTy); 505 if (Idx != -1) 506 return LT.first * AVX1CostTbl[Idx].Cost; 507 } 508 509 if (ST->hasSSE42()) { 510 int Idx = CostTableLookup<MVT>(SSE42CostTbl, array_lengthof(SSE42CostTbl), 511 ISD, MTy); 512 if (Idx != -1) 513 return LT.first * SSE42CostTbl[Idx].Cost; 514 } 515 516 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy); 517 } 518 519 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val, 520 unsigned Index) const { 521 assert(Val->isVectorTy() && "This must be a vector type"); 522 523 if (Index != -1U) { 524 // Legalize the type. 525 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val); 526 527 // This type is legalized to a scalar type. 528 if (!LT.second.isVector()) 529 return 0; 530 531 // The type may be split. Normalize the index to the new type. 532 unsigned Width = LT.second.getVectorNumElements(); 533 Index = Index % Width; 534 535 // Floating point scalars are already located in index #0. 536 if (Val->getScalarType()->isFloatingPointTy() && Index == 0) 537 return 0; 538 } 539 540 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index); 541 } 542 543 unsigned X86TTI::getScalarizationOverhead(Type *Ty, bool Insert, 544 bool Extract) const { 545 assert (Ty->isVectorTy() && "Can only scalarize vectors"); 546 unsigned Cost = 0; 547 548 for (int i = 0, e = Ty->getVectorNumElements(); i < e; ++i) { 549 if (Insert) 550 Cost += TopTTI->getVectorInstrCost(Instruction::InsertElement, Ty, i); 551 if (Extract) 552 Cost += TopTTI->getVectorInstrCost(Instruction::ExtractElement, Ty, i); 553 } 554 555 return Cost; 556 } 557 558 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, 559 unsigned AddressSpace) const { 560 // Handle non power of two vectors such as <3 x float> 561 if (VectorType *VTy = dyn_cast<VectorType>(Src)) { 562 unsigned NumElem = VTy->getVectorNumElements(); 563 564 // Handle a few common cases: 565 // <3 x float> 566 if (NumElem == 3 && VTy->getScalarSizeInBits() == 32) 567 // Cost = 64 bit store + extract + 32 bit store. 568 return 3; 569 570 // <3 x double> 571 if (NumElem == 3 && VTy->getScalarSizeInBits() == 64) 572 // Cost = 128 bit store + unpack + 64 bit store. 573 return 3; 574 575 // Assume that all other non power-of-two numbers are scalarized. 576 if (!isPowerOf2_32(NumElem)) { 577 unsigned Cost = TargetTransformInfo::getMemoryOpCost(Opcode, 578 VTy->getScalarType(), 579 Alignment, 580 AddressSpace); 581 unsigned SplitCost = getScalarizationOverhead(Src, 582 Opcode == Instruction::Load, 583 Opcode==Instruction::Store); 584 return NumElem * Cost + SplitCost; 585 } 586 } 587 588 // Legalize the type. 589 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src); 590 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) && 591 "Invalid Opcode"); 592 593 // Each load/store unit costs 1. 594 unsigned Cost = LT.first * 1; 595 596 // On Sandybridge 256bit load/stores are double pumped 597 // (but not on Haswell). 598 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2()) 599 Cost*=2; 600 601 return Cost; 602 } 603 604 unsigned X86TTI::getAddressComputationCost(Type *Ty, bool IsComplex) const { 605 // Address computations in vectorized code with non-consecutive addresses will 606 // likely result in more instructions compared to scalar code where the 607 // computation can more often be merged into the index mode. The resulting 608 // extra micro-ops can significantly decrease throughput. 609 unsigned NumVectorInstToHideOverhead = 10; 610 611 if (Ty->isVectorTy() && IsComplex) 612 return NumVectorInstToHideOverhead; 613 614 return TargetTransformInfo::getAddressComputationCost(Ty, IsComplex); 615 } 616
