| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 36 if (getOpcode() < ISD::BUILTIN_OP_END)
54 case ISD::DELETED_NODE: return "<<Deleted Node!>>";
56 case ISD::PREFETCH: return "Prefetch";
57 case ISD::ATOMIC_FENCE: return "AtomicFence";
58 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap";
59 case ISD::ATOMIC_SWAP: return "AtomicSwap";
60 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd";
61 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
62 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd";
63 case ISD::ATOMIC_LOAD_OR: return "AtomicLoadOr"
[all...] |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
154 if (Op.getOpcode() == ISD::LOAD) {
156 ISD::LoadExtType ExtType = LD->getExtensionType();
157 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) {
163 } else if (Op.getOpcode() == ISD::STORE) {
193 case ISD::ADD:
194 case ISD::SUB
[all...] |
| LegalizeIntegerTypes.cpp | 50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
59 case ISD::CTLZ_ZERO_UNDEF:
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break
[all...] |
| LegalizeVectorTypes.cpp | 49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break
[all...] |
| LegalizeDAG.cpp | 277 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
290 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
307 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
322 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
363 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
365 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
375 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
387 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
404 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
411 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr
[all...] |
| TargetLowering.cpp | 104 ISD::CondCode &CCCode,
112 case ISD::SETEQ:
113 case ISD::SETOEQ:
117 case ISD::SETNE:
118 case ISD::SETUNE:
122 case ISD::SETGE:
123 case ISD::SETOGE:
127 case ISD::SETLT:
128 case ISD::SETOLT:
132 case ISD::SETLE
[all...] |
| DAGCombiner.cpp | 159 ISD::NodeType ExtType);
257 SDValue N3, ISD::CondCode CC,
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
411 if (Op.getOpcode() == ISD::FNEG) return 2;
421 case ISD::ConstantFP:
425 case ISD::FADD:
431 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
441 case ISD::FSUB:
448 case ISD::FMUL:
449 case ISD::FDIV
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 174 int ISD = TLI->InstructionOpcodeToISD(Opcode);
175 assert(ISD && "Invalid opcode");
180 { ISD::SHL, MVT::v4i32, 1 },
181 { ISD::SRL, MVT::v4i32, 1 },
182 { ISD::SRA, MVT::v4i32, 1 },
183 { ISD::SHL, MVT::v8i32, 1 },
184 { ISD::SRL, MVT::v8i32, 1 },
185 { ISD::SRA, MVT::v8i32, 1 },
186 { ISD::SHL, MVT::v2i64, 1 },
187 { ISD::SRL, MVT::v2i64, 1 }
[all...] |
| X86ISelLowering.cpp | 73 if (Vec.getOpcode() == ISD::UNDEF)
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
122 if (Vec.getOpcode() == ISD::UNDEF)
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand)
[all...] |
| /external/llvm/include/llvm/Target/ |
| CostTable.h | 23 int ISD;
31 unsigned len, int ISD, TypeTy Ty) {
33 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
43 int ISD;
52 unsigned len, int ISD, TypeTy Dst, TypeTy Src) {
54 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
58 setOperationAction(ISD::STORE, MVT::f32, Promote)
[all...] |
| AMDILISelLowering.cpp | 99 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
100 setOperationAction(ISD::SUBE, VT, Expand);
101 setOperationAction(ISD::SUBC, VT, Expand);
102 setOperationAction(ISD::ADDE, VT, Expand);
103 setOperationAction(ISD::ADDC, VT, Expand);
104 setOperationAction(ISD::BRCOND, VT, Custom);
105 setOperationAction(ISD::BR_JT, VT, Expand);
106 setOperationAction(ISD::BRIND, VT, Expand);
108 setOperationAction(ISD::SREM, VT, Expand);
109 setOperationAction(ISD::SMUL_LOHI, VT, Expand)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 181 int ISD = TLI->InstructionOpcodeToISD(Opcode);
182 assert(ISD && "Invalid opcode");
187 { ISD::FP_ROUND, MVT::v2f64, 2 },
188 { ISD::FP_EXTEND, MVT::v2f32, 2 },
189 { ISD::FP_EXTEND, MVT::v4f32, 4 }
192 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
193 ISD == ISD::FP_EXTEND)) {
196 ISD, LT.second)
[all...] |
| ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
27 case ISD::SRL: return ARM_AM::lsr;
28 case ISD::SRA: return ARM_AM::asr;
29 case ISD::ROTR: return ARM_AM::ror;
30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
|
| /external/llvm/lib/CodeGen/ |
| BasicTargetTransformInfo.cpp | 181 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
182 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
223 int ISD = TLI->InstructionOpcodeToISD(Opcode);
224 assert(ISD && "Invalid opcode");
233 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
243 if (!TLI->isOperationExpand(ISD, LT.second)) {
270 int ISD = TLI->InstructionOpcodeToISD(Opcode);
271 assert(ISD && "Invalid opcode");
294 if (TLI->isOperationLegalOrPromote(ISD, DstLT.second))
305 if (!TLI->isOperationExpand(ISD, DstLT.second)
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
111 setOperationAction(ISD::SUBE, VT, Expand);
112 setOperationAction(ISD::SUBC, VT, Expand);
113 setOperationAction(ISD::ADDE, VT, Expand);
114 setOperationAction(ISD::ADDC, VT, Expand);
115 setOperationAction(ISD::BRCOND, VT, Custom);
116 setOperationAction(ISD::BR_JT, VT, Expand);
117 setOperationAction(ISD::BRIND, VT, Expand);
119 setOperationAction(ISD::SREM, VT, Expand);
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand)
[all...] |
| AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
39 setOperationAction(ISD::UDIV, MVT::i32, Expand);
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
41 setOperationAction(ISD::UREM, MVT::i32, Expand);
52 const SmallVectorImpl<ISD::InputArg> &Ins,
68 const SmallVectorImpl<ISD::OutputArg> &Outs,
89 case ISD::SDIV: return LowerSDIV(Op, DAG)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
111 setOperationAction(ISD::SUBE, VT, Expand);
112 setOperationAction(ISD::SUBC, VT, Expand);
113 setOperationAction(ISD::ADDE, VT, Expand);
114 setOperationAction(ISD::ADDC, VT, Expand);
115 setOperationAction(ISD::BRCOND, VT, Custom);
116 setOperationAction(ISD::BR_JT, VT, Expand);
117 setOperationAction(ISD::BRIND, VT, Expand);
119 setOperationAction(ISD::SREM, VT, Expand);
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand)
[all...] |
| AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
39 setOperationAction(ISD::UDIV, MVT::i32, Expand);
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
41 setOperationAction(ISD::UREM, MVT::i32, Expand);
52 const SmallVectorImpl<ISD::InputArg> &Ins,
68 const SmallVectorImpl<ISD::OutputArg> &Outs,
89 case ISD::SDIV: return LowerSDIV(Op, DAG)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| Analysis.h | 68 /// getFCmpCondCode - Return the ISD condition code corresponding to
72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
74 /// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats,
76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
78 /// getICmpCondCode - Return the ISD condition code corresponding to
81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 54 ISD::ArgFlagsTy ArgFlags, CCState &State);
59 ISD::ArgFlagsTy ArgFlags, CCState &State);
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
69 ISD::ArgFlagsTy ArgFlags, CCState &State);
74 ISD::ArgFlagsTy ArgFlags, CCState &State);
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
84 ISD::ArgFlagsTy ArgFlags, CCState &State) {
133 ISD::ArgFlagsTy ArgFlags, CCState &State) {
171 ISD::ArgFlagsTy ArgFlags, CCState &State) {
189 ISD::ArgFlagsTy ArgFlags, CCState &State)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 76 setTargetDAGCombine(ISD::OR);
78 setTargetDAGCombine(ISD::AND);
79 setTargetDAGCombine(ISD::SRA);
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
88 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
89 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
92 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 39 ISD::ArgFlagsTy &ArgFlags, CCState &State)
52 ISD::ArgFlagsTy &ArgFlags, CCState &State)
81 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
120 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
165 const SmallVectorImpl<ISD::OutputArg> &Outs,
176 const SmallVectorImpl<ISD::OutputArg> &Outs,
239 const SmallVectorImpl<ISD::OutputArg> &Outs,
268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
274 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
126 if (N.getOpcode() == ISD::TargetConstant ||
127 N.getOpcode() == ISD::TargetGlobalAddress) {
282 if (N->getOpcode() != ISD::Constant)
300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
371 if (Opcode == ISD::SHL) {
376 } else if (Opcode == ISD::SRL) {
383 } else if (Opcode == ISD::ROTL) {
421 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
95 setOperationAction(ISD::SRA, MVT::i8, Custom);
96 setOperationAction(ISD::SHL, MVT::i8, Custom);
97 setOperationAction(ISD::SRL, MVT::i8, Custom)
[all...] |
