| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.td | 67 def v4f32 : ValueType<128, 43>; // 4 x f32 vector value
|
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 301 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
309 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
313 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
326 def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
| ARMISelLowering.cpp | 463 addQRTypeForNEON(MVT::v4f32);
472 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
473 // supported for v4f32.
509 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
510 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
511 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
512 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
513 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
514 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
515 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand)
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 317 DecodeSHUFPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
356 DecodeUNPCKLMask(MVT::v4f32, ShuffleMask);
392 DecodeUNPCKHMask(MVT::v4f32, ShuffleMask);
408 DecodePSHUFMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
|
| /external/llvm/test/CodeGen/ARM/ |
| vminmax.ll | 125 %tmp3 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
147 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
271 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
293 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
| vldlane.ll | 194 %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
208 declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind readonly
327 %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
343 declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
480 %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1, i32 1)
498 declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly
|
| vabd.ll | 125 %tmp3 = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
147 declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
|
| vbsl.ll | 161 %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
200 declare <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
|
| debug-info-branch-folding.ll | 46 !5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ]
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 631 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
644 // v4f32 != v4f32 could be translate to unordered not equal
645 else if (VecVT == MVT::v4f32)
658 else if (VecVT == MVT::v4f32)
673 if (VecVT == MVT::v4f32)
679 if (VecVT == MVT::v4f32)
683 if (VecVT == MVT::v4f32)
694 // types (v16i8, v8i16, v4i32, and v4f32).
703 case MVT::v4f32
[all...] |
| README_ALTIVEC.txt | 33 v4f32 Vector;
34 v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
|
| PPCRegisterInfo.td | 202 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/IR/ |
| IntrinsicsPowerPC.td | 54 /// PowerPC_Vec_FF_Intrinsic - A PowerPC intrinsic that takes one v4f32
60 /// PowerPC_Vec_FFF_Intrinsic - A PowerPC intrinsic that takes two v4f32
|
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
41 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
45 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
47 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
552 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
646 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
[all...] |
| SIInstructions.td | [all...] |
| R600RegisterInfo.td | 197 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128,
|
| AMDILISelLowering.cpp | 53 (int)MVT::v4f32,
78 (int)MVT::v4f32,
407 FLTTY = MVT::v4f32;
|
| SIRegisterInfo.td | 175 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
|
| /external/llvm/test/CodeGen/AArch64/ |
| neon-aba-abd.ll | 210 declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>)
214 %abd = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %lhs, <4 x float> %rhs)
|
| neon-mul-div.ll | 159 declare <4 x float> @llvm.aarch64.neon.vmulx.v4f32(<4 x float>, <4 x float>)
172 %val = call <4 x float> @llvm.aarch64.neon.vmulx.v4f32(<4 x float> %lhs, <4 x float> %rhs)
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 192 [v2f64, v2i64, v4f32, v4i32, v8i16, v16i8], 128,
|
