1 2 class R600Reg <string name, bits<16> encoding> : Register<name> { 3 let Namespace = "AMDGPU"; 4 let HWEncoding = encoding; 5 } 6 7 class R600RegWithChan <string name, bits<9> sel, string chan> : 8 Register <name> { 9 10 field bits<2> chan_encoding = !if(!eq(chan, "X"), 0, 11 !if(!eq(chan, "Y"), 1, 12 !if(!eq(chan, "Z"), 2, 13 !if(!eq(chan, "W"), 3, 0)))); 14 let HWEncoding{8-0} = sel; 15 let HWEncoding{10-9} = chan_encoding; 16 let Namespace = "AMDGPU"; 17 } 18 19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> : 20 RegisterWithSubRegs<n, subregs> { 21 let Namespace = "AMDGPU"; 22 let SubRegIndices = [sub0, sub1, sub2, sub3]; 23 let HWEncoding = encoding; 24 } 25 26 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> : 27 RegisterWithSubRegs<n, subregs> { 28 let Namespace = "AMDGPU"; 29 let SubRegIndices = [sub0, sub1]; 30 let HWEncoding = encoding; 31 } 32 33 34 foreach Index = 0-127 in { 35 foreach Chan = [ "X", "Y", "Z", "W" ] in { 36 // 32-bit Temporary Registers 37 def T#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, Chan>; 38 39 // Indirect addressing offset registers 40 def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan, 41 Index, Chan>; 42 def TRegMem#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, 43 Chan>; 44 } 45 // 128-bit Temporary Registers 46 def T#Index#_XYZW : R600Reg_128 <"T"#Index#"", 47 [!cast<Register>("T"#Index#"_X"), 48 !cast<Register>("T"#Index#"_Y"), 49 !cast<Register>("T"#Index#"_Z"), 50 !cast<Register>("T"#Index#"_W")], 51 Index>; 52 53 def T#Index#_XY : R600Reg_64 <"T"#Index#"", 54 [!cast<Register>("T"#Index#"_X"), 55 !cast<Register>("T"#Index#"_Y")], 56 Index>; 57 } 58 59 // KCACHE_BANK0 60 foreach Index = 159-128 in { 61 foreach Chan = [ "X", "Y", "Z", "W" ] in { 62 // 32-bit Temporary Registers 63 def KC0_#Index#_#Chan : R600RegWithChan <"KC0["#!add(Index,-128)#"]."#Chan, Index, Chan>; 64 } 65 // 128-bit Temporary Registers 66 def KC0_#Index#_XYZW : R600Reg_128 <"KC0["#!add(Index, -128)#"].XYZW", 67 [!cast<Register>("KC0_"#Index#"_X"), 68 !cast<Register>("KC0_"#Index#"_Y"), 69 !cast<Register>("KC0_"#Index#"_Z"), 70 !cast<Register>("KC0_"#Index#"_W")], 71 Index>; 72 } 73 74 // KCACHE_BANK1 75 foreach Index = 191-160 in { 76 foreach Chan = [ "X", "Y", "Z", "W" ] in { 77 // 32-bit Temporary Registers 78 def KC1_#Index#_#Chan : R600RegWithChan <"KC1["#!add(Index,-160)#"]."#Chan, Index, Chan>; 79 } 80 // 128-bit Temporary Registers 81 def KC1_#Index#_XYZW : R600Reg_128 <"KC1["#!add(Index, -160)#"].XYZW", 82 [!cast<Register>("KC1_"#Index#"_X"), 83 !cast<Register>("KC1_"#Index#"_Y"), 84 !cast<Register>("KC1_"#Index#"_Z"), 85 !cast<Register>("KC1_"#Index#"_W")], 86 Index>; 87 } 88 89 90 // Array Base Register holding input in FS 91 foreach Index = 448-480 in { 92 def ArrayBase#Index : R600Reg<"ARRAY_BASE", Index>; 93 } 94 95 96 // Special Registers 97 98 def ZERO : R600Reg<"0.0", 248>; 99 def ONE : R600Reg<"1.0", 249>; 100 def NEG_ONE : R600Reg<"-1.0", 249>; 101 def ONE_INT : R600Reg<"1", 250>; 102 def HALF : R600Reg<"0.5", 252>; 103 def NEG_HALF : R600Reg<"-0.5", 252>; 104 def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">; 105 def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">; 106 def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">; 107 def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">; 108 def PV_X : R600RegWithChan<"PV.X", 254, "X">; 109 def PV_Y : R600RegWithChan<"PV.Y", 254, "Y">; 110 def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">; 111 def PV_W : R600RegWithChan<"PV.W", 254, "W">; 112 def PS: R600Reg<"PS", 255>; 113 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>; 114 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>; 115 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>; 116 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>; 117 def AR_X : R600Reg<"AR.x", 0>; 118 def OQAP : R600Reg<"OQAP", 221>; 119 120 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32, 121 (add (sequence "ArrayBase%u", 448, 480))>; 122 // special registers for ALU src operands 123 // const buffer reference, SRCx_SEL contains index 124 def ALU_CONST : R600Reg<"CBuf", 0>; 125 // interpolation param reference, SRCx_SEL contains index 126 def ALU_PARAM : R600Reg<"Param", 0>; 127 128 let isAllocatable = 0 in { 129 130 // XXX: Only use the X channel, until we support wider stack widths 131 def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>; 132 133 } // End isAllocatable = 0 134 135 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32, 136 (add (sequence "KC0_%u_X", 128, 159))>; 137 138 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32, 139 (add (sequence "KC0_%u_Y", 128, 159))>; 140 141 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32, 142 (add (sequence "KC0_%u_Z", 128, 159))>; 143 144 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32, 145 (add (sequence "KC0_%u_W", 128, 159))>; 146 147 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32, 148 (interleave R600_KC0_X, R600_KC0_Y, 149 R600_KC0_Z, R600_KC0_W)>; 150 151 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32, 152 (add (sequence "KC1_%u_X", 160, 191))>; 153 154 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32, 155 (add (sequence "KC1_%u_Y", 160, 191))>; 156 157 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32, 158 (add (sequence "KC1_%u_Z", 160, 191))>; 159 160 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32, 161 (add (sequence "KC1_%u_W", 160, 191))>; 162 163 def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32, 164 (interleave R600_KC1_X, R600_KC1_Y, 165 R600_KC1_Z, R600_KC1_W)>; 166 167 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, 168 (add (sequence "T%u_X", 0, 127), AR_X)>; 169 170 def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32, 171 (add (sequence "T%u_Y", 0, 127))>; 172 173 def R600_TReg32_Z : RegisterClass <"AMDGPU", [f32, i32], 32, 174 (add (sequence "T%u_Z", 0, 127))>; 175 176 def R600_TReg32_W : RegisterClass <"AMDGPU", [f32, i32], 32, 177 (add (sequence "T%u_W", 0, 127))>; 178 179 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, 180 (interleave R600_TReg32_X, R600_TReg32_Y, 181 R600_TReg32_Z, R600_TReg32_W)>; 182 183 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add 184 R600_TReg32, 185 R600_ArrayBase, 186 R600_Addr, 187 ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF, 188 ALU_CONST, ALU_PARAM, OQAP 189 )>; 190 191 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add 192 PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>; 193 194 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add 195 PREDICATE_BIT)>; 196 197 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, 198 (add (sequence "T%u_XYZW", 0, 127))> { 199 let CopyCost = -1; 200 } 201 202 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32], 64, 203 (add (sequence "T%u_XY", 0, 63))>; 204 205 //===----------------------------------------------------------------------===// 206 // Register classes for indirect addressing 207 //===----------------------------------------------------------------------===// 208 209 // Super register for all the Indirect Registers. This register class is used 210 // by the REG_SEQUENCE instruction to specify the registers to use for direct 211 // reads / writes which may be written / read by an indirect address. 212 class IndirectSuper<string n, list<Register> subregs> : 213 RegisterWithSubRegs<n, subregs> { 214 let Namespace = "AMDGPU"; 215 let SubRegIndices = 216 [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, 217 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15]; 218 } 219 220 def IndirectSuperReg : IndirectSuper<"Indirect", 221 [TRegMem0_X, TRegMem1_X, TRegMem2_X, TRegMem3_X, TRegMem4_X, TRegMem5_X, 222 TRegMem6_X, TRegMem7_X, TRegMem8_X, TRegMem9_X, TRegMem10_X, TRegMem11_X, 223 TRegMem12_X, TRegMem13_X, TRegMem14_X, TRegMem15_X] 224 >; 225 226 def IndirectReg : RegisterClass<"AMDGPU", [f32, i32], 32, (add IndirectSuperReg)>; 227 228 // This register class defines the registers that are the storage units for 229 // the "Indirect Addressing" pseudo memory space. 230 // XXX: Only use the X channel, until we support wider stack widths 231 def TRegMem : RegisterClass<"AMDGPU", [f32, i32], 32, 232 (add (sequence "TRegMem%u_X", 0, 16)) 233 >; 234