/external/chromium_org/third_party/mesa/src/src/gallium/drivers/svga/ |
svga_tgsi_insn.c | 111 dest.mask = reg->Register.WriteMask; 924 writemask(temp, channel), 1052 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 )) 1075 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0)) 1100 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 )) [all...] |
/external/mesa3d/src/gallium/drivers/svga/ |
svga_tgsi_insn.c | 111 dest.mask = reg->Register.WriteMask; 924 writemask(temp, channel), 1052 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 )) 1075 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0)) 1100 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 )) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/auxiliary/tgsi/ |
tgsi_dump.c | 191 uint writemask ) 193 if (writemask != TGSI_WRITEMASK_XYZW) { 195 if (writemask & TGSI_WRITEMASK_X) 197 if (writemask & TGSI_WRITEMASK_Y) 199 if (writemask & TGSI_WRITEMASK_Z) 201 if (writemask & TGSI_WRITEMASK_W) 546 _dump_writemask( ctx, dst->Register.WriteMask );
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/external/mesa3d/src/gallium/auxiliary/tgsi/ |
tgsi_dump.c | 191 uint writemask ) 193 if (writemask != TGSI_WRITEMASK_XYZW) { 195 if (writemask & TGSI_WRITEMASK_X) 197 if (writemask & TGSI_WRITEMASK_Y) 199 if (writemask & TGSI_WRITEMASK_Z) 201 if (writemask & TGSI_WRITEMASK_W) 546 _dump_writemask( ctx, dst->Register.WriteMask );
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/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
brw_vec4_reg_allocate.cpp | 339 temp.writemask = 0; 341 temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c)); 342 assert(temp.writemask != 0); 353 * whole register and use spill_reg's writemask to select which
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brw_vec4_copy_propagation.cpp | 279 * not get used based on the destination writemask. 311 if (inst->dst.writemask & (1 << i)) { 324 if (inst->dst.writemask & (1 << j) &&
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brw_vec4_emit.cpp | 66 reg.dw1.bits.writemask = inst->dst.writemask; 165 brw_reg.dw1.bits.writemask = dst.writemask; 171 brw_reg.dw1.bits.writemask = dst.writemask; 285 /* Can't do writemask because math can't be align16. */ 286 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 318 /* Can't do writemask because math can't be align16. */ 319 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW) [all...] |
brw_vs_emit.c | 438 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 464 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 493 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 664 dst.dw1.bits.writemask != 0xf) 747 dst.dw1.bits.writemask != 0xf) 824 if (dst.dw1.bits.writemask & WRITEMASK_X) { 847 if (dst.dw1.bits.writemask & WRITEMASK_Y) { 852 if (dst.dw1.bits.writemask & WRITEMASK_Z) { 867 if (dst.dw1.bits.writemask & WRITEMASK_W) { 882 bool need_tmp = (dst.dw1.bits.writemask != 0xf | [all...] |
brw_eu.h | 90 GLuint writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon15074::__anon15075 184 * \param writemask WRITEMASK_X/Y/Z/W bitfield 194 GLuint writemask ) 217 * set swizzle and writemask to W, as the lower bits of subnr will 223 reg.dw1.bits.writemask = writemask; 531 /* If/else instructions break in align16 mode if writemask & swizzle 693 reg.dw1.bits.writemask &= mask; 701 reg.dw1.bits.writemask = mask; 967 GLuint writemask, [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
brw_vec4_reg_allocate.cpp | 339 temp.writemask = 0; 341 temp.writemask |= (1 << BRW_GET_SWZ(inst->src[i].swizzle, c)); 342 assert(temp.writemask != 0); 353 * whole register and use spill_reg's writemask to select which
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brw_vec4_copy_propagation.cpp | 279 * not get used based on the destination writemask. 311 if (inst->dst.writemask & (1 << i)) { 324 if (inst->dst.writemask & (1 << j) &&
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brw_vec4_emit.cpp | 66 reg.dw1.bits.writemask = inst->dst.writemask; 165 brw_reg.dw1.bits.writemask = dst.writemask; 171 brw_reg.dw1.bits.writemask = dst.writemask; 285 /* Can't do writemask because math can't be align16. */ 286 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW); 318 /* Can't do writemask because math can't be align16. */ 319 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW) [all...] |
brw_vs_emit.c | 438 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 464 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 493 struct brw_reg tmp = brw_writemask(get_tmp(c), dst.dw1.bits.writemask); 664 dst.dw1.bits.writemask != 0xf) 747 dst.dw1.bits.writemask != 0xf) 824 if (dst.dw1.bits.writemask & WRITEMASK_X) { 847 if (dst.dw1.bits.writemask & WRITEMASK_Y) { 852 if (dst.dw1.bits.writemask & WRITEMASK_Z) { 867 if (dst.dw1.bits.writemask & WRITEMASK_W) { 882 bool need_tmp = (dst.dw1.bits.writemask != 0xf | [all...] |
brw_eu.h | 90 GLuint writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon25416::__anon25417 184 * \param writemask WRITEMASK_X/Y/Z/W bitfield 194 GLuint writemask ) 217 * set swizzle and writemask to W, as the lower bits of subnr will 223 reg.dw1.bits.writemask = writemask; 531 /* If/else instructions break in align16 mode if writemask & swizzle 693 reg.dw1.bits.writemask &= mask; 701 reg.dw1.bits.writemask = mask; 967 GLuint writemask, [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/llvmpipe/ |
lp_state_blend.c | 119 state->depth.writemask = 0;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
radeon_compiler.h | 106 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeonsi/ |
si_state.h | 61 uint8_t writemask[2]; member in struct:si_state_dsa
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/external/mesa3d/src/gallium/drivers/llvmpipe/ |
lp_state_blend.c | 119 state->depth.writemask = 0;
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_compiler.h | 106 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask);
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
si_state.h | 61 uint8_t writemask[2]; member in struct:si_state_dsa
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r600/ |
r600_state_common.c | 250 S_028430_STENCILWRITEMASK(state->writemask[0])); 255 S_028434_STENCILWRITEMASK_BF(state->writemask[1])); 278 ref.writemask[0] = dsa->writemask[0]; 279 ref.writemask[1] = dsa->writemask[1]; 301 ref.writemask[0] = dsa->writemask[0]; 302 ref.writemask[1] = dsa->writemask[1] [all...] |
/external/mesa3d/src/gallium/drivers/r600/ |
r600_state_common.c | 250 S_028430_STENCILWRITEMASK(state->writemask[0])); 255 S_028434_STENCILWRITEMASK_BF(state->writemask[1])); 278 ref.writemask[0] = dsa->writemask[0]; 279 ref.writemask[1] = dsa->writemask[1]; 301 ref.writemask[0] = dsa->writemask[0]; 302 ref.writemask[1] = dsa->writemask[1] [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/i915/ |
i915_state.c | 446 int writemask = depth_stencil->stencil[0].writemask & 0xff; local 452 STENCIL_WRITE_MASK(writemask)); 475 int wmask = depth_stencil->stencil[1].writemask & 0xff; 511 if (depth_stencil->depth.writemask) [all...] |
/external/mesa3d/src/gallium/drivers/i915/ |
i915_state.c | 446 int writemask = depth_stencil->stencil[0].writemask & 0xff; local 452 STENCIL_WRITE_MASK(writemask)); 475 int wmask = depth_stencil->stencil[1].writemask & 0xff; 511 if (depth_stencil->depth.writemask) [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv30/ |
nv30_state.c | 221 SB_DATA (so, cso->depth.writemask); 227 SB_DATA (so, cso->stencil[0].writemask); 243 SB_DATA (so, cso->stencil[1].writemask);
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