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  /external/llvm/lib/Target/Mips/
MicroMipsInstrFormats.td 24 bits<16> imm16;
31 let Inst{15-0} = imm16;
37 bits<16> imm16;
44 let Inst{15-0} = imm16;
49 bits<16> imm16;
56 let Inst{15-0} = imm16;
Mips16InstrInfo.td 109 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
110 !strconcat(asmstr, "\t$imm16"),[], itin>;
    [all...]
MipsInstrFormats.td 158 bits<16> imm16;
164 let Inst{15-0} = imm16;
173 bits<16> imm16;
179 let Inst{15-0} = imm16;
233 bits<16> imm16;
240 let Inst{15-0} = imm16;
314 bits<16> imm16;
321 let Inst{15-0} = imm16;
379 bits<16> imm16;
386 let Inst{15-0} = imm16;
    [all...]
Mips16InstrFormats.td 436 bits<16> imm16;
441 let Inst{26-21} = imm16{10-5};
442 let Inst{20-16} = imm16{15-11};
445 let Inst{4-0} = imm16{4-0};
487 bits<16> imm16;
493 let Inst{26-21} = imm16{10-5};
494 let Inst{20-16} = imm16{15-11};
498 let Inst{4-0} = imm16{4-0};
512 bits<16> imm16;
518 let Inst{26-21} = imm16{10-5}
    [all...]
MipsInstrInfo.td 396 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
397 !strconcat(opstr, "\t$rt, $rs, $imm16"),
398 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
437 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
568 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
569 !strconcat(opstr, "\t$rt, $rs, $imm16"),
570 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
    [all...]
  /art/compiler/utils/mips/
assembler_mips.h 226 void Addi(Register rt, Register rs, uint16_t imm16);
227 void Addiu(Register rt, Register rs, uint16_t imm16);
236 void Andi(Register rt, Register rs, uint16_t imm16);
238 void Ori(Register rt, Register rs, uint16_t imm16);
240 void Xori(Register rt, Register rs, uint16_t imm16);
250 void Lb(Register rt, Register rs, uint16_t imm16);
251 void Lh(Register rt, Register rs, uint16_t imm16);
252 void Lw(Register rt, Register rs, uint16_t imm16);
253 void Lbu(Register rt, Register rs, uint16_t imm16);
254 void Lhu(Register rt, Register rs, uint16_t imm16);
    [all...]
assembler_mips.cc 182 void MipsAssembler::Addi(Register rt, Register rs, uint16_t imm16) {
183 EmitI(0x8, rs, rt, imm16);
186 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) {
187 EmitI(0x9, rs, rt, imm16);
218 void MipsAssembler::Andi(Register rt, Register rs, uint16_t imm16) {
219 EmitI(0xc, rs, rt, imm16);
226 void MipsAssembler::Ori(Register rt, Register rs, uint16_t imm16) {
227 EmitI(0xd, rs, rt, imm16);
234 void MipsAssembler::Xori(Register rt, Register rs, uint16_t imm16) {
235 EmitI(0xe, rs, rt, imm16);
    [all...]
  /art/compiler/dex/quick/mips/
mips_lir.h 309 kMipsAddiu, // addiu t,s,imm16 [001001] s[25..21] t[20..16] imm16[15..0].
312 kMipsAndi, // andi t,s,imm16 [001100] s[25..21] t[20..16] imm16[15..0].
332 kMipsLahi, // lui t,imm16 [00111100000] t[20..16] imm16[15..0] load addr hi.
333 kMipsLalo, // ori t,s,imm16 [001001] s[25..21] t[20..16] imm16[15..0] load addr lo.
334 kMipsLui, // lui t,imm16 [00111100000] t[20..16] imm16[15..0]
    [all...]
  /dalvik/vm/compiler/codegen/mips/
MipsLIR.h 401 kMipsAddiu, /* addiu t,s,imm16 [001001] s[25..21] t[20..16] imm16[15..0] */
404 kMipsAndi, /* andi t,s,imm16 [001100] s[25..21] t[20..16] imm16[15..0] */
425 kMipsLahi, /* lui t,imm16 [00111100000] t[20..16] imm16[15..0] load addr hi */
426 kMipsLalo, /* ori t,s,imm16 [001001] s[25..21] t[20..16] imm16[15..0] load addr lo */
427 kMipsLui, /* lui t,imm16 [00111100000] t[20..16] imm16[15..0] *
    [all...]
  /external/valgrind/main/none/tests/x86/
insn_basic.def 35 adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
36 adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
37 adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
38 adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
39 adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
40 adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
68 addw imm16[1234] ax.uw[5678] => 1.uw[6912]
69 addw imm16[1234] bx.uw[5678] => 1.uw[6912]
70 addw imm16[1234] m16.uw[5678] => 1.uw[6912]
88 andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230
    [all...]
  /external/valgrind/main/none/tests/amd64/
insn_basic.def 15 ###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
16 ###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
17 adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
18 adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
19 adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
20 adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
62 addw imm16[1234] ax.uw[5678] => 1.uw[6912]
63 addw imm16[1234] bx.uw[5678] => 1.uw[6912]
64 addw imm16[1234] m16.uw[5678] => 1.uw[6912]
89 andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230
    [all...]
  /dalvik/vm/compiler/codegen/x86/libenc/
enc_tabl.cpp 350 {OpcodeInfo::decoder, {Size16, opcode_starts_from + 5, iw}, {AX, imm16}, DU_U },\
355 {OpcodeInfo::all, {Size16, 0x81, opc_ext, iw}, {r_m16, imm16}, def_use },\
    [all...]
enc_prvt.h 199 #define imm16 {OpndKind_Imm, OpndSize_16, OpndExt_Any, RegName_Null} macro
  /external/valgrind/main/VEX/priv/
host_mips_defs.c 948 MIPSRH *MIPSRH_Imm(Bool syned, UShort imm16)
953 op->Mrh.Imm.imm16 = imm16;
957 vassert(imm16 != 0x8000);
976 vex_printf("%d", (Int) (Short) op->Mrh.Imm.imm16);
978 vex_printf("%u", (UInt) (UShort) op->Mrh.Imm.imm16);
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCJITInfo.cpp 27 #define BUILD_ADDIS(RD,RS,IMM16) \
28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
44 #define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16)
  /art/compiler/utils/arm/
assembler_arm.cc 399 void ArmAssembler::movw(Register rd, uint16_t imm16, Condition cond) {
402 B25 | B24 | ((imm16 >> 12) << 16) |
403 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
408 void ArmAssembler::movt(Register rd, uint16_t imm16, Condition cond) {
411 B25 | B24 | B22 | ((imm16 >> 12) << 16) |
412 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
1038 void ArmAssembler::bkpt(uint16_t imm16) {
    [all...]
assembler_arm.h 260 void movw(Register rd, uint16_t imm16, Condition cond = AL);
261 void movt(Register rd, uint16_t imm16, Condition cond = AL);
301 void bkpt(uint16_t imm16);
  /external/chromium_org/v8/src/ia32/
assembler-ia32.cc 838 void Assembler::cmpw(const Operand& op, Immediate imm16) {
839 ASSERT(imm16.is_int16());
844 emit_w(imm16);
1321 void Assembler::ret(int imm16) {
1323 ASSERT(is_uint16(imm16));
1324 if (imm16 == 0) {
1328 EMIT(imm16 & 0xFF);
1329 EMIT((imm16 >> 8) & 0xFF);
    [all...]
  /external/v8/src/ia32/
assembler-ia32.cc 847 void Assembler::cmpw(const Operand& op, Immediate imm16) {
848 ASSERT(imm16.is_int16());
853 emit_w(imm16);
1305 void Assembler::ret(int imm16) {
1307 ASSERT(is_uint16(imm16));
1308 if (imm16 == 0) {
1312 EMIT(imm16 & 0xFF);
1313 EMIT((imm16 >> 8) & 0xFF);
    [all...]
  /external/chromium_org/v8/src/mips/
constants-mips.cc 311 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16.
assembler-mips.cc 720 int32_t imm16 = imm18 >> 2;
721 ASSERT(is_int16(imm16));
723 instr_at_put(pos, instr | (imm16 & kImm16Mask));
1046 int32_t imm16 = imm18 >> 2; local
1047 ASSERT(is_int16(imm16));
1048 instr_at_put(at_offset, (imm16 & kImm16Mask));
    [all...]
  /external/v8/src/mips/
constants-mips.cc 305 // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16.
assembler-mips.cc 726 int32_t imm16 = imm18 >> 2;
727 ASSERT(is_int16(imm16));
729 instr_at_put(pos, instr | (imm16 & kImm16Mask));
1041 int32_t imm16 = imm18 >> 2; local
1042 ASSERT(is_int16(imm16));
1043 instr_at_put(at_offset, (imm16 & kImm16Mask));
    [all...]
  /external/elfutils/libcpu/defs/
i386 10 %mask {imm16} 16
169 11001000,{imm16},{imm8}:enter{W} {imm16},{imm8}
490 11000010,{imm16}:ret{W} {imm16}
492 11001010,{imm16}:lret {imm16}
    [all...]
  /external/llvm/lib/Target/AArch64/Disassembler/
AArch64Disassembler.cpp 423 unsigned Imm16 = FullImm & 0xffff;
428 Inst.addOperand(MCOperand::CreateImm(Imm16));

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