1 //===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Describe MIPS instructions format 12 // 13 // CPU INSTRUCTION FORMATS 14 // 15 // opcode - operation code. 16 // rs - src reg. 17 // rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18 // rd - dst reg, only used on 3 regs instr. 19 // shamt - only used on shift instructions, contains the shift amount. 20 // funct - combined with opcode field give us an operation code. 21 // 22 //===----------------------------------------------------------------------===// 23 24 // Format specifies the encoding used by the instruction. This is part of the 25 // ad-hoc solution used to emit machine instruction encodings by our machine 26 // code emitter. 27 class Format<bits<4> val> { 28 bits<4> Value = val; 29 } 30 31 def Pseudo : Format<0>; 32 def FrmR : Format<1>; 33 def FrmI : Format<2>; 34 def FrmJ : Format<3>; 35 def FrmFR : Format<4>; 36 def FrmFI : Format<5>; 37 def FrmOther : Format<6>; // Instruction w/ a custom format 38 39 class MMRel; 40 41 def Std2MicroMips : InstrMapping { 42 let FilterClass = "MMRel"; 43 // Instructions with the same BaseOpcode and isNVStore values form a row. 44 let RowFields = ["BaseOpcode"]; 45 // Instructions with the same predicate sense form a column. 46 let ColFields = ["Arch"]; 47 // The key column is the unpredicated instructions. 48 let KeyCol = ["se"]; 49 // Value columns are PredSense=true and PredSense=false 50 let ValueCols = [["se"], ["micromips"]]; 51 } 52 53 class StdArch { 54 string Arch = "se"; 55 } 56 57 // Generic Mips Format 58 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 59 InstrItinClass itin, Format f>: Instruction 60 { 61 field bits<32> Inst; 62 Format Form = f; 63 64 let Namespace = "Mips"; 65 66 let Size = 4; 67 68 bits<6> Opcode = 0; 69 70 // Top 6 bits are the 'opcode' field 71 let Inst{31-26} = Opcode; 72 73 let OutOperandList = outs; 74 let InOperandList = ins; 75 76 let AsmString = asmstr; 77 let Pattern = pattern; 78 let Itinerary = itin; 79 80 // 81 // Attributes specific to Mips instructions... 82 // 83 bits<4> FormBits = Form.Value; 84 85 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 86 let TSFlags{3-0} = FormBits; 87 88 let DecoderNamespace = "Mips"; 89 90 field bits<32> SoftFail = 0; 91 } 92 93 // Mips32/64 Instruction Format 94 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 95 InstrItinClass itin, Format f, string opstr = ""> : 96 MipsInst<outs, ins, asmstr, pattern, itin, f> { 97 let Predicates = [HasStdEnc]; 98 string BaseOpcode = opstr; 99 string Arch; 100 } 101 102 // Mips Pseudo Instructions Format 103 class MipsPseudo<dag outs, dag ins, list<dag> pattern, 104 InstrItinClass itin = IIPseudo> : 105 MipsInst<outs, ins, "", pattern, itin, Pseudo> { 106 let isCodeGenOnly = 1; 107 let isPseudo = 1; 108 } 109 110 // Mips32/64 Pseudo Instruction Format 111 class PseudoSE<dag outs, dag ins, list<dag> pattern, 112 InstrItinClass itin = IIPseudo>: 113 MipsPseudo<outs, ins, pattern, itin> { 114 let Predicates = [HasStdEnc]; 115 } 116 117 // Pseudo-instructions for alternate assembly syntax (never used by codegen). 118 // These are aliases that require C++ handling to convert to the target 119 // instruction, while InstAliases can be handled directly by tblgen. 120 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 121 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> { 122 let isPseudo = 1; 123 let Pattern = []; 124 } 125 //===----------------------------------------------------------------------===// 126 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 127 //===----------------------------------------------------------------------===// 128 129 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 130 list<dag> pattern, InstrItinClass itin>: 131 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 132 { 133 bits<5> rd; 134 bits<5> rs; 135 bits<5> rt; 136 bits<5> shamt; 137 bits<6> funct; 138 139 let Opcode = op; 140 let funct = _funct; 141 142 let Inst{25-21} = rs; 143 let Inst{20-16} = rt; 144 let Inst{15-11} = rd; 145 let Inst{10-6} = shamt; 146 let Inst{5-0} = funct; 147 } 148 149 //===----------------------------------------------------------------------===// 150 // Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 151 //===----------------------------------------------------------------------===// 152 153 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 154 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 155 { 156 bits<5> rt; 157 bits<5> rs; 158 bits<16> imm16; 159 160 let Opcode = op; 161 162 let Inst{25-21} = rs; 163 let Inst{20-16} = rt; 164 let Inst{15-0} = imm16; 165 } 166 167 class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 168 list<dag> pattern, InstrItinClass itin>: 169 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 170 { 171 bits<5> rs; 172 bits<5> rt; 173 bits<16> imm16; 174 175 let Opcode = op; 176 177 let Inst{25-21} = rs; 178 let Inst{20-16} = rt; 179 let Inst{15-0} = imm16; 180 } 181 182 //===----------------------------------------------------------------------===// 183 // Format J instruction class in Mips : <|opcode|address|> 184 //===----------------------------------------------------------------------===// 185 186 class FJ<bits<6> op> 187 { 188 bits<26> target; 189 190 bits<32> Inst; 191 192 let Inst{31-26} = op; 193 let Inst{25-0} = target; 194 } 195 196 //===----------------------------------------------------------------------===// 197 // MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 198 //===----------------------------------------------------------------------===// 199 class MFC3OP_FM<bits<6> op, bits<5> mfmt> 200 { 201 bits<5> rt; 202 bits<5> rd; 203 bits<3> sel; 204 205 bits<32> Inst; 206 207 let Inst{31-26} = op; 208 let Inst{25-21} = mfmt; 209 let Inst{20-16} = rt; 210 let Inst{15-11} = rd; 211 let Inst{10-3} = 0; 212 let Inst{2-0} = sel; 213 } 214 215 class ADD_FM<bits<6> op, bits<6> funct> : StdArch { 216 bits<5> rd; 217 bits<5> rs; 218 bits<5> rt; 219 220 bits<32> Inst; 221 222 let Inst{31-26} = op; 223 let Inst{25-21} = rs; 224 let Inst{20-16} = rt; 225 let Inst{15-11} = rd; 226 let Inst{10-6} = 0; 227 let Inst{5-0} = funct; 228 } 229 230 class ADDI_FM<bits<6> op> : StdArch { 231 bits<5> rs; 232 bits<5> rt; 233 bits<16> imm16; 234 235 bits<32> Inst; 236 237 let Inst{31-26} = op; 238 let Inst{25-21} = rs; 239 let Inst{20-16} = rt; 240 let Inst{15-0} = imm16; 241 } 242 243 class SRA_FM<bits<6> funct, bit rotate> : StdArch { 244 bits<5> rd; 245 bits<5> rt; 246 bits<5> shamt; 247 248 bits<32> Inst; 249 250 let Inst{31-26} = 0; 251 let Inst{25-22} = 0; 252 let Inst{21} = rotate; 253 let Inst{20-16} = rt; 254 let Inst{15-11} = rd; 255 let Inst{10-6} = shamt; 256 let Inst{5-0} = funct; 257 } 258 259 class SRLV_FM<bits<6> funct, bit rotate> : StdArch { 260 bits<5> rd; 261 bits<5> rt; 262 bits<5> rs; 263 264 bits<32> Inst; 265 266 let Inst{31-26} = 0; 267 let Inst{25-21} = rs; 268 let Inst{20-16} = rt; 269 let Inst{15-11} = rd; 270 let Inst{10-7} = 0; 271 let Inst{6} = rotate; 272 let Inst{5-0} = funct; 273 } 274 275 class BEQ_FM<bits<6> op> { 276 bits<5> rs; 277 bits<5> rt; 278 bits<16> offset; 279 280 bits<32> Inst; 281 282 let Inst{31-26} = op; 283 let Inst{25-21} = rs; 284 let Inst{20-16} = rt; 285 let Inst{15-0} = offset; 286 } 287 288 class BGEZ_FM<bits<6> op, bits<5> funct> { 289 bits<5> rs; 290 bits<16> offset; 291 292 bits<32> Inst; 293 294 let Inst{31-26} = op; 295 let Inst{25-21} = rs; 296 let Inst{20-16} = funct; 297 let Inst{15-0} = offset; 298 } 299 300 class B_FM { 301 bits<16> offset; 302 303 bits<32> Inst; 304 305 let Inst{31-26} = 4; 306 let Inst{25-21} = 0; 307 let Inst{20-16} = 0; 308 let Inst{15-0} = offset; 309 } 310 311 class SLTI_FM<bits<6> op> : StdArch { 312 bits<5> rt; 313 bits<5> rs; 314 bits<16> imm16; 315 316 bits<32> Inst; 317 318 let Inst{31-26} = op; 319 let Inst{25-21} = rs; 320 let Inst{20-16} = rt; 321 let Inst{15-0} = imm16; 322 } 323 324 class MFLO_FM<bits<6> funct> { 325 bits<5> rd; 326 327 bits<32> Inst; 328 329 let Inst{31-26} = 0; 330 let Inst{25-16} = 0; 331 let Inst{15-11} = rd; 332 let Inst{10-6} = 0; 333 let Inst{5-0} = funct; 334 } 335 336 class MTLO_FM<bits<6> funct> { 337 bits<5> rs; 338 339 bits<32> Inst; 340 341 let Inst{31-26} = 0; 342 let Inst{25-21} = rs; 343 let Inst{20-6} = 0; 344 let Inst{5-0} = funct; 345 } 346 347 class SEB_FM<bits<5> funct, bits<6> funct2> { 348 bits<5> rd; 349 bits<5> rt; 350 351 bits<32> Inst; 352 353 let Inst{31-26} = 0x1f; 354 let Inst{25-21} = 0; 355 let Inst{20-16} = rt; 356 let Inst{15-11} = rd; 357 let Inst{10-6} = funct; 358 let Inst{5-0} = funct2; 359 } 360 361 class CLO_FM<bits<6> funct> { 362 bits<5> rd; 363 bits<5> rs; 364 bits<5> rt; 365 366 bits<32> Inst; 367 368 let Inst{31-26} = 0x1c; 369 let Inst{25-21} = rs; 370 let Inst{20-16} = rt; 371 let Inst{15-11} = rd; 372 let Inst{10-6} = 0; 373 let Inst{5-0} = funct; 374 let rt = rd; 375 } 376 377 class LUI_FM { 378 bits<5> rt; 379 bits<16> imm16; 380 381 bits<32> Inst; 382 383 let Inst{31-26} = 0xf; 384 let Inst{25-21} = 0; 385 let Inst{20-16} = rt; 386 let Inst{15-0} = imm16; 387 } 388 389 class JALR_FM { 390 bits<5> rd; 391 bits<5> rs; 392 393 bits<32> Inst; 394 395 let Inst{31-26} = 0; 396 let Inst{25-21} = rs; 397 let Inst{20-16} = 0; 398 let Inst{15-11} = rd; 399 let Inst{10-6} = 0; 400 let Inst{5-0} = 9; 401 } 402 403 class BGEZAL_FM<bits<5> funct> { 404 bits<5> rs; 405 bits<16> offset; 406 407 bits<32> Inst; 408 409 let Inst{31-26} = 1; 410 let Inst{25-21} = rs; 411 let Inst{20-16} = funct; 412 let Inst{15-0} = offset; 413 } 414 415 class SYNC_FM { 416 bits<5> stype; 417 418 bits<32> Inst; 419 420 let Inst{31-26} = 0; 421 let Inst{10-6} = stype; 422 let Inst{5-0} = 0xf; 423 } 424 425 class MULT_FM<bits<6> op, bits<6> funct> : StdArch { 426 bits<5> rs; 427 bits<5> rt; 428 429 bits<32> Inst; 430 431 let Inst{31-26} = op; 432 let Inst{25-21} = rs; 433 let Inst{20-16} = rt; 434 let Inst{15-6} = 0; 435 let Inst{5-0} = funct; 436 } 437 438 class EXT_FM<bits<6> funct> { 439 bits<5> rt; 440 bits<5> rs; 441 bits<5> pos; 442 bits<5> size; 443 444 bits<32> Inst; 445 446 let Inst{31-26} = 0x1f; 447 let Inst{25-21} = rs; 448 let Inst{20-16} = rt; 449 let Inst{15-11} = size; 450 let Inst{10-6} = pos; 451 let Inst{5-0} = funct; 452 } 453 454 class RDHWR_FM { 455 bits<5> rt; 456 bits<5> rd; 457 458 bits<32> Inst; 459 460 let Inst{31-26} = 0x1f; 461 let Inst{25-21} = 0; 462 let Inst{20-16} = rt; 463 let Inst{15-11} = rd; 464 let Inst{10-6} = 0; 465 let Inst{5-0} = 0x3b; 466 } 467 468 class TEQ_FM<bits<6> funct> { 469 bits<5> rs; 470 bits<5> rt; 471 bits<10> code_; 472 473 bits<32> Inst; 474 475 let Inst{31-26} = 0; 476 let Inst{25-21} = rs; 477 let Inst{20-16} = rt; 478 let Inst{15-6} = code_; 479 let Inst{5-0} = funct; 480 } 481 482 //===----------------------------------------------------------------------===// 483 // System calls format <op|code_|funct> 484 //===----------------------------------------------------------------------===// 485 486 class SYS_FM<bits<6> funct> 487 { 488 bits<20> code_; 489 bits<32> Inst; 490 let Inst{31-26} = 0x0; 491 let Inst{25-6} = code_; 492 let Inst{5-0} = funct; 493 } 494 495 //===----------------------------------------------------------------------===// 496 // Break instruction format <op|code_1|funct> 497 //===----------------------------------------------------------------------===// 498 499 class BRK_FM<bits<6> funct> 500 { 501 bits<10> code_1; 502 bits<10> code_2; 503 bits<32> Inst; 504 let Inst{31-26} = 0x0; 505 let Inst{25-16} = code_1; 506 let Inst{15-6} = code_2; 507 let Inst{5-0} = funct; 508 } 509 510 //===----------------------------------------------------------------------===// 511 // Exception return format <Cop0|1|0|funct> 512 //===----------------------------------------------------------------------===// 513 514 class ER_FM<bits<6> funct> 515 { 516 bits<32> Inst; 517 let Inst{31-26} = 0x10; 518 let Inst{25} = 1; 519 let Inst{24-6} = 0; 520 let Inst{5-0} = funct; 521 } 522 523 //===----------------------------------------------------------------------===// 524 // 525 // FLOATING POINT INSTRUCTION FORMATS 526 // 527 // opcode - operation code. 528 // fs - src reg. 529 // ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 530 // fd - dst reg, only used on 3 regs instr. 531 // fmt - double or single precision. 532 // funct - combined with opcode field give us an operation code. 533 // 534 //===----------------------------------------------------------------------===// 535 536 //===----------------------------------------------------------------------===// 537 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 538 //===----------------------------------------------------------------------===// 539 540 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 541 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 542 { 543 bits<5> ft; 544 bits<5> base; 545 bits<16> imm16; 546 547 let Opcode = op; 548 549 let Inst{25-21} = base; 550 let Inst{20-16} = ft; 551 let Inst{15-0} = imm16; 552 } 553 554 class ADDS_FM<bits<6> funct, bits<5> fmt> { 555 bits<5> fd; 556 bits<5> fs; 557 bits<5> ft; 558 559 bits<32> Inst; 560 561 let Inst{31-26} = 0x11; 562 let Inst{25-21} = fmt; 563 let Inst{20-16} = ft; 564 let Inst{15-11} = fs; 565 let Inst{10-6} = fd; 566 let Inst{5-0} = funct; 567 } 568 569 class ABSS_FM<bits<6> funct, bits<5> fmt> { 570 bits<5> fd; 571 bits<5> fs; 572 573 bits<32> Inst; 574 575 let Inst{31-26} = 0x11; 576 let Inst{25-21} = fmt; 577 let Inst{20-16} = 0; 578 let Inst{15-11} = fs; 579 let Inst{10-6} = fd; 580 let Inst{5-0} = funct; 581 } 582 583 class MFC1_FM<bits<5> funct> { 584 bits<5> rt; 585 bits<5> fs; 586 587 bits<32> Inst; 588 589 let Inst{31-26} = 0x11; 590 let Inst{25-21} = funct; 591 let Inst{20-16} = rt; 592 let Inst{15-11} = fs; 593 let Inst{10-0} = 0; 594 } 595 596 class LW_FM<bits<6> op> : StdArch { 597 bits<5> rt; 598 bits<21> addr; 599 600 bits<32> Inst; 601 602 let Inst{31-26} = op; 603 let Inst{25-21} = addr{20-16}; 604 let Inst{20-16} = rt; 605 let Inst{15-0} = addr{15-0}; 606 } 607 608 class MADDS_FM<bits<3> funct, bits<3> fmt> { 609 bits<5> fd; 610 bits<5> fr; 611 bits<5> fs; 612 bits<5> ft; 613 614 bits<32> Inst; 615 616 let Inst{31-26} = 0x13; 617 let Inst{25-21} = fr; 618 let Inst{20-16} = ft; 619 let Inst{15-11} = fs; 620 let Inst{10-6} = fd; 621 let Inst{5-3} = funct; 622 let Inst{2-0} = fmt; 623 } 624 625 class LWXC1_FM<bits<6> funct> { 626 bits<5> fd; 627 bits<5> base; 628 bits<5> index; 629 630 bits<32> Inst; 631 632 let Inst{31-26} = 0x13; 633 let Inst{25-21} = base; 634 let Inst{20-16} = index; 635 let Inst{15-11} = 0; 636 let Inst{10-6} = fd; 637 let Inst{5-0} = funct; 638 } 639 640 class SWXC1_FM<bits<6> funct> { 641 bits<5> fs; 642 bits<5> base; 643 bits<5> index; 644 645 bits<32> Inst; 646 647 let Inst{31-26} = 0x13; 648 let Inst{25-21} = base; 649 let Inst{20-16} = index; 650 let Inst{15-11} = fs; 651 let Inst{10-6} = 0; 652 let Inst{5-0} = funct; 653 } 654 655 class BC1F_FM<bit nd, bit tf> { 656 bits<3> fcc; 657 bits<16> offset; 658 659 bits<32> Inst; 660 661 let Inst{31-26} = 0x11; 662 let Inst{25-21} = 0x8; 663 let Inst{20-18} = fcc; 664 let Inst{17} = nd; 665 let Inst{16} = tf; 666 let Inst{15-0} = offset; 667 } 668 669 class CEQS_FM<bits<5> fmt> { 670 bits<5> fs; 671 bits<5> ft; 672 bits<4> cond; 673 674 bits<32> Inst; 675 676 let Inst{31-26} = 0x11; 677 let Inst{25-21} = fmt; 678 let Inst{20-16} = ft; 679 let Inst{15-11} = fs; 680 let Inst{10-8} = 0; // cc 681 let Inst{7-4} = 0x3; 682 let Inst{3-0} = cond; 683 } 684 685 class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 686 let cond = c; 687 } 688 689 class CMov_I_F_FM<bits<6> funct, bits<5> fmt> { 690 bits<5> fd; 691 bits<5> fs; 692 bits<5> rt; 693 694 bits<32> Inst; 695 696 let Inst{31-26} = 0x11; 697 let Inst{25-21} = fmt; 698 let Inst{20-16} = rt; 699 let Inst{15-11} = fs; 700 let Inst{10-6} = fd; 701 let Inst{5-0} = funct; 702 } 703 704 class CMov_F_I_FM<bit tf> { 705 bits<5> rd; 706 bits<5> rs; 707 bits<3> fcc; 708 709 bits<32> Inst; 710 711 let Inst{31-26} = 0; 712 let Inst{25-21} = rs; 713 let Inst{20-18} = fcc; 714 let Inst{17} = 0; 715 let Inst{16} = tf; 716 let Inst{15-11} = rd; 717 let Inst{10-6} = 0; 718 let Inst{5-0} = 1; 719 } 720 721 class CMov_F_F_FM<bits<5> fmt, bit tf> { 722 bits<5> fd; 723 bits<5> fs; 724 bits<3> fcc; 725 726 bits<32> Inst; 727 728 let Inst{31-26} = 0x11; 729 let Inst{25-21} = fmt; 730 let Inst{20-18} = fcc; 731 let Inst{17} = 0; 732 let Inst{16} = tf; 733 let Inst{15-11} = fs; 734 let Inst{10-6} = fd; 735 let Inst{5-0} = 0x11; 736 } 737
