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  /external/pixman/pixman/
pixman-arm-neon-asm.h 112 .macro pixldst numbytes, op, elem_size, basereg, mem_operand, abits variable
114 pixldst4 op, elem_size, %(basereg+4), %(basereg+5), \ variable
115 %(basereg+6), %(basereg+7), mem_operand, abits variable
117 pixldst2 op, elem_size, %(basereg+2), %(basereg+3), mem_operand, abits variable
119 pixldst1 op, elem_size, %(basereg+1), mem_operand, abits variable
122 pixldst0 op, 32, %(basereg+0), 1, mem_operand, abits variable
124 pixldst0 op, 16, %(basereg+0), 2, mem_operand, abit variable
125 pixldst0 op, 16, %(basereg+0), 3, mem_operand, abits variable
127 pixldst0 op, 8, %(basereg+0), 4, mem_operand, abits variable
128 pixldst0 op, 8, %(basereg+0), 5, mem_operand, abits variable
129 pixldst0 op, 8, %(basereg+0), 6, mem_operand, abits variable
130 pixldst0 op, 8, %(basereg+0), 7, mem_operand, abits variable
134 pixldst0 op, 16, %(basereg+0), 1, mem_operand, abits variable
136 pixldst0 op, 8, %(basereg+0), 2, mem_operand, abits variable
137 pixldst0 op, 8, %(basereg+0), 3, mem_operand, abits variable
140 pixldst0 op, 8, %(basereg+0), 1, mem_operand, abits variable
146 .macro pixld numpix, bpp, basereg, mem_operand, abits=0 variable
149 pixldst4 vld4, 8, %(basereg+4), %(basereg+5), \\ variable
150 %(basereg+6), %(basereg+7), mem_operand, abits variable
152 pixldst3 vld3, 8, %(basereg+3), %(basereg+4), %(basereg+5), mem_operand variable
154 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 4, mem_operand variable
155 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 5, mem_operand variable
156 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 6, mem_operand variable
157 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 7, mem_operand variable
159 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 2, mem_operand variable
160 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 3, mem_operand variable
162 pixldst30 vld3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 1, mem_operand variable
169 .macro pixst numpix, bpp, basereg, mem_operand, abits=0 variable
172 pixldst4 vst4, 8, %(basereg+4), %(basereg+5), \\ variable
173 %(basereg+6), %(basereg+7), mem_operand, abits variable
175 pixldst3 vst3, 8, %(basereg+3), %(basereg+4), %(basereg+5), mem_operand variable
177 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 4, mem_operand variable
178 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 5, mem_operand variable
179 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 6, mem_operand variable
180 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 7, mem_operand variable
182 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 2, mem_operand variable
183 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 3, mem_operand variable
185 pixldst30 vst3, 8, %(basereg+0), %(basereg+1), %(basereg+2), 1, mem_operand variable
192 .macro pixld_a numpix, bpp, basereg, mem_operand variable
194 pixld numpix, bpp, basereg, mem_operand, %(bpp * numpix) variable
196 pixld numpix, bpp, basereg, mem_operand, 128 variable
200 .macro pixst_a numpix, bpp, basereg, mem_operand variable
202 pixst numpix, bpp, basereg, mem_operand, %(bpp * numpix) variable
204 pixst numpix, bpp, basereg, mem_operand, 128 variable
298 .macro pixld_s_internal numbytes, elem_size, basereg, mem_operand variable
300 pixld2_s elem_size, %(basereg+4), %(basereg+5), mem_operand variable
301 pixld2_s elem_size, %(basereg+6), %(basereg+7), mem_operand variable
304 pixld2_s elem_size, %(basereg+2), %(basereg+3), mem_operand variable
306 pixld1_s elem_size, %(basereg+1), mem_operand variable
309 pixld0_s elem_size, %(basereg+0), 1, mem_operand variable
311 pixld0_s elem_size, %(basereg+0), 2, mem_operand variable
312 pixld0_s elem_size, %(basereg+0), 3, mem_operand variable
314 pixld0_s elem_size, %(basereg+0), 4, mem_operand variable
315 pixld0_s elem_size, %(basereg+0), 5, mem_operand variable
316 pixld0_s elem_size, %(basereg+0), 6, mem_operand variable
317 pixld0_s elem_size, %(basereg+0), 7, mem_operand variable
321 pixld0_s elem_size, %(basereg+0), 1, mem_operand variable
323 pixld0_s elem_size, %(basereg+0), 2, mem_operand variable
324 pixld0_s elem_size, %(basereg+0), 3, mem_operand variable
327 pixld0_s elem_size, %(basereg+0), 1, mem_operand variable
333 .macro pixld_s numpix, bpp, basereg, mem_operand variable
    [all...]
  /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/
x86expr.c 672 int basereg = REG3264_NONE; /* "base" register (for SIB) */ local
723 /* Find a basereg (*1, but not indexreg), if there is one.
734 basereg == REG3264_NONE)
735 basereg = i;
742 * Also check basereg (must be a GPR if present) and indexreg
745 if (basereg >= SIMDREGS &&
747 int temp = basereg;
748 basereg = indexreg;
751 if (basereg >= REG64_RIP || indexreg < SIMDREGS) {
756 } else if (indexreg != REG3264_NONE && basereg == REG3264_NONE
    [all...]
  /external/llvm/lib/Target/ARM/
Thumb1RegisterInfo.cpp 86 /// a destreg = basereg + immediate in Thumb code. Materialize the immediate
93 unsigned DestReg, unsigned BaseReg,
100 (BaseReg != 0 && !isARMLowRegister(BaseReg));
112 assert(BaseReg == ARM::SP && "Unexpected!");
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
166 /// a destreg = basereg + immediate in Thumb code.
170 unsigned DestReg, unsigned BaseReg,
186 if (DestReg == BaseReg && BaseReg == ARM::SP)
    [all...]
Thumb2InstrInfo.cpp 214 unsigned DestReg, unsigned BaseReg, int NumBytes,
222 if (DestReg != ARM::SP && DestReg != BaseReg &&
244 .addReg(BaseReg, RegState::Kill)
251 .addReg(BaseReg, RegState::Kill)
262 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
265 .addReg(BaseReg).setMIFlags(MIFlags));
266 BaseReg = ARM::SP;
271 if (BaseReg == ARM::SP) {
277 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
295 assert(DestReg != ARM::SP && BaseReg != ARM::SP)
    [all...]
Thumb1RegisterInfo.h 53 unsigned BaseReg, int64_t Offset) const;
ARMBaseRegisterInfo.h 140 unsigned BaseReg, int FrameIdx,
143 unsigned BaseReg, int64_t Offset) const;
ARMBaseInstrInfo.h 382 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
386 unsigned DestReg, unsigned BaseReg, int NumBytes,
392 unsigned DestReg, unsigned BaseReg, int NumBytes,
397 unsigned DestReg, unsigned BaseReg,
ARMBaseRegisterInfo.cpp 559 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
563 unsigned BaseReg, int FrameIdx,
578 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
580 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
589 unsigned BaseReg, int64_t Offset) const {
608 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
611 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
ARMLoadStoreOptimizer.cpp     [all...]
Thumb2SizeReduction.cpp 127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
420 unsigned BaseReg = MI->getOperand(0).getReg();
421 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
428 if (MI->getOperand(i).getReg() == BaseReg) {
442 unsigned BaseReg = MI->getOperand(1).getReg();
443 if (BaseReg != ARM::SP)
456 unsigned BaseReg = MI->getOperand(1).getReg();
457 if (BaseReg == ARM::SP &&
462 } else if (!isARMLowRegister(BaseReg) ||
    [all...]
  /external/llvm/test/CodeGen/X86/
vec_shuffle-26.ll 45 ; CHECK: movhps ([[BASEREG:%[a-z]+]]),
46 ; CHECK: extractps ${{[0-9]+}}, %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
47 ; CHECK: extractps ${{[0-9]+}}, %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
49 ; ATOM: movhps ([[BASEREG:%[a-z]+]]),
50 ; ATOM: movd %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
51 ; ATOM: movd %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.cpp 140 unsigned BaseReg =
143 BaseReg, FrameReg, BaseReg, Offset);
144 FrameReg = BaseReg;
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 204 unsigned BaseReg, IndexReg, TmpReg, Scale;
213 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
217 unsigned getBaseReg() { return BaseReg; }
246 // If we already have a BaseReg, then assume this is the IndexReg with
248 if (!BaseReg) {
249 BaseReg = TmpReg;
251 assert (!IndexReg && "BaseReg/IndexReg already set!");
282 // If we already have a BaseReg, then assume this is the IndexReg with
284 if (!BaseReg) {
285 BaseReg = TmpReg
1010 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local
1020 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.h 86 unsigned BaseReg, int FrameIdx,
89 unsigned BaseReg, int64_t Offset) const;
PPCRegisterInfo.cpp 798 /// Insert defining instruction(s) for BaseReg to
802 unsigned BaseReg, int FrameIdx,
815 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
817 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
823 unsigned BaseReg, int64_t Offset) const {
833 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
  /external/llvm/lib/Target/X86/InstPrinter/
X86ATTInstPrinter.cpp 175 const MCOperand &BaseReg = MI->getOperand(Op);
190 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
197 if (IndexReg.getReg() || BaseReg.getReg()) {
199 if (BaseReg.getReg())
X86IntelInstPrinter.cpp 154 const MCOperand &BaseReg = MI->getOperand(Op);
169 if (BaseReg.getReg()) {
188 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
  /external/llvm/lib/Target/X86/Disassembler/
X86Disassembler.cpp 372 // 1. basereg (register) The R/M base, or (if there is a SIB) the
383 MCOperand baseReg;
398 baseReg = MCOperand::CreateReg(X86::x); break;
403 baseReg = MCOperand::CreateReg(0);
470 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
473 baseReg = MCOperand::CreateReg(0);
478 baseReg = MCOperand::CreateReg(X86::BX);
482 baseReg = MCOperand::CreateReg(X86::BX);
486 baseReg = MCOperand::CreateReg(X86::BP);
490 baseReg = MCOperand::CreateReg(X86::BP)
    [all...]
  /external/llvm/lib/CodeGen/
LocalStackSlotAllocation.cpp 271 unsigned BaseReg = 0;
309 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
343 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
345 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
351 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
362 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
366 TRI->resolveFrameIndex(I, BaseReg, Offset);
MachineScheduler.cpp 781 unsigned BaseReg;
784 : SU(su), BaseReg(reg), Offset(ofs) {}
805 if (LHS.BaseReg != RHS.BaseReg)
806 return LHS.BaseReg < RHS.BaseReg;
815 unsigned BaseReg;
817 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
818 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset));
825 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg)
    [all...]
  /external/llvm/lib/Target/X86/
X86CodeEmitter.cpp 484 unsigned BaseReg = Base.getReg();
487 if (BaseReg == X86::RIP ||
502 // If no BaseReg, issue a RIP relative instruction only if the MCE can
506 if (BaseReg != 0 && BaseReg != X86::RIP)
507 BaseRegNo = getX86RegNum(BaseReg);
517 (!Is64BitMode || BaseReg != 0)) {
518 if (BaseReg == 0 || // [disp32] in X86-32 mode
519 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
553 if (BaseReg == 0)
    [all...]
X86AsmPrinter.cpp 272 const MachineOperand &BaseReg = MI->getOperand(Op);
277 bool HasBaseReg = BaseReg.getReg() != 0;
279 BaseReg.getReg() == X86::RIP)
331 const MachineOperand &BaseReg = MI->getOperand(Op);
346 if (BaseReg.getReg()) {
364 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 221 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
224 if ((BaseReg.getReg() != 0 &&
225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
236 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
239 if ((BaseReg.getReg() != 0 &&
240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
251 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
254 if ((BaseReg.getReg() != 0 &&
255 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
374 unsigned BaseReg = Base.getReg()
    [all...]
  /dalvik/vm/compiler/codegen/x86/libenc/
enc_wrapper.cpp 52 inline void add_m(EncoderBase::Operands & args, int baseReg, int disp, OpndSize sz, OpndExt ext = OpndExt_None) {
54 map_of_regno_2_regname[baseReg],
58 inline void add_m_scale(EncoderBase::Operands & args, int baseReg, int indexReg, int scale,
61 map_of_regno_2_regname[baseReg],
65 inline void add_m_disp_scale(EncoderBase::Operands & args, int baseReg, int disp, int indexReg, int scale,
68 map_of_regno_2_regname[baseReg],
  /external/llvm/lib/Transforms/Scalar/
CodeGenPrepare.cpp 830 Value *BaseReg;
832 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
837 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
861 if (BaseReg) {
864 WriteAsOperand(OS, BaseReg, /*PrintType=*/false);
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