| /external/llvm/test/MC/Mips/ |
| micromips-shift-instructions.s | 12 # CHECK: srlv $2, $3, $5 # encoding: [0x50,0x10,0x65,0x00]
20 srlv $2, $3, $5
|
| mips-alu-instructions.s | 31 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
62 srlv $2, $3, $5
|
| mips64-alu-instructions.s | 29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
57 srlv $2, $3, $5
|
| /external/llvm/test/CodeGen/Mips/ |
| srl2.ll | 13 ; 16: srlv ${{[0-9]+}}, ${{[0-9]+}}
|
| atomic.ll | 132 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
158 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
189 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
215 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
247 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
274 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
304 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
329 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
364 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
394 ; CHECK-EB: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]
[all...] |
| /external/valgrind/main/none/tests/mips32/ |
| MIPS32int.c | [all...] |
| MIPS32int.stdout.exp | [all...] |
| MIPS32int.stdout.exp-BE | [all...] |
| MIPS32int.stdout.exp-mips32 | [all...] |
| /external/chromium_org/v8/test/cctest/ |
| test-disasm-mips.cc | 242 COMPARE(srlv(a0, a1, a2),
243 "00c52006 srlv a0, a1, a2");
244 COMPARE(srlv(s0, s1, s2),
245 "02518006 srlv s0, s1, s2");
246 COMPARE(srlv(t2, t3, t4),
247 "018b5006 srlv t2, t3, t4");
248 COMPARE(srlv(v0, v1, fp),
249 "03c31006 srlv v0, v1, fp");
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 252 COMPARE(srlv(a0, a1, a2),
253 "00c52006 srlv a0, a1, a2");
254 COMPARE(srlv(s0, s1, s2),
255 "02518006 srlv s0, s1, s2");
256 COMPARE(srlv(t2, t3, t4),
257 "018b5006 srlv t2, t3, t4");
258 COMPARE(srlv(v0, v1, fp),
259 "03c31006 srlv v0, v1, fp");
|
| /external/kernel-headers/original/asm-mips/ |
| asm.h | 265 #define INT_SRLV srlv
302 #define LONG_SRLV srlv
351 #define PTR_SRLV srlv
|
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrInfo.td | 49 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
|
| /bionic/libc/kernel/arch-mips/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /external/chromium_org/v8/src/mips/ |
| constants-mips.cc | 251 case SRLV:
|
| /external/v8/src/mips/ |
| constants-mips.cc | 247 case SRLV:
|
| /art/runtime/ |
| disassembler_mips.cc | 59 { kRTypeMask, 6, "srlv", "DTS", },
|
| /art/compiler/utils/mips/ |
| assembler_mips.h | 247 void Srlv(Register rd, Register rs, Register rt);
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 389 # CHECK: srlv $2, $3, $5
|
