1 ; RUN: llc -march=mipsel --disable-machine-licm < %s | FileCheck %s -check-prefix=CHECK-EL 2 ; RUN: llc -march=mips --disable-machine-licm < %s | FileCheck %s -check-prefix=CHECK-EB 3 4 @x = common global i32 0, align 4 5 6 define i32 @AtomicLoadAdd32(i32 %incr) nounwind { 7 entry: 8 %0 = atomicrmw add i32* @x, i32 %incr monotonic 9 ret i32 %0 10 11 ; CHECK-EL-LABEL: AtomicLoadAdd32: 12 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(x) 13 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 14 ; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]]) 15 ; CHECK-EL: addu $[[R2:[0-9]+]], $[[R1]], $4 16 ; CHECK-EL: sc $[[R2]], 0($[[R0]]) 17 ; CHECK-EL: beqz $[[R2]], $[[BB0]] 18 19 ; CHECK-EB-LABEL: AtomicLoadAdd32: 20 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(x) 21 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 22 ; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]]) 23 ; CHECK-EB: addu $[[R2:[0-9]+]], $[[R1]], $4 24 ; CHECK-EB: sc $[[R2]], 0($[[R0]]) 25 ; CHECK-EB: beqz $[[R2]], $[[BB0]] 26 } 27 28 define i32 @AtomicLoadNand32(i32 %incr) nounwind { 29 entry: 30 %0 = atomicrmw nand i32* @x, i32 %incr monotonic 31 ret i32 %0 32 33 ; CHECK-EL-LABEL: AtomicLoadNand32: 34 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(x) 35 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 36 ; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]]) 37 ; CHECK-EL: and $[[R3:[0-9]+]], $[[R1]], $4 38 ; CHECK-EL: nor $[[R2:[0-9]+]], $zero, $[[R3]] 39 ; CHECK-EL: sc $[[R2]], 0($[[R0]]) 40 ; CHECK-EL: beqz $[[R2]], $[[BB0]] 41 42 ; CHECK-EB-LABEL: AtomicLoadNand32: 43 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(x) 44 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 45 ; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]]) 46 ; CHECK-EB: and $[[R3:[0-9]+]], $[[R1]], $4 47 ; CHECK-EB: nor $[[R2:[0-9]+]], $zero, $[[R3]] 48 ; CHECK-EB: sc $[[R2]], 0($[[R0]]) 49 ; CHECK-EB: beqz $[[R2]], $[[BB0]] 50 } 51 52 define i32 @AtomicSwap32(i32 %newval) nounwind { 53 entry: 54 %newval.addr = alloca i32, align 4 55 store i32 %newval, i32* %newval.addr, align 4 56 %tmp = load i32* %newval.addr, align 4 57 %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic 58 ret i32 %0 59 60 ; CHECK-EL-LABEL: AtomicSwap32: 61 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(x) 62 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 63 ; CHECK-EL: ll ${{[0-9]+}}, 0($[[R0]]) 64 ; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]]) 65 ; CHECK-EL: beqz $[[R2]], $[[BB0]] 66 67 ; CHECK-EB-LABEL: AtomicSwap32: 68 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(x) 69 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 70 ; CHECK-EB: ll ${{[0-9]+}}, 0($[[R0]]) 71 ; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]]) 72 ; CHECK-EB: beqz $[[R2]], $[[BB0]] 73 } 74 75 define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind { 76 entry: 77 %newval.addr = alloca i32, align 4 78 store i32 %newval, i32* %newval.addr, align 4 79 %tmp = load i32* %newval.addr, align 4 80 %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic 81 ret i32 %0 82 83 ; CHECK-EL-LABEL: AtomicCmpSwap32: 84 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(x) 85 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 86 ; CHECK-EL: ll $2, 0($[[R0]]) 87 ; CHECK-EL: bne $2, $4, $[[BB1:[A-Z_0-9]+]] 88 ; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]]) 89 ; CHECK-EL: beqz $[[R2]], $[[BB0]] 90 ; CHECK-EL: $[[BB1]]: 91 92 ; CHECK-EB-LABEL: AtomicCmpSwap32: 93 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(x) 94 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 95 ; CHECK-EB: ll $2, 0($[[R0]]) 96 ; CHECK-EB: bne $2, $4, $[[BB1:[A-Z_0-9]+]] 97 ; CHECK-EB: sc $[[R2:[0-9]+]], 0($[[R0]]) 98 ; CHECK-EB: beqz $[[R2]], $[[BB0]] 99 ; CHECK-EB: $[[BB1]]: 100 } 101 102 103 104 @y = common global i8 0, align 1 105 106 define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { 107 entry: 108 %0 = atomicrmw add i8* @y, i8 %incr monotonic 109 ret i8 %0 110 111 ; CHECK-EL-LABEL: AtomicLoadAdd8: 112 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(y) 113 ; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4 114 ; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 115 ; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3 116 ; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3 117 ; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255 118 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] 119 ; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]] 120 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]] 121 122 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 123 ; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]]) 124 ; CHECK-EL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] 125 ; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] 126 ; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] 127 ; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 128 ; CHECK-EL: sc $[[R14]], 0($[[R2]]) 129 ; CHECK-EL: beqz $[[R14]], $[[BB0]] 130 131 ; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] 132 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] 133 ; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24 134 ; CHECK-EL: sra $2, $[[R17]], 24 135 136 ; CHECK-EB-LABEL: AtomicLoadAdd8: 137 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(y) 138 ; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4 139 ; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 140 ; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3 141 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 142 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 143 ; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255 144 ; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 145 ; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]] 146 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]] 147 148 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 149 ; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]]) 150 ; CHECK-EB: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] 151 ; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] 152 ; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 153 ; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 154 ; CHECK-EB: sc $[[R14]], 0($[[R2]]) 155 ; CHECK-EB: beqz $[[R14]], $[[BB0]] 156 157 ; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 158 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 159 ; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24 160 ; CHECK-EB: sra $2, $[[R17]], 24 161 } 162 163 define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { 164 entry: 165 %0 = atomicrmw sub i8* @y, i8 %incr monotonic 166 ret i8 %0 167 168 ; CHECK-EL-LABEL: AtomicLoadSub8: 169 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(y) 170 ; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4 171 ; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 172 ; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3 173 ; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3 174 ; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255 175 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] 176 ; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]] 177 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]] 178 179 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 180 ; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]]) 181 ; CHECK-EL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] 182 ; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] 183 ; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] 184 ; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 185 ; CHECK-EL: sc $[[R14]], 0($[[R2]]) 186 ; CHECK-EL: beqz $[[R14]], $[[BB0]] 187 188 ; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] 189 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] 190 ; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24 191 ; CHECK-EL: sra $2, $[[R17]], 24 192 193 ; CHECK-EB-LABEL: AtomicLoadSub8: 194 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(y) 195 ; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4 196 ; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 197 ; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3 198 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 199 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 200 ; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255 201 ; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 202 ; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]] 203 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]] 204 205 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 206 ; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]]) 207 ; CHECK-EB: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] 208 ; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] 209 ; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 210 ; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 211 ; CHECK-EB: sc $[[R14]], 0($[[R2]]) 212 ; CHECK-EB: beqz $[[R14]], $[[BB0]] 213 214 ; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 215 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 216 ; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24 217 ; CHECK-EB: sra $2, $[[R17]], 24 218 } 219 220 define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { 221 entry: 222 %0 = atomicrmw nand i8* @y, i8 %incr monotonic 223 ret i8 %0 224 225 ; CHECK-EL-LABEL: AtomicLoadNand8: 226 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(y) 227 ; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4 228 ; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 229 ; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3 230 ; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3 231 ; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255 232 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] 233 ; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]] 234 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]] 235 236 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 237 ; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]]) 238 ; CHECK-EL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] 239 ; CHECK-EL: nor $[[R11:[0-9]+]], $zero, $[[R18]] 240 ; CHECK-EL: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] 241 ; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] 242 ; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 243 ; CHECK-EL: sc $[[R14]], 0($[[R2]]) 244 ; CHECK-EL: beqz $[[R14]], $[[BB0]] 245 246 ; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] 247 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] 248 ; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24 249 ; CHECK-EL: sra $2, $[[R17]], 24 250 251 ; CHECK-EB-LABEL: AtomicLoadNand8: 252 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(y) 253 ; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4 254 ; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 255 ; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3 256 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 257 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 258 ; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255 259 ; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 260 ; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]] 261 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]] 262 263 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 264 ; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]]) 265 ; CHECK-EB: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] 266 ; CHECK-EB: nor $[[R11:[0-9]+]], $zero, $[[R18]] 267 ; CHECK-EB: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] 268 ; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 269 ; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] 270 ; CHECK-EB: sc $[[R14]], 0($[[R2]]) 271 ; CHECK-EB: beqz $[[R14]], $[[BB0]] 272 273 ; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 274 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 275 ; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24 276 ; CHECK-EB: sra $2, $[[R17]], 24 277 } 278 279 define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { 280 entry: 281 %0 = atomicrmw xchg i8* @y, i8 %newval monotonic 282 ret i8 %0 283 284 ; CHECK-EL-LABEL: AtomicSwap8: 285 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(y) 286 ; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4 287 ; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 288 ; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3 289 ; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3 290 ; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255 291 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] 292 ; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]] 293 ; CHECK-EL: sllv $[[R9:[0-9]+]], $4, $[[R4]] 294 295 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 296 ; CHECK-EL: ll $[[R10:[0-9]+]], 0($[[R2]]) 297 ; CHECK-EL: and $[[R18:[0-9]+]], $[[R9]], $[[R6]] 298 ; CHECK-EL: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] 299 ; CHECK-EL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]] 300 ; CHECK-EL: sc $[[R14]], 0($[[R2]]) 301 ; CHECK-EL: beqz $[[R14]], $[[BB0]] 302 303 ; CHECK-EL: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] 304 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]] 305 ; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24 306 ; CHECK-EL: sra $2, $[[R17]], 24 307 308 ; CHECK-EB-LABEL: AtomicSwap8: 309 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(y) 310 ; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4 311 ; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 312 ; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3 313 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 314 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 315 ; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255 316 ; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 317 ; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]] 318 ; CHECK-EB: sllv $[[R9:[0-9]+]], $4, $[[R5]] 319 320 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 321 ; CHECK-EB: ll $[[R10:[0-9]+]], 0($[[R2]]) 322 ; CHECK-EB: and $[[R18:[0-9]+]], $[[R9]], $[[R7]] 323 ; CHECK-EB: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] 324 ; CHECK-EB: or $[[R14:[0-9]+]], $[[R13]], $[[R18]] 325 ; CHECK-EB: sc $[[R14]], 0($[[R2]]) 326 ; CHECK-EB: beqz $[[R14]], $[[BB0]] 327 328 ; CHECK-EB: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] 329 ; CHECK-EB: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] 330 ; CHECK-EB: sll $[[R17:[0-9]+]], $[[R16]], 24 331 ; CHECK-EB: sra $2, $[[R17]], 24 332 } 333 334 define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind { 335 entry: 336 %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic 337 ret i8 %0 338 339 ; CHECK-EL-LABEL: AtomicCmpSwap8: 340 ; CHECK-EL: lw $[[R0:[0-9]+]], %got(y) 341 ; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4 342 ; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 343 ; CHECK-EL: andi $[[R3:[0-9]+]], $[[R0]], 3 344 ; CHECK-EL: sll $[[R4:[0-9]+]], $[[R3]], 3 345 ; CHECK-EL: ori $[[R5:[0-9]+]], $zero, 255 346 ; CHECK-EL: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]] 347 ; CHECK-EL: nor $[[R7:[0-9]+]], $zero, $[[R6]] 348 ; CHECK-EL: andi $[[R8:[0-9]+]], $4, 255 349 ; CHECK-EL: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]] 350 ; CHECK-EL: andi $[[R10:[0-9]+]], $5, 255 351 ; CHECK-EL: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]] 352 353 ; CHECK-EL: $[[BB0:[A-Z_0-9]+]]: 354 ; CHECK-EL: ll $[[R12:[0-9]+]], 0($[[R2]]) 355 ; CHECK-EL: and $[[R13:[0-9]+]], $[[R12]], $[[R6]] 356 ; CHECK-EL: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]] 357 358 ; CHECK-EL: and $[[R14:[0-9]+]], $[[R12]], $[[R7]] 359 ; CHECK-EL: or $[[R15:[0-9]+]], $[[R14]], $[[R11]] 360 ; CHECK-EL: sc $[[R15]], 0($[[R2]]) 361 ; CHECK-EL: beqz $[[R15]], $[[BB0]] 362 363 ; CHECK-EL: $[[BB1]]: 364 ; CHECK-EL: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]] 365 ; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24 366 ; CHECK-EL: sra $2, $[[R17]], 24 367 368 ; CHECK-EB-LABEL: AtomicCmpSwap8: 369 ; CHECK-EB: lw $[[R0:[0-9]+]], %got(y) 370 ; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4 371 ; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] 372 ; CHECK-EB: andi $[[R3:[0-9]+]], $[[R0]], 3 373 ; CHECK-EB: xori $[[R4:[0-9]+]], $[[R3]], 3 374 ; CHECK-EB: sll $[[R5:[0-9]+]], $[[R4]], 3 375 ; CHECK-EB: ori $[[R6:[0-9]+]], $zero, 255 376 ; CHECK-EB: sllv $[[R7:[0-9]+]], $[[R6]], $[[R5]] 377 ; CHECK-EB: nor $[[R8:[0-9]+]], $zero, $[[R7]] 378 ; CHECK-EB: andi $[[R9:[0-9]+]], $4, 255 379 ; CHECK-EB: sllv $[[R10:[0-9]+]], $[[R9]], $[[R5]] 380 ; CHECK-EB: andi $[[R11:[0-9]+]], $5, 255 381 ; CHECK-EB: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] 382 383 ; CHECK-EB: $[[BB0:[A-Z_0-9]+]]: 384 ; CHECK-EB: ll $[[R13:[0-9]+]], 0($[[R2]]) 385 ; CHECK-EB: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] 386 ; CHECK-EB: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] 387 388 ; CHECK-EB: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] 389 ; CHECK-EB: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] 390 ; CHECK-EB: sc $[[R16]], 0($[[R2]]) 391 ; CHECK-EB: beqz $[[R16]], $[[BB0]] 392 393 ; CHECK-EB: $[[BB1]]: 394 ; CHECK-EB: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] 395 ; CHECK-EB: sll $[[R18:[0-9]+]], $[[R17]], 24 396 ; CHECK-EB: sra $2, $[[R18]], 24 397 } 398 399 @countsint = common global i32 0, align 4 400 401 define i32 @CheckSync(i32 %v) nounwind noinline { 402 entry: 403 %0 = atomicrmw add i32* @countsint, i32 %v seq_cst 404 ret i32 %0 405 406 ; CHECK-EL-LABEL: CheckSync: 407 ; CHECK-EL: sync 0 408 ; CHECK-EL: ll 409 ; CHECK-EL: sc 410 ; CHECK-EL: beq 411 ; CHECK-EL: sync 0 412 413 ; CHECK-EB-LABEL: CheckSync: 414 ; CHECK-EB: sync 0 415 ; CHECK-EB: ll 416 ; CHECK-EB: sc 417 ; CHECK-EB: beq 418 ; CHECK-EB: sync 0 419 } 420 421 ; make sure that this assertion in 422 ; TwoAddressInstructionPass::TryInstructionTransform does not fail: 423 ; 424 ; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) && 425 ; 426 ; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an 427 ; operand of an atomic instruction with register $zero. 428 @a = external global i32 429 430 define i32 @zeroreg() nounwind { 431 entry: 432 %0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst 433 %1 = icmp eq i32 %0, 1 434 %conv = zext i1 %1 to i32 435 ret i32 %conv 436 } 437
