| /external/clang/test/SemaTemplate/ |
| instantiate-subscript.cpp | 4 struct Sub0 {
24 template struct Subscript0<Sub0, int, int&>;
26 template struct Subscript0<Sub1, Sub0, long&>; // expected-note{{instantiation}}
|
| /external/chromium_org/third_party/cld/encodings/compact_lang_det/ |
| tote.cc | 55 int sub0 = ikey & 15; local
56 if (key_[sub0] == ikey) {
57 value_[sub0] += idelta;
60 int sub1 = sub0 ^ 8;
73 if (key_[sub0] == 0) {
74 alloc = sub0;
81 alloc = sub0;
171 int sub0 = ikey & 15; local
172 if (key_[sub0] == ikey) {
173 value_[sub0] += ibytes
227 int sub0 = ikey & 15; local
[all...] |
| /external/lzma/CPP/7zip/Common/ |
| FilterCoder.h | 10 #define MY_QUERYINTERFACE_ENTRY_AG(i, sub0, sub) if (iid == IID_ ## i) \
11 { if (!sub) RINOK(sub0->QueryInterface(IID_ ## i, (void **)&sub)) \
|
| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.td | 46 def SGPR_64 : RegisterTuples<[sub0, sub1],
51 def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
58 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
69 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
93 def VGPR_64 : RegisterTuples<[sub0, sub1],
98 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
104 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
111 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
122 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
| AMDGPUInstructions.td | 265 (vecType (build_vector elemType:$sub0, elemType:$sub1)),
267 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1)
273 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3)
277 (vecType (build_vector elemType:$sub0, elemType:$sub1,
283 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1),
290 (vecType (build_vector elemType:$sub0, elemType:$sub1,
302 (vecType (IMPLICIT_DEF)), $sub0, sub0), $sub1, sub1)
[all...] |
| SIInstrInfo.cpp | 46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
53 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
58 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
62 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
66 AMDGPU::sub0, AMDGPU::sub1, 0
|
| R600RegisterInfo.td | 22 let SubRegIndices = [sub0, sub1, sub2, sub3];
29 let SubRegIndices = [sub0, sub1];
216 [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
| R600OptimizeVectorRegisters.cpp | 15 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
17 /// vreg7<def> = REG_SEQ vreg1, sub0, vreg3, sub1, undef, sub2, vreg4, sub3
18 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub1, sub2, sub3
21 /// vreg5<def> = REG_SEQ vreg1, sub0, vreg2, sub1, vreg3, sub2, undef, sub3
24 /// (swizzable Inst) vreg7, SwizzleMask : sub0, sub2, sub1, sub3
|
| AMDGPURegisterInfo.cpp | 52 case 0: return AMDGPU::sub0;
|
| R600RegisterInfo.cpp | 92 case 0: return AMDGPU::sub0;
|
| SIInstructions.td | [all...] |
| SILowerControlFlow.cpp | 383 .addReg(TRI->getSubReg(Vec, AMDGPU::sub0) + Off)
401 .addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define)
|
| SIISelLowering.cpp | 230 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
297 .addImm(AMDGPU::sub0)
929 case AMDGPU::sub0: return 0;
[all...] |
| R600Instructions.td | 474 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
480 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), R600_Reg32:$reg, sub0),
[all...] |
| R600MachineScheduler.cpp | 291 case AMDGPU::sub0:
|
| /external/llvm/test/CodeGen/SystemZ/ |
| fp-sub-01.ll | 106 %sub0 = fsub float %ret, %val0
107 %sub1 = fsub float %sub0, %val1
|
| fp-sub-02.ll | 106 %sub0 = fsub double %ret, %val0
107 %sub1 = fsub double %sub0, %val1
|
| int-sub-04.ll | 128 %sub0 = sub i64 %ret, %val0
129 %sub1 = sub i64 %sub0, %val1
|
| int-sub-01.ll | 163 %sub0 = sub i32 %ret, %val0
164 %sub1 = sub i32 %sub0, %val1
|
| int-sub-02.ll | 168 %sub0 = sub i64 %ret, %ext0
169 %sub1 = sub i64 %sub0, %ext1
|
| int-sub-03.ll | 168 %sub0 = sub i64 %ret, %ext0
169 %sub1 = sub i64 %sub0, %ext1
|
| int-sub-05.ll | 145 %sub0 = sub i128 %ret, %val0
146 %sub1 = sub i128 %sub0, %val1
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 33 def sub0 : SubRegIndex;
59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 33 def sub0 : SubRegIndex;
59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
|
| /external/icu4c/common/ |
| locdispnames.cpp | 470 static const UChar sub0[4] = { 0x007b, 0x0030, 0x007d , 0x0000 } ; /* {0} */ local
530 UChar *p0=u_strstr(pattern, sub0);
|
