| /external/llvm/test/Transforms/InstCombine/ |
| addnegneg.ll | 8 %sub4 = add i32 %c.neg, %b.neg ; <i32> [#uses=1]
9 %sub6 = add i32 %sub4, %d ; <i32> [#uses=1]
|
| /external/clang/test/Sema/ |
| typecheck-binop.c | 17 int sub4(void *P, void *Q) { function
|
| /cts/suite/audio_quality/test/ |
| StringUtilTest.cpp | 43 android::String8 sub4 = StringUtil::substr(str, 100, 5); local
44 ASSERT_TRUE(sub4.length() == 0);
|
| /external/llvm/test/Transforms/Reassociate/ |
| pr12245.ll | 25 %sub4 = sub nsw i32 %dec3, %5
26 store i32 %sub4, i32* @d, align 4
|
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| phi3.ll | 22 %sub4 = fsub double %sub1, undef
23 %div.i16 = fdiv double %sub4, undef
|
| /external/llvm/test/CodeGen/Mips/ |
| stldst.ll | 26 %sub4 = add nsw i32 %5, -5
33 %call7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind
|
| /external/llvm/test/CodeGen/X86/ |
| 2011-03-02-DAGCombiner.ll | 36 %sub4 = fsub x86_fp80 %conv3, %tmp1
37 %conv5 = fptoui x86_fp80 %sub4 to i32
|
| atomic_add.ll | 128 define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp {
130 ; CHECK-LABEL: sub4:
|
| /external/sfntly/cpp/src/test/ |
| bitmap_table_test.cc | 168 IndexSubTableFormat4Ptr sub4 = local
170 EXPECT_FALSE(sub4 == NULL);
190 info.Attach(sub4->GlyphInfo(i));
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstructions.td | 279 elemType:$sub4, elemType:$sub5,
285 $sub4, sub4), $sub5, sub5),
292 elemType:$sub4, elemType:$sub5,
304 $sub4, sub4), $sub5, sub5),
|
| SIRegisterInfo.td | 58 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
69 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
111 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
122 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
| AMDGPURegisterInfo.cpp | 56 case 4: return AMDGPU::sub4;
|
| SIInstrInfo.cpp | 47 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
54 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
|
| R600RegisterInfo.td | 216 [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
| /external/llvm/test/CodeGen/SystemZ/ |
| fp-sub-01.ll | 110 %sub4 = fsub float %sub3, %val4
111 %sub5 = fsub float %sub4, %val5
|
| fp-sub-02.ll | 110 %sub4 = fsub double %sub3, %val4
111 %sub5 = fsub double %sub4, %val5
|
| int-sub-04.ll | 132 %sub4 = sub i64 %sub3, %val4
133 %sub5 = sub i64 %sub4, %val5
|
| int-sub-01.ll | 167 %sub4 = sub i32 %sub3, %val4
168 %sub5 = sub i32 %sub4, %val5
|
| int-sub-02.ll | 172 %sub4 = sub i64 %sub3, %ext4
173 %sub5 = sub i64 %sub4, %ext5
|
| int-sub-03.ll | 172 %sub4 = sub i64 %sub3, %ext4
173 %sub5 = sub i64 %sub4, %ext5
|
| int-sub-05.ll | 149 %sub4 = sub i128 %sub3, %val4
150 store i128 %sub4, i128 *%retptr
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 37 def sub4 : SubRegIndex;
59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 37 def sub4 : SubRegIndex;
59 let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
181 my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7');
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| global_alias.ll | 585 %sub4 = sub nsw i32 %sub3, 1
588 %arrayidx6 = getelementptr inbounds [100 x i32]* %arrayidx5, i32 0, i32 %sub4
645 %sub4 = sub nsw i32 100, %5
646 %sub5 = sub nsw i32 %sub4, 1
[all...] |
| /external/llvm/test/Analysis/DependenceAnalysis/ |
| Coupled.ll | 219 %sub4 = sub nsw i64 %mul2, %conv3
220 %add = add nsw i64 %sub4, 1
|
