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  /external/llvm/test/CodeGen/ARM/
vfloatintrinsics.ll 131 %v4f32 = type <4 x float>
133 define %v4f32 @test_v4f32.sqrt(%v4f32 %a) {
135 %1 = call %v4f32 @llvm.sqrt.v4f32(%v4f32 %a)
136 ret %v4f32 %1
139 define %v4f32 @test_v4f32.powi(%v4f32 %a, i32 %b) {
141 %1 = call %v4f32 @llvm.powi.v4f32(%v4f32 %a, i32 %b
    [all...]
fabs-neon.ll 6 %foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
9 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
spill-q.ll 10 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
21 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#uses=1]
23 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
25 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
36 %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwin
    [all...]
vcvt-v8.ll 6 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
22 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
38 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
54 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
70 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
86 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1)
102 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1)
118 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1)
130 declare <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
132 declare <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float>) nounwind readnon
    [all...]
2011-11-29-128bitArithmetics.ll 20 %1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %0)
25 declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
52 %1 = call <4 x float> @llvm.cos.v4f32(<4 x float> %0)
57 declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
83 %1 = call <4 x float> @llvm.exp.v4f32(<4 x float> %0)
88 declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
114 %1 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %0)
119 declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
145 %1 = call <4 x float> @llvm.log10.v4f32(<4 x float> %0)
150 declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonl
    [all...]
2013-02-27-expand-vfma.ll 13 %tmp = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> %c, <4 x float> %a) #2
17 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
neon-fma.ll 17 %call = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone
22 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone
2009-11-01-NeonMoves.ll 23 %8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses=3]
25 %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1]
38 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
40 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
vminmaxnm.ll 8 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
26 %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
39 declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
41 declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
vrec.ll 31 %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
39 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
55 %tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
60 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
90 %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
98 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
114 %tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
119 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
2012-01-23-PostRA-LICM.ll 32 %tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
33 %tmp17 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp16, <4 x float> %tmp11) nounwind
35 %tmp19 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp18, <4 x float> %tmp11) nounwind
38 %tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwind
51 %tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounwind
73 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
97 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
99 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
101 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
2012-01-24-RegSequenceLiveRange.ll 55 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind
56 tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind
66 tail call void @llvm.arm.neon.vst2.v4f32(i8* %p, <4 x float> undef, <4 x float> undef, i32 4)
71 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
72 declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
2010-05-21-BuildVector.ll 39 tail call void @llvm.arm.neon.vst1.v4f32(i8* %20, <4 x float> %19, i32 1)
43 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
vcvt.ll 108 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
116 %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
124 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
132 %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
136 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
137 declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
138 declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
139 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
  /external/llvm/test/Analysis/CostModel/X86/
intrinsic-cost.ll 15 %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
25 ; CORE2: Cost Model: Found an estimated cost of 400 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
28 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.load)
32 declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone
43 %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
53 ; CORE2: Cost Model: Found an estimated cost of 400 for instruction: %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
56 ; COREI7: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
60 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone
  /external/llvm/test/CodeGen/Thumb2/
thumb2-spill-q.ll 10 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
21 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %vecptr, i32 1) nounwind
23 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
25 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwind
36 %ld8 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) nounwin
    [all...]
machine-licm.ll 62 %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1, i32 1)
63 %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, <4 x float> %tmp2)
65 call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1)
76 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
78 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
80 declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone
  /external/llvm/lib/Target/PowerPC/
PPCInstrAltivec.td 213 [(set v4f32:$vD, (IntID v4f32:$vB))]>;
319 [(set v4f32:$vD,
320 (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
325 [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
326 (fneg v4f32:$vB))))]>;
    [all...]
  /external/clang/test/CodeGen/
arm-vector-align.c 17 // CHECK: call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %{{.*}}, i32 16)
19 // CHECK: call void @llvm.arm.neon.vst1.v4f32(i8* %{{.*}}, <4 x float> %{{.*}}, i32 16)
arm-neon-fma.c 18 // CHECK: call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %rhs, <4 x float> %accum)
  /external/llvm/test/CodeGen/X86/
vec_fabs.ll 17 %t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
20 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
vec_floor.ll 17 %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
20 declare <4 x float> @llvm.floor.v4f32(<4 x float> %p)
53 %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
56 declare <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
89 %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
92 declare <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
125 %t = call <4 x float> @llvm.rint.v4f32(<4 x float> %p)
128 declare <4 x float> @llvm.rint.v4f32(<4 x float> %p)
161 %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
164 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p
    [all...]
  /external/llvm/test/CodeGen/AArch64/
neon-frsqrt-frecp.ll 6 declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>)
19 %val = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %lhs, <4 x float> %rhs)
31 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>)
44 %val = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %lhs, <4 x float> %rhs)
  /external/llvm/test/CodeGen/PowerPC/
vec_rounding.ll 98 declare <4 x float> @llvm.floor.v4f32(<4 x float> %p)
101 %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
117 declare <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
120 %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
136 declare <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
139 %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
155 declare <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
158 %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
  /external/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
382 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
383 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
384 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
385 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
386 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
417 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }
    [all...]

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