1 /* 2 * Copyright (C) 2013 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #include "sea_ir/ir/instruction_tools.h" 18 19 namespace sea_ir { 20 21 bool InstructionTools::IsDefinition(const art::Instruction* const instruction) { 22 if (0 != (InstructionTools::instruction_attributes_[instruction->Opcode()] & (1 << kDA))) { 23 return true; 24 } 25 return false; 26 } 27 28 const int InstructionTools::instruction_attributes_[] = { 29 // 00 NOP 30 DF_NOP, 31 32 // 01 MOVE vA, vB 33 DF_DA | DF_UB | DF_IS_MOVE, 34 35 // 02 MOVE_FROM16 vAA, vBBBB 36 DF_DA | DF_UB | DF_IS_MOVE, 37 38 // 03 MOVE_16 vAAAA, vBBBB 39 DF_DA | DF_UB | DF_IS_MOVE, 40 41 // 04 MOVE_WIDE vA, vB 42 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE, 43 44 // 05 MOVE_WIDE_FROM16 vAA, vBBBB 45 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE, 46 47 // 06 MOVE_WIDE_16 vAAAA, vBBBB 48 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_IS_MOVE, 49 50 // 07 MOVE_OBJECT vA, vB 51 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B, 52 53 // 08 MOVE_OBJECT_FROM16 vAA, vBBBB 54 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B, 55 56 // 09 MOVE_OBJECT_16 vAAAA, vBBBB 57 DF_DA | DF_UB | DF_NULL_TRANSFER_0 | DF_IS_MOVE | DF_REF_A | DF_REF_B, 58 59 // 0A MOVE_RESULT vAA 60 DF_DA, 61 62 // 0B MOVE_RESULT_WIDE vAA 63 DF_DA | DF_A_WIDE, 64 65 // 0C MOVE_RESULT_OBJECT vAA 66 DF_DA | DF_REF_A, 67 68 // 0D MOVE_EXCEPTION vAA 69 DF_DA | DF_REF_A | DF_NON_NULL_DST, 70 71 // 0E RETURN_VOID 72 DF_NOP, 73 74 // 0F RETURN vAA 75 DF_UA, 76 77 // 10 RETURN_WIDE vAA 78 DF_UA | DF_A_WIDE, 79 80 // 11 RETURN_OBJECT vAA 81 DF_UA | DF_REF_A, 82 83 // 12 CONST_4 vA, #+B 84 DF_DA | DF_SETS_CONST, 85 86 // 13 CONST_16 vAA, #+BBBB 87 DF_DA | DF_SETS_CONST, 88 89 // 14 CONST vAA, #+BBBBBBBB 90 DF_DA | DF_SETS_CONST, 91 92 // 15 CONST_HIGH16 VAA, #+BBBB0000 93 DF_DA | DF_SETS_CONST, 94 95 // 16 CONST_WIDE_16 vAA, #+BBBB 96 DF_DA | DF_A_WIDE | DF_SETS_CONST, 97 98 // 17 CONST_WIDE_32 vAA, #+BBBBBBBB 99 DF_DA | DF_A_WIDE | DF_SETS_CONST, 100 101 // 18 CONST_WIDE vAA, #+BBBBBBBBBBBBBBBB 102 DF_DA | DF_A_WIDE | DF_SETS_CONST, 103 104 // 19 CONST_WIDE_HIGH16 vAA, #+BBBB000000000000 105 DF_DA | DF_A_WIDE | DF_SETS_CONST, 106 107 // 1A CONST_STRING vAA, string@BBBB 108 DF_DA | DF_REF_A | DF_NON_NULL_DST, 109 110 // 1B CONST_STRING_JUMBO vAA, string@BBBBBBBB 111 DF_DA | DF_REF_A | DF_NON_NULL_DST, 112 113 // 1C CONST_CLASS vAA, type@BBBB 114 DF_DA | DF_REF_A | DF_NON_NULL_DST, 115 116 // 1D MONITOR_ENTER vAA 117 DF_UA | DF_NULL_CHK_0 | DF_REF_A, 118 119 // 1E MONITOR_EXIT vAA 120 DF_UA | DF_NULL_CHK_0 | DF_REF_A, 121 122 // 1F CHK_CAST vAA, type@BBBB 123 DF_UA | DF_REF_A | DF_UMS, 124 125 // 20 INSTANCE_OF vA, vB, type@CCCC 126 DF_DA | DF_UB | DF_CORE_A | DF_REF_B | DF_UMS, 127 128 // 21 ARRAY_LENGTH vA, vB 129 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_CORE_A | DF_REF_B, 130 131 // 22 NEW_INSTANCE vAA, type@BBBB 132 DF_DA | DF_NON_NULL_DST | DF_REF_A | DF_UMS, 133 134 // 23 NEW_ARRAY vA, vB, type@CCCC 135 DF_DA | DF_UB | DF_NON_NULL_DST | DF_REF_A | DF_CORE_B | DF_UMS, 136 137 // 24 FILLED_NEW_ARRAY {vD, vE, vF, vG, vA} 138 DF_FORMAT_35C | DF_NON_NULL_RET | DF_UMS, 139 140 // 25 FILLED_NEW_ARRAY_RANGE {vCCCC .. vNNNN}, type@BBBB 141 DF_FORMAT_3RC | DF_NON_NULL_RET | DF_UMS, 142 143 // 26 FILL_ARRAY_DATA vAA, +BBBBBBBB 144 DF_UA | DF_REF_A | DF_UMS, 145 146 // 27 THROW vAA 147 DF_UA | DF_REF_A | DF_UMS, 148 149 // 28 GOTO 150 DF_NOP, 151 152 // 29 GOTO_16 153 DF_NOP, 154 155 // 2A GOTO_32 156 DF_NOP, 157 158 // 2B PACKED_SWITCH vAA, +BBBBBBBB 159 DF_UA, 160 161 // 2C SPARSE_SWITCH vAA, +BBBBBBBB 162 DF_UA, 163 164 // 2D CMPL_FLOAT vAA, vBB, vCC 165 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A, 166 167 // 2E CMPG_FLOAT vAA, vBB, vCC 168 DF_DA | DF_UB | DF_UC | DF_FP_B | DF_FP_C | DF_CORE_A, 169 170 // 2F CMPL_DOUBLE vAA, vBB, vCC 171 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A, 172 173 // 30 CMPG_DOUBLE vAA, vBB, vCC 174 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_B | DF_FP_C | DF_CORE_A, 175 176 // 31 CMP_LONG vAA, vBB, vCC 177 DF_DA | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 178 179 // 32 IF_EQ vA, vB, +CCCC 180 DF_UA | DF_UB, 181 182 // 33 IF_NE vA, vB, +CCCC 183 DF_UA | DF_UB, 184 185 // 34 IF_LT vA, vB, +CCCC 186 DF_UA | DF_UB, 187 188 // 35 IF_GE vA, vB, +CCCC 189 DF_UA | DF_UB, 190 191 // 36 IF_GT vA, vB, +CCCC 192 DF_UA | DF_UB, 193 194 // 37 IF_LE vA, vB, +CCCC 195 DF_UA | DF_UB, 196 197 // 38 IF_EQZ vAA, +BBBB 198 DF_UA, 199 200 // 39 IF_NEZ vAA, +BBBB 201 DF_UA, 202 203 // 3A IF_LTZ vAA, +BBBB 204 DF_UA, 205 206 // 3B IF_GEZ vAA, +BBBB 207 DF_UA, 208 209 // 3C IF_GTZ vAA, +BBBB 210 DF_UA, 211 212 // 3D IF_LEZ vAA, +BBBB 213 DF_UA, 214 215 // 3E UNUSED_3E 216 DF_NOP, 217 218 // 3F UNUSED_3F 219 DF_NOP, 220 221 // 40 UNUSED_40 222 DF_NOP, 223 224 // 41 UNUSED_41 225 DF_NOP, 226 227 // 42 UNUSED_42 228 DF_NOP, 229 230 // 43 UNUSED_43 231 DF_NOP, 232 233 // 44 AGET vAA, vBB, vCC 234 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C, 235 236 // 45 AGET_WIDE vAA, vBB, vCC 237 DF_DA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C, 238 239 // 46 AGET_OBJECT vAA, vBB, vCC 240 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_A | DF_REF_B | DF_CORE_C, 241 242 // 47 AGET_BOOLEAN vAA, vBB, vCC 243 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C, 244 245 // 48 AGET_BYTE vAA, vBB, vCC 246 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C, 247 248 // 49 AGET_CHAR vAA, vBB, vCC 249 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C, 250 251 // 4A AGET_SHORT vAA, vBB, vCC 252 DF_DA | DF_UB | DF_UC | DF_NULL_CHK_0 | DF_RANGE_CHK_1 | DF_REF_B | DF_CORE_C, 253 254 // 4B APUT vAA, vBB, vCC 255 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C, 256 257 // 4C APUT_WIDE vAA, vBB, vCC 258 DF_UA | DF_A_WIDE | DF_UB | DF_UC | DF_NULL_CHK_2 | DF_RANGE_CHK_3 | DF_REF_B | DF_CORE_C, 259 260 // 4D APUT_OBJECT vAA, vBB, vCC 261 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_A | DF_REF_B | DF_CORE_C, 262 263 // 4E APUT_BOOLEAN vAA, vBB, vCC 264 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C, 265 266 // 4F APUT_BYTE vAA, vBB, vCC 267 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C, 268 269 // 50 APUT_CHAR vAA, vBB, vCC 270 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C, 271 272 // 51 APUT_SHORT vAA, vBB, vCC 273 DF_UA | DF_UB | DF_UC | DF_NULL_CHK_1 | DF_RANGE_CHK_2 | DF_REF_B | DF_CORE_C, 274 275 // 52 IGET vA, vB, field@CCCC 276 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 277 278 // 53 IGET_WIDE vA, vB, field@CCCC 279 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 280 281 // 54 IGET_OBJECT vA, vB, field@CCCC 282 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B, 283 284 // 55 IGET_BOOLEAN vA, vB, field@CCCC 285 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 286 287 // 56 IGET_BYTE vA, vB, field@CCCC 288 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 289 290 // 57 IGET_CHAR vA, vB, field@CCCC 291 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 292 293 // 58 IGET_SHORT vA, vB, field@CCCC 294 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 295 296 // 59 IPUT vA, vB, field@CCCC 297 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B, 298 299 // 5A IPUT_WIDE vA, vB, field@CCCC 300 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B, 301 302 // 5B IPUT_OBJECT vA, vB, field@CCCC 303 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B, 304 305 // 5C IPUT_BOOLEAN vA, vB, field@CCCC 306 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B, 307 308 // 5D IPUT_BYTE vA, vB, field@CCCC 309 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B, 310 311 // 5E IPUT_CHAR vA, vB, field@CCCC 312 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B, 313 314 // 5F IPUT_SHORT vA, vB, field@CCCC 315 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B, 316 317 // 60 SGET vAA, field@BBBB 318 DF_DA | DF_UMS, 319 320 // 61 SGET_WIDE vAA, field@BBBB 321 DF_DA | DF_A_WIDE | DF_UMS, 322 323 // 62 SGET_OBJECT vAA, field@BBBB 324 DF_DA | DF_REF_A | DF_UMS, 325 326 // 63 SGET_BOOLEAN vAA, field@BBBB 327 DF_DA | DF_UMS, 328 329 // 64 SGET_BYTE vAA, field@BBBB 330 DF_DA | DF_UMS, 331 332 // 65 SGET_CHAR vAA, field@BBBB 333 DF_DA | DF_UMS, 334 335 // 66 SGET_SHORT vAA, field@BBBB 336 DF_DA | DF_UMS, 337 338 // 67 SPUT vAA, field@BBBB 339 DF_UA | DF_UMS, 340 341 // 68 SPUT_WIDE vAA, field@BBBB 342 DF_UA | DF_A_WIDE | DF_UMS, 343 344 // 69 SPUT_OBJECT vAA, field@BBBB 345 DF_UA | DF_REF_A | DF_UMS, 346 347 // 6A SPUT_BOOLEAN vAA, field@BBBB 348 DF_UA | DF_UMS, 349 350 // 6B SPUT_BYTE vAA, field@BBBB 351 DF_UA | DF_UMS, 352 353 // 6C SPUT_CHAR vAA, field@BBBB 354 DF_UA | DF_UMS, 355 356 // 6D SPUT_SHORT vAA, field@BBBB 357 DF_UA | DF_UMS, 358 359 // 6E INVOKE_VIRTUAL {vD, vE, vF, vG, vA} 360 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS, 361 362 // 6F INVOKE_SUPER {vD, vE, vF, vG, vA} 363 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS, 364 365 // 70 INVOKE_DIRECT {vD, vE, vF, vG, vA} 366 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS, 367 368 // 71 INVOKE_STATIC {vD, vE, vF, vG, vA} 369 DF_FORMAT_35C | DF_UMS, 370 371 // 72 INVOKE_INTERFACE {vD, vE, vF, vG, vA} 372 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS, 373 374 // 73 UNUSED_73 375 DF_NOP, 376 377 // 74 INVOKE_VIRTUAL_RANGE {vCCCC .. vNNNN} 378 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS, 379 380 // 75 INVOKE_SUPER_RANGE {vCCCC .. vNNNN} 381 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS, 382 383 // 76 INVOKE_DIRECT_RANGE {vCCCC .. vNNNN} 384 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS, 385 386 // 77 INVOKE_STATIC_RANGE {vCCCC .. vNNNN} 387 DF_FORMAT_3RC | DF_UMS, 388 389 // 78 INVOKE_INTERFACE_RANGE {vCCCC .. vNNNN} 390 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS, 391 392 // 79 UNUSED_79 393 DF_NOP, 394 395 // 7A UNUSED_7A 396 DF_NOP, 397 398 // 7B NEG_INT vA, vB 399 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 400 401 // 7C NOT_INT vA, vB 402 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 403 404 // 7D NEG_LONG vA, vB 405 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 406 407 // 7E NOT_LONG vA, vB 408 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 409 410 // 7F NEG_FLOAT vA, vB 411 DF_DA | DF_UB | DF_FP_A | DF_FP_B, 412 413 // 80 NEG_DOUBLE vA, vB 414 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B, 415 416 // 81 INT_TO_LONG vA, vB 417 DF_DA | DF_A_WIDE | DF_UB | DF_CORE_A | DF_CORE_B, 418 419 // 82 INT_TO_FLOAT vA, vB 420 DF_DA | DF_UB | DF_FP_A | DF_CORE_B, 421 422 // 83 INT_TO_DOUBLE vA, vB 423 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_CORE_B, 424 425 // 84 LONG_TO_INT vA, vB 426 DF_DA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 427 428 // 85 LONG_TO_FLOAT vA, vB 429 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B, 430 431 // 86 LONG_TO_DOUBLE vA, vB 432 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_A | DF_CORE_B, 433 434 // 87 FLOAT_TO_INT vA, vB 435 DF_DA | DF_UB | DF_FP_B | DF_CORE_A, 436 437 // 88 FLOAT_TO_LONG vA, vB 438 DF_DA | DF_A_WIDE | DF_UB | DF_FP_B | DF_CORE_A, 439 440 // 89 FLOAT_TO_DOUBLE vA, vB 441 DF_DA | DF_A_WIDE | DF_UB | DF_FP_A | DF_FP_B, 442 443 // 8A DOUBLE_TO_INT vA, vB 444 DF_DA | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A, 445 446 // 8B DOUBLE_TO_LONG vA, vB 447 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_FP_B | DF_CORE_A, 448 449 // 8C DOUBLE_TO_FLOAT vA, vB 450 DF_DA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B, 451 452 // 8D INT_TO_BYTE vA, vB 453 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 454 455 // 8E INT_TO_CHAR vA, vB 456 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 457 458 // 8F INT_TO_SHORT vA, vB 459 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 460 461 // 90 ADD_INT vAA, vBB, vCC 462 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 463 464 // 91 SUB_INT vAA, vBB, vCC 465 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 466 467 // 92 MUL_INT vAA, vBB, vCC 468 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 469 470 // 93 DIV_INT vAA, vBB, vCC 471 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 472 473 // 94 REM_INT vAA, vBB, vCC 474 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 475 476 // 95 AND_INT vAA, vBB, vCC 477 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 478 479 // 96 OR_INT vAA, vBB, vCC 480 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 481 482 // 97 XOR_INT vAA, vBB, vCC 483 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 484 485 // 98 SHL_INT vAA, vBB, vCC 486 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 487 488 // 99 SHR_INT vAA, vBB, vCC 489 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 490 491 // 9A USHR_INT vAA, vBB, vCC 492 DF_DA | DF_UB | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 493 494 // 9B ADD_LONG vAA, vBB, vCC 495 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 496 497 // 9C SUB_LONG vAA, vBB, vCC 498 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 499 500 // 9D MUL_LONG vAA, vBB, vCC 501 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 502 503 // 9E DIV_LONG vAA, vBB, vCC 504 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 505 506 // 9F REM_LONG vAA, vBB, vCC 507 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 508 509 // A0 AND_LONG vAA, vBB, vCC 510 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 511 512 // A1 OR_LONG vAA, vBB, vCC 513 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 514 515 // A2 XOR_LONG vAA, vBB, vCC 516 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_CORE_A | DF_CORE_B | DF_CORE_C, 517 518 // A3 SHL_LONG vAA, vBB, vCC 519 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 520 521 // A4 SHR_LONG vAA, vBB, vCC 522 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 523 524 // A5 USHR_LONG vAA, vBB, vCC 525 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_CORE_A | DF_CORE_B | DF_CORE_C, 526 527 // A6 ADD_FLOAT vAA, vBB, vCC 528 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C, 529 530 // A7 SUB_FLOAT vAA, vBB, vCC 531 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C, 532 533 // A8 MUL_FLOAT vAA, vBB, vCC 534 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C, 535 536 // A9 DIV_FLOAT vAA, vBB, vCC 537 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C, 538 539 // AA REM_FLOAT vAA, vBB, vCC 540 DF_DA | DF_UB | DF_UC | DF_FP_A | DF_FP_B | DF_FP_C, 541 542 // AB ADD_DOUBLE vAA, vBB, vCC 543 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C, 544 545 // AC SUB_DOUBLE vAA, vBB, vCC 546 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C, 547 548 // AD MUL_DOUBLE vAA, vBB, vCC 549 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C, 550 551 // AE DIV_DOUBLE vAA, vBB, vCC 552 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C, 553 554 // AF REM_DOUBLE vAA, vBB, vCC 555 DF_DA | DF_A_WIDE | DF_UB | DF_B_WIDE | DF_UC | DF_C_WIDE | DF_FP_A | DF_FP_B | DF_FP_C, 556 557 // B0 ADD_INT_2ADDR vA, vB 558 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 559 560 // B1 SUB_INT_2ADDR vA, vB 561 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 562 563 // B2 MUL_INT_2ADDR vA, vB 564 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 565 566 // B3 DIV_INT_2ADDR vA, vB 567 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 568 569 // B4 REM_INT_2ADDR vA, vB 570 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 571 572 // B5 AND_INT_2ADDR vA, vB 573 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 574 575 // B6 OR_INT_2ADDR vA, vB 576 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 577 578 // B7 XOR_INT_2ADDR vA, vB 579 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 580 581 // B8 SHL_INT_2ADDR vA, vB 582 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 583 584 // B9 SHR_INT_2ADDR vA, vB 585 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 586 587 // BA USHR_INT_2ADDR vA, vB 588 DF_DA | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 589 590 // BB ADD_LONG_2ADDR vA, vB 591 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 592 593 // BC SUB_LONG_2ADDR vA, vB 594 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 595 596 // BD MUL_LONG_2ADDR vA, vB 597 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 598 599 // BE DIV_LONG_2ADDR vA, vB 600 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 601 602 // BF REM_LONG_2ADDR vA, vB 603 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 604 605 // C0 AND_LONG_2ADDR vA, vB 606 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 607 608 // C1 OR_LONG_2ADDR vA, vB 609 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 610 611 // C2 XOR_LONG_2ADDR vA, vB 612 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_CORE_A | DF_CORE_B, 613 614 // C3 SHL_LONG_2ADDR vA, vB 615 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 616 617 // C4 SHR_LONG_2ADDR vA, vB 618 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 619 620 // C5 USHR_LONG_2ADDR vA, vB 621 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_CORE_A | DF_CORE_B, 622 623 // C6 ADD_FLOAT_2ADDR vA, vB 624 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B, 625 626 // C7 SUB_FLOAT_2ADDR vA, vB 627 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B, 628 629 // C8 MUL_FLOAT_2ADDR vA, vB 630 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B, 631 632 // C9 DIV_FLOAT_2ADDR vA, vB 633 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B, 634 635 // CA REM_FLOAT_2ADDR vA, vB 636 DF_DA | DF_UA | DF_UB | DF_FP_A | DF_FP_B, 637 638 // CB ADD_DOUBLE_2ADDR vA, vB 639 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B, 640 641 // CC SUB_DOUBLE_2ADDR vA, vB 642 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B, 643 644 // CD MUL_DOUBLE_2ADDR vA, vB 645 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B, 646 647 // CE DIV_DOUBLE_2ADDR vA, vB 648 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B, 649 650 // CF REM_DOUBLE_2ADDR vA, vB 651 DF_DA | DF_A_WIDE | DF_UA | DF_UB | DF_B_WIDE | DF_FP_A | DF_FP_B, 652 653 // D0 ADD_INT_LIT16 vA, vB, #+CCCC 654 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 655 656 // D1 RSUB_INT vA, vB, #+CCCC 657 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 658 659 // D2 MUL_INT_LIT16 vA, vB, #+CCCC 660 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 661 662 // D3 DIV_INT_LIT16 vA, vB, #+CCCC 663 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 664 665 // D4 REM_INT_LIT16 vA, vB, #+CCCC 666 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 667 668 // D5 AND_INT_LIT16 vA, vB, #+CCCC 669 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 670 671 // D6 OR_INT_LIT16 vA, vB, #+CCCC 672 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 673 674 // D7 XOR_INT_LIT16 vA, vB, #+CCCC 675 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 676 677 // D8 ADD_INT_LIT8 vAA, vBB, #+CC 678 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 679 680 // D9 RSUB_INT_LIT8 vAA, vBB, #+CC 681 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 682 683 // DA MUL_INT_LIT8 vAA, vBB, #+CC 684 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 685 686 // DB DIV_INT_LIT8 vAA, vBB, #+CC 687 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 688 689 // DC REM_INT_LIT8 vAA, vBB, #+CC 690 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 691 692 // DD AND_INT_LIT8 vAA, vBB, #+CC 693 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 694 695 // DE OR_INT_LIT8 vAA, vBB, #+CC 696 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 697 698 // DF XOR_INT_LIT8 vAA, vBB, #+CC 699 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 700 701 // E0 SHL_INT_LIT8 vAA, vBB, #+CC 702 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 703 704 // E1 SHR_INT_LIT8 vAA, vBB, #+CC 705 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 706 707 // E2 USHR_INT_LIT8 vAA, vBB, #+CC 708 DF_DA | DF_UB | DF_CORE_A | DF_CORE_B, 709 710 // E3 IGET_VOLATILE 711 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 712 713 // E4 IPUT_VOLATILE 714 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_B, 715 716 // E5 SGET_VOLATILE 717 DF_DA | DF_UMS, 718 719 // E6 SPUT_VOLATILE 720 DF_UA | DF_UMS, 721 722 // E7 IGET_OBJECT_VOLATILE 723 DF_DA | DF_UB | DF_NULL_CHK_0 | DF_REF_A | DF_REF_B, 724 725 // E8 IGET_WIDE_VOLATILE 726 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0 | DF_REF_B, 727 728 // E9 IPUT_WIDE_VOLATILE 729 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2 | DF_REF_B, 730 731 // EA SGET_WIDE_VOLATILE 732 DF_DA | DF_A_WIDE | DF_UMS, 733 734 // EB SPUT_WIDE_VOLATILE 735 DF_UA | DF_A_WIDE | DF_UMS, 736 737 // EC BREAKPOINT 738 DF_NOP, 739 740 // ED THROW_VERIFICATION_ERROR 741 DF_NOP | DF_UMS, 742 743 // EE EXECUTE_INLINE 744 DF_FORMAT_35C, 745 746 // EF EXECUTE_INLINE_RANGE 747 DF_FORMAT_3RC, 748 749 // F0 INVOKE_OBJECT_INIT_RANGE 750 DF_NOP | DF_NULL_CHK_0, 751 752 // F1 RETURN_VOID_BARRIER 753 DF_NOP, 754 755 // F2 IGET_QUICK 756 DF_DA | DF_UB | DF_NULL_CHK_0, 757 758 // F3 IGET_WIDE_QUICK 759 DF_DA | DF_A_WIDE | DF_UB | DF_NULL_CHK_0, 760 761 // F4 IGET_OBJECT_QUICK 762 DF_DA | DF_UB | DF_NULL_CHK_0, 763 764 // F5 IPUT_QUICK 765 DF_UA | DF_UB | DF_NULL_CHK_1, 766 767 // F6 IPUT_WIDE_QUICK 768 DF_UA | DF_A_WIDE | DF_UB | DF_NULL_CHK_2, 769 770 // F7 IPUT_OBJECT_QUICK 771 DF_UA | DF_UB | DF_NULL_CHK_1, 772 773 // F8 INVOKE_VIRTUAL_QUICK 774 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS, 775 776 // F9 INVOKE_VIRTUAL_QUICK_RANGE 777 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS, 778 779 // FA INVOKE_SUPER_QUICK 780 DF_FORMAT_35C | DF_NULL_CHK_OUT0 | DF_UMS, 781 782 // FB INVOKE_SUPER_QUICK_RANGE 783 DF_FORMAT_3RC | DF_NULL_CHK_OUT0 | DF_UMS, 784 785 // FC IPUT_OBJECT_VOLATILE 786 DF_UA | DF_UB | DF_NULL_CHK_1 | DF_REF_A | DF_REF_B, 787 788 // FD SGET_OBJECT_VOLATILE 789 DF_DA | DF_REF_A | DF_UMS, 790 791 // FE SPUT_OBJECT_VOLATILE 792 DF_UA | DF_REF_A | DF_UMS, 793 794 // FF UNUSED_FF 795 DF_NOP 796 }; 797 } // namespace sea_ir 798
