1 // Copyright (c) 2011 The Chromium Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 // For atomic operations on reference counts, see atomic_refcount.h. 6 // For atomic operations on sequence numbers, see atomic_sequence_num.h. 7 8 // The routines exported by this module are subtle. If you use them, even if 9 // you get the code right, it will depend on careful reasoning about atomicity 10 // and memory ordering; it will be less readable, and harder to maintain. If 11 // you plan to use these routines, you should have a good reason, such as solid 12 // evidence that performance would otherwise suffer, or there being no 13 // alternative. You should assume only properties explicitly guaranteed by the 14 // specifications in this file. You are almost certainly _not_ writing code 15 // just for the x86; if you assume x86 semantics, x86 hardware bugs and 16 // implementations on other archtectures will cause your code to break. If you 17 // do not know what you are doing, avoid these routines, and use a Mutex. 18 // 19 // It is incorrect to make direct assignments to/from an atomic variable. 20 // You should use one of the Load or Store routines. The NoBarrier 21 // versions are provided when no barriers are needed: 22 // NoBarrier_Store() 23 // NoBarrier_Load() 24 // Although there are currently no compiler enforcement, you are encouraged 25 // to use these. 26 // 27 28 #ifndef BASE_ATOMICOPS_H_ 29 #define BASE_ATOMICOPS_H_ 30 #pragma once 31 32 #include "base/basictypes.h" 33 #include "build/build_config.h" 34 35 namespace base { 36 namespace subtle { 37 38 // Bug 1308991. We need this for /Wp64, to mark it safe for AtomicWord casting. 39 #ifndef OS_WIN 40 #define __w64 41 #endif 42 typedef __w64 int32 Atomic32; 43 #ifdef ARCH_CPU_64_BITS 44 // We need to be able to go between Atomic64 and AtomicWord implicitly. This 45 // means Atomic64 and AtomicWord should be the same type on 64-bit. 46 #if defined(OS_NACL) 47 // NaCl's intptr_t is not actually 64-bits on 64-bit! 48 // http://code.google.com/p/nativeclient/issues/detail?id=1162 49 typedef int64_t Atomic64; 50 #else 51 typedef intptr_t Atomic64; 52 #endif 53 #endif 54 55 // Use AtomicWord for a machine-sized pointer. It will use the Atomic32 or 56 // Atomic64 routines below, depending on your architecture. 57 typedef intptr_t AtomicWord; 58 59 // Atomically execute: 60 // result = *ptr; 61 // if (*ptr == old_value) 62 // *ptr = new_value; 63 // return result; 64 // 65 // I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value". 66 // Always return the old value of "*ptr" 67 // 68 // This routine implies no memory barriers. 69 Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr, 70 Atomic32 old_value, 71 Atomic32 new_value); 72 73 // Atomically store new_value into *ptr, returning the previous value held in 74 // *ptr. This routine implies no memory barriers. 75 Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value); 76 77 // Atomically increment *ptr by "increment". Returns the new value of 78 // *ptr with the increment applied. This routine implies no memory barriers. 79 Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment); 80 81 Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr, 82 Atomic32 increment); 83 84 // These following lower-level operations are typically useful only to people 85 // implementing higher-level synchronization operations like spinlocks, 86 // mutexes, and condition-variables. They combine CompareAndSwap(), a load, or 87 // a store with appropriate memory-ordering instructions. "Acquire" operations 88 // ensure that no later memory access can be reordered ahead of the operation. 89 // "Release" operations ensure that no previous memory access can be reordered 90 // after the operation. "Barrier" operations have both "Acquire" and "Release" 91 // semantics. A MemoryBarrier() has "Barrier" semantics, but does no memory 92 // access. 93 Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr, 94 Atomic32 old_value, 95 Atomic32 new_value); 96 Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr, 97 Atomic32 old_value, 98 Atomic32 new_value); 99 100 void MemoryBarrier(); 101 void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value); 102 void Acquire_Store(volatile Atomic32* ptr, Atomic32 value); 103 void Release_Store(volatile Atomic32* ptr, Atomic32 value); 104 105 Atomic32 NoBarrier_Load(volatile const Atomic32* ptr); 106 Atomic32 Acquire_Load(volatile const Atomic32* ptr); 107 Atomic32 Release_Load(volatile const Atomic32* ptr); 108 109 // 64-bit atomic operations (only available on 64-bit processors). 110 #ifdef ARCH_CPU_64_BITS 111 Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr, 112 Atomic64 old_value, 113 Atomic64 new_value); 114 Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value); 115 Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); 116 Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment); 117 118 Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr, 119 Atomic64 old_value, 120 Atomic64 new_value); 121 Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr, 122 Atomic64 old_value, 123 Atomic64 new_value); 124 void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value); 125 void Acquire_Store(volatile Atomic64* ptr, Atomic64 value); 126 void Release_Store(volatile Atomic64* ptr, Atomic64 value); 127 Atomic64 NoBarrier_Load(volatile const Atomic64* ptr); 128 Atomic64 Acquire_Load(volatile const Atomic64* ptr); 129 Atomic64 Release_Load(volatile const Atomic64* ptr); 130 #endif // ARCH_CPU_64_BITS 131 132 } // namespace base::subtle 133 } // namespace base 134 135 // Include our platform specific implementation. 136 #if defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY) 137 #include "base/atomicops_internals_x86_msvc.h" 138 #elif defined(OS_MACOSX) && defined(ARCH_CPU_X86_FAMILY) 139 #include "base/atomicops_internals_x86_macosx.h" 140 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY) 141 #include "base/atomicops_internals_x86_gcc.h" 142 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY) 143 #include "base/atomicops_internals_arm_gcc.h" 144 #elif defined(COMPILER_GCC) && defined(ARCH_CPU_MIPS_FAMILY) 145 #include "base/atomicops_internals_mips_gcc.h" 146 #else 147 #error "Atomic operations are not supported on your platform" 148 #endif 149 150 // On some platforms we need additional declarations to make 151 // AtomicWord compatible with our other Atomic* types. 152 #if defined(OS_MACOSX) || defined(OS_OPENBSD) 153 #include "base/atomicops_internals_atomicword_compat.h" 154 #endif 155 156 #endif // BASE_ATOMICOPS_H_ 157
