1 // Copyright 2010 the V8 project authors. All rights reserved. 2 // Redistribution and use in source and binary forms, with or without 3 // modification, are permitted provided that the following conditions are 4 // met: 5 // 6 // * Redistributions of source code must retain the above copyright 7 // notice, this list of conditions and the following disclaimer. 8 // * Redistributions in binary form must reproduce the above 9 // copyright notice, this list of conditions and the following 10 // disclaimer in the documentation and/or other materials provided 11 // with the distribution. 12 // * Neither the name of Google Inc. nor the names of its 13 // contributors may be used to endorse or promote products derived 14 // from this software without specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 28 // This module gets enough CPU information to optimize the 29 // atomicops module on x86. 30 31 #include <string.h> 32 33 #include "atomicops.h" 34 #include "platform.h" 35 36 // This file only makes sense with atomicops_internals_x86_gcc.h -- it 37 // depends on structs that are defined in that file. If atomicops.h 38 // doesn't sub-include that file, then we aren't needed, and shouldn't 39 // try to do anything. 40 #ifdef V8_ATOMICOPS_INTERNALS_X86_GCC_H_ 41 42 // Inline cpuid instruction. In PIC compilations, %ebx contains the address 43 // of the global offset table. To avoid breaking such executables, this code 44 // must preserve that register's value across cpuid instructions. 45 #if defined(__i386__) 46 #define cpuid(a, b, c, d, inp) \ 47 asm("mov %%ebx, %%edi\n" \ 48 "cpuid\n" \ 49 "xchg %%edi, %%ebx\n" \ 50 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) 51 #elif defined(__x86_64__) 52 #define cpuid(a, b, c, d, inp) \ 53 asm("mov %%rbx, %%rdi\n" \ 54 "cpuid\n" \ 55 "xchg %%rdi, %%rbx\n" \ 56 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) 57 #endif 58 59 #if defined(cpuid) // initialize the struct only on x86 60 61 namespace v8 { 62 namespace internal { 63 64 // Set the flags so that code will run correctly and conservatively, so even 65 // if we haven't been initialized yet, we're probably single threaded, and our 66 // default values should hopefully be pretty safe. 67 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { 68 false, // bug can't exist before process spawns multiple threads 69 false, // no SSE2 70 }; 71 72 } } // namespace v8::internal 73 74 namespace { 75 76 // Initialize the AtomicOps_Internalx86CPUFeatures struct. 77 void AtomicOps_Internalx86CPUFeaturesInit() { 78 using v8::internal::AtomicOps_Internalx86CPUFeatures; 79 80 uint32_t eax; 81 uint32_t ebx; 82 uint32_t ecx; 83 uint32_t edx; 84 85 // Get vendor string (issue CPUID with eax = 0) 86 cpuid(eax, ebx, ecx, edx, 0); 87 char vendor[13]; 88 v8::internal::OS::MemCopy(vendor, &ebx, 4); 89 v8::internal::OS::MemCopy(vendor + 4, &edx, 4); 90 v8::internal::OS::MemCopy(vendor + 8, &ecx, 4); 91 vendor[12] = 0; 92 93 // get feature flags in ecx/edx, and family/model in eax 94 cpuid(eax, ebx, ecx, edx, 1); 95 96 int family = (eax >> 8) & 0xf; // family and model fields 97 int model = (eax >> 4) & 0xf; 98 if (family == 0xf) { // use extended family and model fields 99 family += (eax >> 20) & 0xff; 100 model += ((eax >> 16) & 0xf) << 4; 101 } 102 103 // Opteron Rev E has a bug in which on very rare occasions a locked 104 // instruction doesn't act as a read-acquire barrier if followed by a 105 // non-locked read-modify-write instruction. Rev F has this bug in 106 // pre-release versions, but not in versions released to customers, 107 // so we test only for Rev E, which is family 15, model 32..63 inclusive. 108 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD 109 family == 15 && 110 32 <= model && model <= 63) { 111 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; 112 } else { 113 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; 114 } 115 116 // edx bit 26 is SSE2 which we use to tell use whether we can use mfence 117 AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); 118 } 119 120 class AtomicOpsx86Initializer { 121 public: 122 AtomicOpsx86Initializer() { 123 AtomicOps_Internalx86CPUFeaturesInit(); 124 } 125 }; 126 127 128 // A global to get use initialized on startup via static initialization :/ 129 AtomicOpsx86Initializer g_initer; 130 131 } // namespace 132 133 #endif // if x86 134 135 #endif // ifdef V8_ATOMICOPS_INTERNALS_X86_GCC_H_ 136
