1 tblgen - Target Description To C++ Code Generator 2 ================================================= 3 4 SYNOPSIS 5 -------- 6 7 :program:`tblgen` [*options*] [*filename*] 8 9 DESCRIPTION 10 ----------- 11 12 :program:`tblgen` translates from target description (``.td``) files into C++ 13 code that can be included in the definition of an LLVM target library. Most 14 users of LLVM will not need to use this program. It is only for assisting with 15 writing an LLVM target backend. 16 17 The input and output of :program:`tblgen` is beyond the scope of this short 18 introduction. Please see :doc:`../TableGenFundamentals`. 19 20 The *filename* argument specifies the name of a Target Description (``.td``) 21 file to read as input. 22 23 OPTIONS 24 ------- 25 26 .. program:: tblgen 27 28 .. option:: -help 29 30 Print a summary of command line options. 31 32 .. option:: -o filename 33 34 Specify the output file name. If ``filename`` is ``-``, then 35 :program:`tblgen` sends its output to standard output. 36 37 .. option:: -I directory 38 39 Specify where to find other target description files for inclusion. The 40 ``directory`` value should be a full or partial path to a directory that 41 contains target description files. 42 43 .. option:: -asmparsernum N 44 45 Make -gen-asm-parser emit assembly writer number ``N``. 46 47 .. option:: -asmwriternum N 48 49 Make -gen-asm-writer emit assembly writer number ``N``. 50 51 .. option:: -class className 52 53 Print the enumeration list for this class. 54 55 .. option:: -print-records 56 57 Print all records to standard output (default). 58 59 .. option:: -print-enums 60 61 Print enumeration values for a class. 62 63 .. option:: -print-sets 64 65 Print expanded sets for testing DAG exprs. 66 67 .. option:: -gen-emitter 68 69 Generate machine code emitter. 70 71 .. option:: -gen-register-info 72 73 Generate registers and register classes info. 74 75 .. option:: -gen-instr-info 76 77 Generate instruction descriptions. 78 79 .. option:: -gen-asm-writer 80 81 Generate the assembly writer. 82 83 .. option:: -gen-disassembler 84 85 Generate disassembler. 86 87 .. option:: -gen-pseudo-lowering 88 89 Generate pseudo instruction lowering. 90 91 .. option:: -gen-dag-isel 92 93 Generate a DAG (Directed Acycle Graph) instruction selector. 94 95 .. option:: -gen-asm-matcher 96 97 Generate assembly instruction matcher. 98 99 .. option:: -gen-dfa-packetizer 100 101 Generate DFA Packetizer for VLIW targets. 102 103 .. option:: -gen-fast-isel 104 105 Generate a "fast" instruction selector. 106 107 .. option:: -gen-subtarget 108 109 Generate subtarget enumerations. 110 111 .. option:: -gen-intrinsic 112 113 Generate intrinsic information. 114 115 .. option:: -gen-tgt-intrinsic 116 117 Generate target intrinsic information. 118 119 .. option:: -gen-enhanced-disassembly-info 120 121 Generate enhanced disassembly info. 122 123 .. option:: -version 124 125 Show the version number of this program. 126 127 EXIT STATUS 128 ----------- 129 130 If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error 131 occurs, it will exit with a non-zero value. 132
