1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Thumb instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Thumb specific DAG Nodes. 16 // 17 18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22 def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); 25 }]>; 26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30 }], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33 } 34 35 def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 37 }]>; 38 39 def imm0_7_neg : PatLeaf<(i32 imm), [{ 40 return (uint32_t)-N->getZExtValue() < 8; 41 }], imm_neg_XFORM>; 42 43 def imm0_255_comp : PatLeaf<(i32 imm), [{ 44 return ~((uint32_t)N->getZExtValue()) < 256; 45 }]>; 46 47 def imm8_255 : ImmLeaf<i32, [{ 48 return Imm >= 8 && Imm < 256; 49 }]>; 50 def imm8_255_neg : PatLeaf<(i32 imm), [{ 51 unsigned Val = -N->getZExtValue(); 52 return Val >= 8 && Val < 256; 53 }], imm_neg_XFORM>; 54 55 // Break imm's up into two pieces: an immediate + a left shift. This uses 56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 57 // to get the val/shift pieces. 58 def thumb_immshifted : PatLeaf<(imm), [{ 59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 60 }]>; 61 62 def thumb_immshifted_val : SDNodeXForm<imm, [{ 63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 64 return CurDAG->getTargetConstant(V, MVT::i32); 65 }]>; 66 67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 69 return CurDAG->getTargetConstant(V, MVT::i32); 70 }]>; 71 72 // Scaled 4 immediate. 73 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 74 def t_imm0_1020s4 : Operand<i32> { 75 let PrintMethod = "printThumbS4ImmOperand"; 76 let ParserMatchClass = t_imm0_1020s4_asmoperand; 77 let OperandType = "OPERAND_IMMEDIATE"; 78 } 79 80 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 81 def t_imm0_508s4 : Operand<i32> { 82 let PrintMethod = "printThumbS4ImmOperand"; 83 let ParserMatchClass = t_imm0_508s4_asmoperand; 84 let OperandType = "OPERAND_IMMEDIATE"; 85 } 86 // Alias use only, so no printer is necessary. 87 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 88 def t_imm0_508s4_neg : Operand<i32> { 89 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 90 let OperandType = "OPERAND_IMMEDIATE"; 91 } 92 93 // Define Thumb specific addressing modes. 94 95 // unsigned 8-bit, 2-scaled memory offset 96 class OperandUnsignedOffset_b8s2 : AsmOperandClass { 97 let Name = "UnsignedOffset_b8s2"; 98 let PredicateMethod = "isUnsignedOffset<8, 2>"; 99 } 100 101 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 102 103 // thumb style PC relative operand. signed, 8 bits magnitude, 104 // two bits shift. can be represented as either [pc, #imm], #imm, 105 // or relocatable expression... 106 def ThumbMemPC : AsmOperandClass { 107 let Name = "ThumbMemPC"; 108 } 109 110 let OperandType = "OPERAND_PCREL" in { 111 def t_brtarget : Operand<OtherVT> { 112 let EncoderMethod = "getThumbBRTargetOpValue"; 113 let DecoderMethod = "DecodeThumbBROperand"; 114 } 115 116 // ADR instruction labels. 117 def t_adrlabel : Operand<i32> { 118 let EncoderMethod = "getThumbAdrLabelOpValue"; 119 let PrintMethod = "printAdrLabelOperand<2>"; 120 let ParserMatchClass = UnsignedOffset_b8s2; 121 } 122 123 def t_bcctarget : Operand<i32> { 124 let EncoderMethod = "getThumbBCCTargetOpValue"; 125 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 126 } 127 128 def t_cbtarget : Operand<i32> { 129 let EncoderMethod = "getThumbCBTargetOpValue"; 130 let DecoderMethod = "DecodeThumbCmpBROperand"; 131 } 132 133 def t_bltarget : Operand<i32> { 134 let EncoderMethod = "getThumbBLTargetOpValue"; 135 let DecoderMethod = "DecodeThumbBLTargetOperand"; 136 } 137 138 def t_blxtarget : Operand<i32> { 139 let EncoderMethod = "getThumbBLXTargetOpValue"; 140 let DecoderMethod = "DecodeThumbBLXOffset"; 141 } 142 143 // t_addrmode_pc := <label> => pc + imm8 * 4 144 // 145 def t_addrmode_pc : Operand<i32> { 146 let EncoderMethod = "getAddrModePCOpValue"; 147 let DecoderMethod = "DecodeThumbAddrModePC"; 148 let PrintMethod = "printThumbLdrLabelOperand"; 149 let ParserMatchClass = ThumbMemPC; 150 } 151 } 152 153 // t_addrmode_rr := reg + reg 154 // 155 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 156 def t_addrmode_rr : Operand<i32>, 157 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 158 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 159 let PrintMethod = "printThumbAddrModeRROperand"; 160 let DecoderMethod = "DecodeThumbAddrModeRR"; 161 let ParserMatchClass = t_addrmode_rr_asm_operand; 162 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 163 } 164 165 // t_addrmode_rrs := reg + reg 166 // 167 // We use separate scaled versions because the Select* functions need 168 // to explicitly check for a matching constant and return false here so that 169 // the reg+imm forms will match instead. This is a horrible way to do that, 170 // as it forces tight coupling between the methods, but it's how selectiondag 171 // currently works. 172 def t_addrmode_rrs1 : Operand<i32>, 173 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 174 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 175 let PrintMethod = "printThumbAddrModeRROperand"; 176 let DecoderMethod = "DecodeThumbAddrModeRR"; 177 let ParserMatchClass = t_addrmode_rr_asm_operand; 178 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 179 } 180 def t_addrmode_rrs2 : Operand<i32>, 181 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 182 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 183 let DecoderMethod = "DecodeThumbAddrModeRR"; 184 let PrintMethod = "printThumbAddrModeRROperand"; 185 let ParserMatchClass = t_addrmode_rr_asm_operand; 186 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 187 } 188 def t_addrmode_rrs4 : Operand<i32>, 189 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 190 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 191 let DecoderMethod = "DecodeThumbAddrModeRR"; 192 let PrintMethod = "printThumbAddrModeRROperand"; 193 let ParserMatchClass = t_addrmode_rr_asm_operand; 194 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 195 } 196 197 // t_addrmode_is4 := reg + imm5 * 4 198 // 199 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 200 def t_addrmode_is4 : Operand<i32>, 201 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 202 let EncoderMethod = "getAddrModeISOpValue"; 203 let DecoderMethod = "DecodeThumbAddrModeIS"; 204 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 205 let ParserMatchClass = t_addrmode_is4_asm_operand; 206 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 207 } 208 209 // t_addrmode_is2 := reg + imm5 * 2 210 // 211 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 212 def t_addrmode_is2 : Operand<i32>, 213 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 214 let EncoderMethod = "getAddrModeISOpValue"; 215 let DecoderMethod = "DecodeThumbAddrModeIS"; 216 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 217 let ParserMatchClass = t_addrmode_is2_asm_operand; 218 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 219 } 220 221 // t_addrmode_is1 := reg + imm5 222 // 223 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 224 def t_addrmode_is1 : Operand<i32>, 225 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 226 let EncoderMethod = "getAddrModeISOpValue"; 227 let DecoderMethod = "DecodeThumbAddrModeIS"; 228 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 229 let ParserMatchClass = t_addrmode_is1_asm_operand; 230 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 231 } 232 233 // t_addrmode_sp := sp + imm8 * 4 234 // 235 // FIXME: This really shouldn't have an explicit SP operand at all. It should 236 // be implicit, just like in the instruction encoding itself. 237 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 238 def t_addrmode_sp : Operand<i32>, 239 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 240 let EncoderMethod = "getAddrModeThumbSPOpValue"; 241 let DecoderMethod = "DecodeThumbAddrModeSP"; 242 let PrintMethod = "printThumbAddrModeSPOperand"; 243 let ParserMatchClass = t_addrmode_sp_asm_operand; 244 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 245 } 246 247 //===----------------------------------------------------------------------===// 248 // Miscellaneous Instructions. 249 // 250 251 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 252 // from removing one half of the matched pairs. That breaks PEI, which assumes 253 // these will always be in pairs, and asserts if it finds otherwise. Better way? 254 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 255 def tADJCALLSTACKUP : 256 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 257 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 258 Requires<[IsThumb, IsThumb1Only]>; 259 260 def tADJCALLSTACKDOWN : 261 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 262 [(ARMcallseq_start imm:$amt)]>, 263 Requires<[IsThumb, IsThumb1Only]>; 264 } 265 266 class T1SystemEncoding<bits<8> opc> 267 : T1Encoding<0b101111> { 268 let Inst{9-8} = 0b11; 269 let Inst{7-0} = opc; 270 } 271 272 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, 273 T1SystemEncoding<0x00>, // A8.6.110 274 Requires<[IsThumb2]>; 275 276 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, 277 T1SystemEncoding<0x10>, // A8.6.410 278 Requires<[IsThumb2]>; 279 280 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, 281 T1SystemEncoding<0x20>, // A8.6.408 282 Requires<[IsThumb2]>; 283 284 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, 285 T1SystemEncoding<0x30>, // A8.6.409 286 Requires<[IsThumb2]>; 287 288 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, 289 T1SystemEncoding<0x40>, // A8.6.157 290 Requires<[IsThumb2]>; 291 292 // The imm operand $val can be used by a debugger to store more information 293 // about the breakpoint. 294 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 295 []>, 296 T1Encoding<0b101111> { 297 let Inst{9-8} = 0b10; 298 // A8.6.22 299 bits<8> val; 300 let Inst{7-0} = val; 301 } 302 303 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 304 []>, T1Encoding<0b101101> { 305 bits<1> end; 306 // A8.6.156 307 let Inst{9-5} = 0b10010; 308 let Inst{4} = 1; 309 let Inst{3} = end; 310 let Inst{2-0} = 0b000; 311 } 312 313 // Change Processor State is a system instruction -- for disassembly only. 314 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 315 NoItinerary, "cps$imod $iflags", []>, 316 T1Misc<0b0110011> { 317 // A8.6.38 & B6.1.1 318 bit imod; 319 bits<3> iflags; 320 321 let Inst{4} = imod; 322 let Inst{3} = 0; 323 let Inst{2-0} = iflags; 324 let DecoderMethod = "DecodeThumbCPS"; 325 } 326 327 // For both thumb1 and thumb2. 328 let isNotDuplicable = 1, isCodeGenOnly = 1 in 329 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 330 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 331 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 332 // A8.6.6 333 bits<3> dst; 334 let Inst{6-3} = 0b1111; // Rm = pc 335 let Inst{2-0} = dst; 336 } 337 338 // ADD <Rd>, sp, #<imm8> 339 // FIXME: This should not be marked as having side effects, and it should be 340 // rematerializable. Clearing the side effect bit causes miscompilations, 341 // probably because the instruction can be moved around. 342 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 343 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 344 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 345 // A6.2 & A8.6.8 346 bits<3> dst; 347 bits<8> imm; 348 let Inst{10-8} = dst; 349 let Inst{7-0} = imm; 350 let DecoderMethod = "DecodeThumbAddSpecialReg"; 351 } 352 353 // ADD sp, sp, #<imm7> 354 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 355 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 356 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 357 // A6.2.5 & A8.6.8 358 bits<7> imm; 359 let Inst{6-0} = imm; 360 let DecoderMethod = "DecodeThumbAddSPImm"; 361 } 362 363 // SUB sp, sp, #<imm7> 364 // FIXME: The encoding and the ASM string don't match up. 365 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 366 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 367 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 368 // A6.2.5 & A8.6.214 369 bits<7> imm; 370 let Inst{6-0} = imm; 371 let DecoderMethod = "DecodeThumbAddSPImm"; 372 } 373 374 def : tInstAlias<"add${p} sp, $imm", 375 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 376 def : tInstAlias<"add${p} sp, sp, $imm", 377 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 378 379 // Can optionally specify SP as a three operand instruction. 380 def : tInstAlias<"add${p} sp, sp, $imm", 381 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 382 def : tInstAlias<"sub${p} sp, sp, $imm", 383 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 384 385 // ADD <Rm>, sp 386 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 387 "add", "\t$Rdn, $sp, $Rn", []>, 388 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 389 // A8.6.9 Encoding T1 390 bits<4> Rdn; 391 let Inst{7} = Rdn{3}; 392 let Inst{6-3} = 0b1101; 393 let Inst{2-0} = Rdn{2-0}; 394 let DecoderMethod = "DecodeThumbAddSPReg"; 395 } 396 397 // ADD sp, <Rm> 398 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 399 "add", "\t$Rdn, $Rm", []>, 400 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 401 // A8.6.9 Encoding T2 402 bits<4> Rm; 403 let Inst{7} = 1; 404 let Inst{6-3} = Rm; 405 let Inst{2-0} = 0b101; 406 let DecoderMethod = "DecodeThumbAddSPReg"; 407 } 408 409 //===----------------------------------------------------------------------===// 410 // Control Flow Instructions. 411 // 412 413 // Indirect branches 414 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 415 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 416 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 417 // A6.2.3 & A8.6.25 418 bits<4> Rm; 419 let Inst{6-3} = Rm; 420 let Inst{2-0} = 0b000; 421 let Unpredictable{2-0} = 0b111; 422 } 423 } 424 425 let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 426 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 427 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 428 429 // Alternative return instruction used by vararg functions. 430 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 431 2, IIC_Br, [], 432 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 433 } 434 435 // All calls clobber the non-callee saved registers. SP is marked as a use to 436 // prevent stack-pointer assignments that appear immediately before calls from 437 // potentially appearing dead. 438 let isCall = 1, 439 Defs = [LR], Uses = [SP] in { 440 // Also used for Thumb2 441 def tBL : TIx2<0b11110, 0b11, 1, 442 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 443 "bl${p}\t$func", 444 [(ARMtcall tglobaladdr:$func)]>, 445 Requires<[IsThumb]>, Sched<[WriteBrL]> { 446 bits<24> func; 447 let Inst{26} = func{23}; 448 let Inst{25-16} = func{20-11}; 449 let Inst{13} = func{22}; 450 let Inst{11} = func{21}; 451 let Inst{10-0} = func{10-0}; 452 } 453 454 // ARMv5T and above, also used for Thumb2 455 def tBLXi : TIx2<0b11110, 0b11, 0, 456 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 457 "blx${p}\t$func", 458 [(ARMcall tglobaladdr:$func)]>, 459 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> { 460 bits<24> func; 461 let Inst{26} = func{23}; 462 let Inst{25-16} = func{20-11}; 463 let Inst{13} = func{22}; 464 let Inst{11} = func{21}; 465 let Inst{10-1} = func{10-1}; 466 let Inst{0} = 0; // func{0} is assumed zero 467 } 468 469 // Also used for Thumb2 470 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 471 "blx${p}\t$func", 472 [(ARMtcall GPR:$func)]>, 473 Requires<[IsThumb, HasV5T]>, 474 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 475 bits<4> func; 476 let Inst{6-3} = func; 477 let Inst{2-0} = 0b000; 478 } 479 480 // ARMv4T 481 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 482 4, IIC_Br, 483 [(ARMcall_nolink tGPR:$func)]>, 484 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 485 } 486 487 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 488 let isPredicable = 1 in 489 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 490 "b", "\t$target", [(br bb:$target)]>, 491 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 492 bits<11> target; 493 let Inst{10-0} = target; 494 } 495 496 // Far jump 497 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 498 // the clobber of LR. 499 let Defs = [LR] in 500 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 501 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>, 502 Sched<[WriteBrTbl]>; 503 504 def tBR_JTr : tPseudoInst<(outs), 505 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 506 0, IIC_Br, 507 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>, 508 Sched<[WriteBrTbl]> { 509 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 510 } 511 } 512 513 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 514 // a two-value operand where a dag node expects two operands. :( 515 let isBranch = 1, isTerminator = 1 in 516 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 517 "b${p}\t$target", 518 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 519 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 520 bits<4> p; 521 bits<8> target; 522 let Inst{11-8} = p; 523 let Inst{7-0} = target; 524 } 525 526 527 // Tail calls 528 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 529 // IOS versions. 530 let Uses = [SP] in { 531 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 532 4, IIC_Br, [], 533 (tBX GPR:$dst, (ops 14, zero_reg))>, 534 Requires<[IsThumb]>, Sched<[WriteBr]>; 535 } 536 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls 537 // on IOS), so it's in ARMInstrThumb2.td. 538 // Non-IOS version: 539 let Uses = [SP] in { 540 def tTAILJMPdND : tPseudoExpand<(outs), 541 (ins t_brtarget:$dst, pred:$p), 542 4, IIC_Br, [], 543 (tB t_brtarget:$dst, pred:$p)>, 544 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>; 545 } 546 } 547 548 549 // A8.6.218 Supervisor Call (Software Interrupt) 550 // A8.6.16 B: Encoding T1 551 // If Inst{11-8} == 0b1111 then SEE SVC 552 let isCall = 1, Uses = [SP] in 553 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 554 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 555 bits<8> imm; 556 let Inst{15-12} = 0b1101; 557 let Inst{11-8} = 0b1111; 558 let Inst{7-0} = imm; 559 } 560 561 // The assembler uses 0xDEFE for a trap instruction. 562 let isBarrier = 1, isTerminator = 1 in 563 def tTRAP : TI<(outs), (ins), IIC_Br, 564 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 565 let Inst = 0xdefe; 566 } 567 568 //===----------------------------------------------------------------------===// 569 // Load Store Instructions. 570 // 571 572 // Loads: reg/reg and reg/imm5 573 let canFoldAsLoad = 1, isReMaterializable = 1 in 574 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 575 Operand AddrMode_r, Operand AddrMode_i, 576 AddrMode am, InstrItinClass itin_r, 577 InstrItinClass itin_i, string asm, 578 PatFrag opnode> { 579 def r : // reg/reg 580 T1pILdStEncode<reg_opc, 581 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 582 am, itin_r, asm, "\t$Rt, $addr", 583 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 584 def i : // reg/imm5 585 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 586 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 587 am, itin_i, asm, "\t$Rt, $addr", 588 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 589 } 590 // Stores: reg/reg and reg/imm5 591 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 592 Operand AddrMode_r, Operand AddrMode_i, 593 AddrMode am, InstrItinClass itin_r, 594 InstrItinClass itin_i, string asm, 595 PatFrag opnode> { 596 def r : // reg/reg 597 T1pILdStEncode<reg_opc, 598 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 599 am, itin_r, asm, "\t$Rt, $addr", 600 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 601 def i : // reg/imm5 602 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 603 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 604 am, itin_i, asm, "\t$Rt, $addr", 605 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 606 } 607 608 // A8.6.57 & A8.6.60 609 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 610 t_addrmode_is4, AddrModeT1_4, 611 IIC_iLoad_r, IIC_iLoad_i, "ldr", 612 UnOpFrag<(load node:$Src)>>; 613 614 // A8.6.64 & A8.6.61 615 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 616 t_addrmode_is1, AddrModeT1_1, 617 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 618 UnOpFrag<(zextloadi8 node:$Src)>>; 619 620 // A8.6.76 & A8.6.73 621 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 622 t_addrmode_is2, AddrModeT1_2, 623 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 624 UnOpFrag<(zextloadi16 node:$Src)>>; 625 626 let AddedComplexity = 10 in 627 def tLDRSB : // A8.6.80 628 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 629 AddrModeT1_1, IIC_iLoad_bh_r, 630 "ldrsb", "\t$Rt, $addr", 631 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 632 633 let AddedComplexity = 10 in 634 def tLDRSH : // A8.6.84 635 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 636 AddrModeT1_2, IIC_iLoad_bh_r, 637 "ldrsh", "\t$Rt, $addr", 638 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 639 640 let canFoldAsLoad = 1 in 641 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 642 "ldr", "\t$Rt, $addr", 643 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 644 T1LdStSP<{1,?,?}> { 645 bits<3> Rt; 646 bits<8> addr; 647 let Inst{10-8} = Rt; 648 let Inst{7-0} = addr; 649 } 650 651 let canFoldAsLoad = 1, isReMaterializable = 1 in 652 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 653 "ldr", "\t$Rt, $addr", 654 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 655 T1Encoding<{0,1,0,0,1,?}> { 656 // A6.2 & A8.6.59 657 bits<3> Rt; 658 bits<8> addr; 659 let Inst{10-8} = Rt; 660 let Inst{7-0} = addr; 661 } 662 663 def : tInstAlias<"ldr${p}.n $Rt, $addr", 664 (tLDRpci tGPR:$Rt, t_addrmode_pc:$addr, pred:$p), 0>; 665 666 // A8.6.194 & A8.6.192 667 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 668 t_addrmode_is4, AddrModeT1_4, 669 IIC_iStore_r, IIC_iStore_i, "str", 670 BinOpFrag<(store node:$LHS, node:$RHS)>>; 671 672 // A8.6.197 & A8.6.195 673 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 674 t_addrmode_is1, AddrModeT1_1, 675 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 676 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 677 678 // A8.6.207 & A8.6.205 679 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 680 t_addrmode_is2, AddrModeT1_2, 681 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 682 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 683 684 685 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 686 "str", "\t$Rt, $addr", 687 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 688 T1LdStSP<{0,?,?}> { 689 bits<3> Rt; 690 bits<8> addr; 691 let Inst{10-8} = Rt; 692 let Inst{7-0} = addr; 693 } 694 695 //===----------------------------------------------------------------------===// 696 // Load / store multiple Instructions. 697 // 698 699 // These require base address to be written back or one of the loaded regs. 700 let neverHasSideEffects = 1 in { 701 702 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 703 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 704 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 705 bits<3> Rn; 706 bits<8> regs; 707 let Inst{10-8} = Rn; 708 let Inst{7-0} = regs; 709 } 710 711 // Writeback version is just a pseudo, as there's no encoding difference. 712 // Writeback happens iff the base register is not in the destination register 713 // list. 714 def tLDMIA_UPD : 715 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 716 "$Rn = $wb", IIC_iLoad_mu>, 717 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 718 let Size = 2; 719 let OutOperandList = (outs GPR:$wb); 720 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 721 let Pattern = []; 722 let isCodeGenOnly = 1; 723 let isPseudo = 1; 724 list<Predicate> Predicates = [IsThumb]; 725 } 726 727 // There is no non-writeback version of STM for Thumb. 728 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 729 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 730 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 731 AddrModeNone, 2, IIC_iStore_mu, 732 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 733 T1Encoding<{1,1,0,0,0,?}> { 734 bits<3> Rn; 735 bits<8> regs; 736 let Inst{10-8} = Rn; 737 let Inst{7-0} = regs; 738 } 739 740 } // neverHasSideEffects 741 742 def : InstAlias<"ldm${p} $Rn!, $regs", 743 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 744 Requires<[IsThumb, IsThumb1Only]>; 745 746 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 747 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 748 IIC_iPop, 749 "pop${p}\t$regs", []>, 750 T1Misc<{1,1,0,?,?,?,?}> { 751 bits<16> regs; 752 let Inst{8} = regs{15}; 753 let Inst{7-0} = regs{7-0}; 754 } 755 756 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 757 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 758 IIC_iStore_m, 759 "push${p}\t$regs", []>, 760 T1Misc<{0,1,0,?,?,?,?}> { 761 bits<16> regs; 762 let Inst{8} = regs{14}; 763 let Inst{7-0} = regs{7-0}; 764 } 765 766 //===----------------------------------------------------------------------===// 767 // Arithmetic Instructions. 768 // 769 770 // Helper classes for encoding T1pI patterns: 771 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 772 string opc, string asm, list<dag> pattern> 773 : T1pI<oops, iops, itin, opc, asm, pattern>, 774 T1DataProcessing<opA> { 775 bits<3> Rm; 776 bits<3> Rn; 777 let Inst{5-3} = Rm; 778 let Inst{2-0} = Rn; 779 } 780 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 781 string opc, string asm, list<dag> pattern> 782 : T1pI<oops, iops, itin, opc, asm, pattern>, 783 T1Misc<opA> { 784 bits<3> Rm; 785 bits<3> Rd; 786 let Inst{5-3} = Rm; 787 let Inst{2-0} = Rd; 788 } 789 790 // Helper classes for encoding T1sI patterns: 791 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 792 string opc, string asm, list<dag> pattern> 793 : T1sI<oops, iops, itin, opc, asm, pattern>, 794 T1DataProcessing<opA> { 795 bits<3> Rd; 796 bits<3> Rn; 797 let Inst{5-3} = Rn; 798 let Inst{2-0} = Rd; 799 } 800 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 801 string opc, string asm, list<dag> pattern> 802 : T1sI<oops, iops, itin, opc, asm, pattern>, 803 T1General<opA> { 804 bits<3> Rm; 805 bits<3> Rn; 806 bits<3> Rd; 807 let Inst{8-6} = Rm; 808 let Inst{5-3} = Rn; 809 let Inst{2-0} = Rd; 810 } 811 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 812 string opc, string asm, list<dag> pattern> 813 : T1sI<oops, iops, itin, opc, asm, pattern>, 814 T1General<opA> { 815 bits<3> Rd; 816 bits<3> Rm; 817 let Inst{5-3} = Rm; 818 let Inst{2-0} = Rd; 819 } 820 821 // Helper classes for encoding T1sIt patterns: 822 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 823 string opc, string asm, list<dag> pattern> 824 : T1sIt<oops, iops, itin, opc, asm, pattern>, 825 T1DataProcessing<opA> { 826 bits<3> Rdn; 827 bits<3> Rm; 828 let Inst{5-3} = Rm; 829 let Inst{2-0} = Rdn; 830 } 831 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 832 string opc, string asm, list<dag> pattern> 833 : T1sIt<oops, iops, itin, opc, asm, pattern>, 834 T1General<opA> { 835 bits<3> Rdn; 836 bits<8> imm8; 837 let Inst{10-8} = Rdn; 838 let Inst{7-0} = imm8; 839 } 840 841 // Add with carry register 842 let isCommutable = 1, Uses = [CPSR] in 843 def tADC : // A8.6.2 844 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 845 "adc", "\t$Rdn, $Rm", 846 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 847 848 // Add immediate 849 def tADDi3 : // A8.6.4 T1 850 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 851 IIC_iALUi, 852 "add", "\t$Rd, $Rm, $imm3", 853 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 854 Sched<[WriteALU]> { 855 bits<3> imm3; 856 let Inst{8-6} = imm3; 857 } 858 859 def tADDi8 : // A8.6.4 T2 860 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 861 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 862 "add", "\t$Rdn, $imm8", 863 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 864 Sched<[WriteALU]>; 865 866 // Add register 867 let isCommutable = 1 in 868 def tADDrr : // A8.6.6 T1 869 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 870 IIC_iALUr, 871 "add", "\t$Rd, $Rn, $Rm", 872 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 873 874 let neverHasSideEffects = 1 in 875 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 876 "add", "\t$Rdn, $Rm", []>, 877 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 878 // A8.6.6 T2 879 bits<4> Rdn; 880 bits<4> Rm; 881 let Inst{7} = Rdn{3}; 882 let Inst{6-3} = Rm; 883 let Inst{2-0} = Rdn{2-0}; 884 } 885 886 // AND register 887 let isCommutable = 1 in 888 def tAND : // A8.6.12 889 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 890 IIC_iBITr, 891 "and", "\t$Rdn, $Rm", 892 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 893 894 // ASR immediate 895 def tASRri : // A8.6.14 896 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 897 IIC_iMOVsi, 898 "asr", "\t$Rd, $Rm, $imm5", 899 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 900 Sched<[WriteALU]> { 901 bits<5> imm5; 902 let Inst{10-6} = imm5; 903 } 904 905 // ASR register 906 def tASRrr : // A8.6.15 907 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 908 IIC_iMOVsr, 909 "asr", "\t$Rdn, $Rm", 910 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 911 912 // BIC register 913 def tBIC : // A8.6.20 914 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 915 IIC_iBITr, 916 "bic", "\t$Rdn, $Rm", 917 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 918 Sched<[WriteALU]>; 919 920 // CMN register 921 let isCompare = 1, Defs = [CPSR] in { 922 //FIXME: Disable CMN, as CCodes are backwards from compare expectations 923 // Compare-to-zero still works out, just not the relationals 924 //def tCMN : // A8.6.33 925 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 926 // IIC_iCMPr, 927 // "cmn", "\t$lhs, $rhs", 928 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 929 930 def tCMNz : // A8.6.33 931 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 932 IIC_iCMPr, 933 "cmn", "\t$Rn, $Rm", 934 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 935 936 } // isCompare = 1, Defs = [CPSR] 937 938 // CMP immediate 939 let isCompare = 1, Defs = [CPSR] in { 940 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 941 "cmp", "\t$Rn, $imm8", 942 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 943 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 944 // A8.6.35 945 bits<3> Rn; 946 bits<8> imm8; 947 let Inst{10-8} = Rn; 948 let Inst{7-0} = imm8; 949 } 950 951 // CMP register 952 def tCMPr : // A8.6.36 T1 953 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 954 IIC_iCMPr, 955 "cmp", "\t$Rn, $Rm", 956 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 957 958 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 959 "cmp", "\t$Rn, $Rm", []>, 960 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 961 // A8.6.36 T2 962 bits<4> Rm; 963 bits<4> Rn; 964 let Inst{7} = Rn{3}; 965 let Inst{6-3} = Rm; 966 let Inst{2-0} = Rn{2-0}; 967 } 968 } // isCompare = 1, Defs = [CPSR] 969 970 971 // XOR register 972 let isCommutable = 1 in 973 def tEOR : // A8.6.45 974 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 975 IIC_iBITr, 976 "eor", "\t$Rdn, $Rm", 977 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 978 979 // LSL immediate 980 def tLSLri : // A8.6.88 981 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 982 IIC_iMOVsi, 983 "lsl", "\t$Rd, $Rm, $imm5", 984 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 985 Sched<[WriteALU]> { 986 bits<5> imm5; 987 let Inst{10-6} = imm5; 988 } 989 990 // LSL register 991 def tLSLrr : // A8.6.89 992 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 993 IIC_iMOVsr, 994 "lsl", "\t$Rdn, $Rm", 995 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 996 997 // LSR immediate 998 def tLSRri : // A8.6.90 999 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1000 IIC_iMOVsi, 1001 "lsr", "\t$Rd, $Rm, $imm5", 1002 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1003 Sched<[WriteALU]> { 1004 bits<5> imm5; 1005 let Inst{10-6} = imm5; 1006 } 1007 1008 // LSR register 1009 def tLSRrr : // A8.6.91 1010 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1011 IIC_iMOVsr, 1012 "lsr", "\t$Rdn, $Rm", 1013 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1014 1015 // Move register 1016 let isMoveImm = 1 in 1017 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1018 "mov", "\t$Rd, $imm8", 1019 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1020 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1021 // A8.6.96 1022 bits<3> Rd; 1023 bits<8> imm8; 1024 let Inst{10-8} = Rd; 1025 let Inst{7-0} = imm8; 1026 } 1027 // Because we have an explicit tMOVSr below, we need an alias to handle 1028 // the immediate "movs" form here. Blech. 1029 def : tInstAlias <"movs $Rdn, $imm", 1030 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1031 1032 // A7-73: MOV(2) - mov setting flag. 1033 1034 let neverHasSideEffects = 1 in { 1035 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1036 2, IIC_iMOVr, 1037 "mov", "\t$Rd, $Rm", "", []>, 1038 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1039 // A8.6.97 1040 bits<4> Rd; 1041 bits<4> Rm; 1042 let Inst{7} = Rd{3}; 1043 let Inst{6-3} = Rm; 1044 let Inst{2-0} = Rd{2-0}; 1045 } 1046 let Defs = [CPSR] in 1047 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1048 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1049 // A8.6.97 1050 bits<3> Rd; 1051 bits<3> Rm; 1052 let Inst{15-6} = 0b0000000000; 1053 let Inst{5-3} = Rm; 1054 let Inst{2-0} = Rd; 1055 } 1056 } // neverHasSideEffects 1057 1058 // Multiply register 1059 let isCommutable = 1 in 1060 def tMUL : // A8.6.105 T1 1061 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1062 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1063 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1064 T1DataProcessing<0b1101> { 1065 bits<3> Rd; 1066 bits<3> Rn; 1067 let Inst{5-3} = Rn; 1068 let Inst{2-0} = Rd; 1069 let AsmMatchConverter = "cvtThumbMultiply"; 1070 } 1071 1072 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1073 pred:$p)>; 1074 1075 // Move inverse register 1076 def tMVN : // A8.6.107 1077 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1078 "mvn", "\t$Rd, $Rn", 1079 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1080 1081 // Bitwise or register 1082 let isCommutable = 1 in 1083 def tORR : // A8.6.114 1084 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1085 IIC_iBITr, 1086 "orr", "\t$Rdn, $Rm", 1087 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1088 1089 // Swaps 1090 def tREV : // A8.6.134 1091 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1092 IIC_iUNAr, 1093 "rev", "\t$Rd, $Rm", 1094 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1095 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1096 1097 def tREV16 : // A8.6.135 1098 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1099 IIC_iUNAr, 1100 "rev16", "\t$Rd, $Rm", 1101 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1102 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1103 1104 def tREVSH : // A8.6.136 1105 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1106 IIC_iUNAr, 1107 "revsh", "\t$Rd, $Rm", 1108 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1109 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1110 1111 // Rotate right register 1112 def tROR : // A8.6.139 1113 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1114 IIC_iMOVsr, 1115 "ror", "\t$Rdn, $Rm", 1116 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1117 Sched<[WriteALU]>; 1118 1119 // Negate register 1120 def tRSB : // A8.6.141 1121 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1122 IIC_iALUi, 1123 "rsb", "\t$Rd, $Rn, #0", 1124 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1125 1126 // Subtract with carry register 1127 let Uses = [CPSR] in 1128 def tSBC : // A8.6.151 1129 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1130 IIC_iALUr, 1131 "sbc", "\t$Rdn, $Rm", 1132 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1133 Sched<[WriteALU]>; 1134 1135 // Subtract immediate 1136 def tSUBi3 : // A8.6.210 T1 1137 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1138 IIC_iALUi, 1139 "sub", "\t$Rd, $Rm, $imm3", 1140 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1141 Sched<[WriteALU]> { 1142 bits<3> imm3; 1143 let Inst{8-6} = imm3; 1144 } 1145 1146 def tSUBi8 : // A8.6.210 T2 1147 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1148 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1149 "sub", "\t$Rdn, $imm8", 1150 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1151 Sched<[WriteALU]>; 1152 1153 // Subtract register 1154 def tSUBrr : // A8.6.212 1155 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1156 IIC_iALUr, 1157 "sub", "\t$Rd, $Rn, $Rm", 1158 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1159 Sched<[WriteALU]>; 1160 1161 // Sign-extend byte 1162 def tSXTB : // A8.6.222 1163 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1164 IIC_iUNAr, 1165 "sxtb", "\t$Rd, $Rm", 1166 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1167 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1168 Sched<[WriteALU]>; 1169 1170 // Sign-extend short 1171 def tSXTH : // A8.6.224 1172 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1173 IIC_iUNAr, 1174 "sxth", "\t$Rd, $Rm", 1175 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1176 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1177 Sched<[WriteALU]>; 1178 1179 // Test 1180 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1181 def tTST : // A8.6.230 1182 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1183 "tst", "\t$Rn, $Rm", 1184 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1185 Sched<[WriteALU]>; 1186 1187 // Zero-extend byte 1188 def tUXTB : // A8.6.262 1189 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1190 IIC_iUNAr, 1191 "uxtb", "\t$Rd, $Rm", 1192 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1193 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1194 Sched<[WriteALU]>; 1195 1196 // Zero-extend short 1197 def tUXTH : // A8.6.264 1198 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1199 IIC_iUNAr, 1200 "uxth", "\t$Rd, $Rm", 1201 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1202 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1203 1204 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1205 // Expanded after instruction selection into a branch sequence. 1206 let usesCustomInserter = 1 in // Expanded after instruction selection. 1207 def tMOVCCr_pseudo : 1208 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1209 NoItinerary, 1210 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1211 1212 // tLEApcrel - Load a pc-relative address into a register without offending the 1213 // assembler. 1214 1215 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1216 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1217 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1218 bits<3> Rd; 1219 bits<8> addr; 1220 let Inst{10-8} = Rd; 1221 let Inst{7-0} = addr; 1222 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1223 } 1224 1225 let neverHasSideEffects = 1, isReMaterializable = 1 in 1226 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1227 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1228 1229 let hasSideEffects = 1 in 1230 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1231 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1232 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1233 1234 //===----------------------------------------------------------------------===// 1235 // TLS Instructions 1236 // 1237 1238 // __aeabi_read_tp preserves the registers r1-r3. 1239 // This is a pseudo inst so that we can get the encoding right, 1240 // complete with fixup for the aeabi_read_tp function. 1241 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1242 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1243 [(set R0, ARMthread_pointer)]>, 1244 Sched<[WriteBr]>; 1245 1246 //===----------------------------------------------------------------------===// 1247 // SJLJ Exception handling intrinsics 1248 // 1249 1250 // eh_sjlj_setjmp() is an instruction sequence to store the return address and 1251 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1252 // from some other function to get here, and we're using the stack frame for the 1253 // containing function to save/restore registers, we can't keep anything live in 1254 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1255 // tromped upon when we get here from a longjmp(). We force everything out of 1256 // registers except for our own input by listing the relevant registers in 1257 // Defs. By doing so, we also cause the prologue/epilogue code to actively 1258 // preserve all of the callee-saved resgisters, which is exactly what we want. 1259 // $val is a scratch register for our use. 1260 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1261 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1262 usesCustomInserter = 1 in 1263 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1264 AddrModeNone, 0, NoItinerary, "","", 1265 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1266 1267 // FIXME: Non-IOS version(s) 1268 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1269 Defs = [ R7, LR, SP ] in 1270 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1271 AddrModeNone, 0, IndexModeNone, 1272 Pseudo, NoItinerary, "", "", 1273 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1274 Requires<[IsThumb, IsIOS]>; 1275 1276 //===----------------------------------------------------------------------===// 1277 // Non-Instruction Patterns 1278 // 1279 1280 // Comparisons 1281 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1282 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1283 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1284 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1285 1286 // Add with carry 1287 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1288 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1289 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1290 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1291 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1292 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1293 1294 // Subtract with carry 1295 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1296 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1297 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1298 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1299 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1300 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1301 1302 // ConstantPool, GlobalAddress 1303 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1304 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1305 1306 // JumpTable 1307 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1308 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1309 1310 // Direct calls 1311 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1312 Requires<[IsThumb]>; 1313 1314 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1315 Requires<[IsThumb, HasV5T]>; 1316 1317 // Indirect calls to ARM routines 1318 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1319 Requires<[IsThumb, HasV5T]>; 1320 1321 // zextload i1 -> zextload i8 1322 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1323 (tLDRBr t_addrmode_rrs1:$addr)>; 1324 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1325 (tLDRBi t_addrmode_is1:$addr)>; 1326 1327 // extload -> zextload 1328 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1329 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1330 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1331 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1332 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1333 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1334 1335 // If it's impossible to use [r,r] address mode for sextload, select to 1336 // ldr{b|h} + sxt{b|h} instead. 1337 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1338 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1339 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1340 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1341 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1342 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1343 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1344 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1345 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1346 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1347 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1348 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1349 1350 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1351 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1352 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1353 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1354 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1355 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1356 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1357 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1358 1359 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1360 (tLDRBi t_addrmode_is1:$src)>; 1361 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src), 1362 (tLDRBr t_addrmode_rrs1:$src)>; 1363 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1364 (tLDRHi t_addrmode_is2:$src)>; 1365 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src), 1366 (tLDRHr t_addrmode_rrs2:$src)>; 1367 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1368 (tLDRi t_addrmode_is4:$src)>; 1369 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src), 1370 (tLDRr t_addrmode_rrs4:$src)>; 1371 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1372 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1373 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val), 1374 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>; 1375 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1376 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1377 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val), 1378 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>; 1379 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1380 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1381 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val), 1382 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>; 1383 1384 // Large immediate handling. 1385 1386 // Two piece imms. 1387 def : T1Pat<(i32 thumb_immshifted:$src), 1388 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1389 (thumb_immshifted_shamt imm:$src))>; 1390 1391 def : T1Pat<(i32 imm0_255_comp:$src), 1392 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1393 1394 // Pseudo instruction that combines ldr from constpool and add pc. This should 1395 // be expanded into two instructions late to allow if-conversion and 1396 // scheduling. 1397 let isReMaterializable = 1 in 1398 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1399 NoItinerary, 1400 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1401 imm:$cp))]>, 1402 Requires<[IsThumb, IsThumb1Only]>; 1403 1404 // Pseudo-instruction for merged POP and return. 1405 // FIXME: remove when we have a way to marking a MI with these properties. 1406 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1407 hasExtraDefRegAllocReq = 1 in 1408 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1409 2, IIC_iPop_Br, [], 1410 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1411 1412 // Indirect branch using "mov pc, $Rm" 1413 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1414 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1415 2, IIC_Br, [(brind GPR:$Rm)], 1416 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1417 } 1418 1419 1420 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1421 // encoding is available on ARMv6K, but we don't differentiate that finely. 1422 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1423 1424 1425 // For round-trip assembly/disassembly, we have to handle a CPS instruction 1426 // without any iflags. That's not, strictly speaking, valid syntax, but it's 1427 // a useful extension and assembles to defined behaviour (the insn does 1428 // nothing). 1429 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1430 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1431 1432 // "neg" is and alias for "rsb rd, rn, #0" 1433 def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1434 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1435 1436 1437 // Implied destination operand forms for shifts. 1438 def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1439 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1440 def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1441 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1442 def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1443 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1444
