1 //===-- MipsCondMov.td - Describe Mips Conditional Moves --*- tablegen -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This is the Conditional Moves implementation. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Conditional moves: 15 // These instructions are expanded in 16 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have 17 // conditional move instructions. 18 // cond:int, data:int 19 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 20 InstrItinClass Itin> : 21 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F), 22 !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR> { 23 let Constraints = "$F = $rd"; 24 } 25 26 // cond:int, data:float 27 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC, 28 InstrItinClass Itin> : 29 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), 30 !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> { 31 let Constraints = "$F = $fd"; 32 } 33 34 // cond:float, data:int 35 class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 36 SDPatternOperator OpNode = null_frag> : 37 InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F), 38 !strconcat(opstr, "\t$rd, $rs, $fcc"), 39 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))], 40 Itin, FrmFR> { 41 let Constraints = "$F = $rd"; 42 } 43 44 // cond:float, data:float 45 class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 46 SDPatternOperator OpNode = null_frag> : 47 InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F), 48 !strconcat(opstr, "\t$fd, $fs, $fcc"), 49 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))], 50 Itin, FrmFR> { 51 let Constraints = "$F = $fd"; 52 } 53 54 // select patterns 55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC, 56 Instruction MOVZInst, Instruction SLTOp, 57 Instruction SLTuOp, Instruction SLTiOp, 58 Instruction SLTiuOp> { 59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>; 63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F), 64 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, immSExt16:$rhs), DRC:$F)>; 65 def : MipsPat<(select (i32 (setuge CRC:$lh, immSExt16:$rh)), DRC:$T, DRC:$F), 66 (MOVZInst DRC:$T, (SLTiuOp CRC:$lh, immSExt16:$rh), DRC:$F)>; 67 def : MipsPat<(select (i32 (setle CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 68 (MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 69 def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 70 (MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>; 71 def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)), 72 DRC:$T, DRC:$F), 73 (MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>; 74 def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)), 75 DRC:$T, DRC:$F), 76 (MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)), 77 DRC:$F)>; 78 } 79 80 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC, 81 Instruction MOVZInst, Instruction XOROp> { 82 def : MipsPat<(select (i32 (seteq CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 83 (MOVZInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 84 def : MipsPat<(select (i32 (seteq CRC:$lhs, 0)), DRC:$T, DRC:$F), 85 (MOVZInst DRC:$T, CRC:$lhs, DRC:$F)>; 86 } 87 88 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC, 89 Instruction MOVZInst, Instruction XORiOp> { 90 def : MipsPat< 91 (select (i32 (seteq CRC:$lhs, immZExt16:$uimm16)), DRC:$T, DRC:$F), 92 (MOVZInst DRC:$T, (XORiOp CRC:$lhs, immZExt16:$uimm16), DRC:$F)>; 93 } 94 95 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst, 96 Instruction XOROp> { 97 def : MipsPat<(select (i32 (setne CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F), 98 (MOVNInst DRC:$T, (XOROp CRC:$lhs, CRC:$rhs), DRC:$F)>; 99 def : MipsPat<(select CRC:$cond, DRC:$T, DRC:$F), 100 (MOVNInst DRC:$T, CRC:$cond, DRC:$F)>; 101 def : MipsPat<(select (i32 (setne CRC:$lhs, 0)),DRC:$T, DRC:$F), 102 (MOVNInst DRC:$T, CRC:$lhs, DRC:$F)>; 103 } 104 105 // Instantiation of instructions. 106 def MOVZ_I_I : CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>, 107 ADD_FM<0, 0xa>; 108 109 let Predicates = [HasStdEnc], isCodeGenOnly = 1 in { 110 def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, 111 NoItinerary>, ADD_FM<0, 0xa>; 112 def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, 113 NoItinerary>, ADD_FM<0, 0xa>; 114 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, 115 NoItinerary>, ADD_FM<0, 0xa>; 116 } 117 118 def MOVN_I_I : CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, 119 NoItinerary>, ADD_FM<0, 0xb>; 120 121 let Predicates = [HasStdEnc], isCodeGenOnly = 1 in { 122 def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, 123 NoItinerary>, ADD_FM<0, 0xb>; 124 def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, 125 NoItinerary>, ADD_FM<0, 0xb>; 126 def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, 127 NoItinerary>, ADD_FM<0, 0xb>; 128 } 129 130 def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32RegsOpnd, IIFmove>, 131 CMov_I_F_FM<18, 16>; 132 133 let isCodeGenOnly = 1 in 134 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32RegsOpnd, IIFmove>, 135 CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>; 136 137 def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32RegsOpnd, IIFmove>, 138 CMov_I_F_FM<19, 16>; 139 140 let isCodeGenOnly = 1 in 141 def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32RegsOpnd, IIFmove>, 142 CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>; 143 144 let Predicates = [NotFP64bit, HasStdEnc] in { 145 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64RegsOpnd, IIFmove>, 146 CMov_I_F_FM<18, 17>; 147 def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64RegsOpnd, IIFmove>, 148 CMov_I_F_FM<19, 17>; 149 } 150 151 let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in { 152 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64RegsOpnd, IIFmove>, 153 CMov_I_F_FM<18, 17>; 154 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64RegsOpnd, 155 IIFmove>, CMov_I_F_FM<18, 17>; 156 def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64RegsOpnd, IIFmove>, 157 CMov_I_F_FM<19, 17>; 158 def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64RegsOpnd, 159 IIFmove>, CMov_I_F_FM<19, 17>; 160 } 161 162 def MOVT_I : CMov_F_I_FT<"movt", GPR32Opnd, IIArith, MipsCMovFP_T>, 163 CMov_F_I_FM<1>; 164 165 let isCodeGenOnly = 1 in 166 def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, IIArith, MipsCMovFP_T>, 167 CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>; 168 169 def MOVF_I : CMov_F_I_FT<"movf", GPR32Opnd, IIArith, MipsCMovFP_F>, 170 CMov_F_I_FM<0>; 171 172 let isCodeGenOnly = 1 in 173 def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, IIArith, MipsCMovFP_F>, 174 CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>; 175 176 def MOVT_S : CMov_F_F_FT<"movt.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_T>, 177 CMov_F_F_FM<16, 1>; 178 def MOVF_S : CMov_F_F_FT<"movf.s", FGR32RegsOpnd, IIFmove, MipsCMovFP_F>, 179 CMov_F_F_FM<16, 0>; 180 181 let Predicates = [NotFP64bit, HasStdEnc] in { 182 def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_T>, 183 CMov_F_F_FM<17, 1>; 184 def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64RegsOpnd, IIFmove, MipsCMovFP_F>, 185 CMov_F_F_FM<17, 0>; 186 } 187 let Predicates = [IsFP64bit, HasStdEnc], isCodeGenOnly = 1 in { 188 def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_T>, 189 CMov_F_F_FM<17, 1>; 190 def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64RegsOpnd, IIFmove, MipsCMovFP_F>, 191 CMov_F_F_FM<17, 0>; 192 } 193 194 // Instantiation of conditional move patterns. 195 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>; 196 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>; 197 defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>; 198 let Predicates = [HasMips64, HasStdEnc] in { 199 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>; 200 defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, 201 SLTiu64>; 202 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, 203 SLTiu64>; 204 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>; 205 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>; 206 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>; 207 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>; 208 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>; 209 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>; 210 } 211 212 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>; 213 let Predicates = [HasMips64, HasStdEnc] in { 214 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>; 215 defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>; 216 defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>; 217 } 218 219 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>; 220 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>; 221 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>; 222 let Predicates = [HasMips64, HasStdEnc] in { 223 defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, 224 SLTiu64>; 225 defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>; 226 defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>; 227 } 228 229 let Predicates = [NotFP64bit, HasStdEnc] in { 230 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>; 231 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>; 232 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>; 233 } 234 let Predicates = [IsFP64bit, HasStdEnc] in { 235 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>; 236 defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, 237 SLTiu64>; 238 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>; 239 defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>; 240 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>; 241 defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>; 242 } 243
