1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the PowerPC 64-bit instructions. These patterns are used 11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // 64-bit operands. 17 // 18 def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22 } 23 def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27 } 28 def s17imm64 : Operand<i64> { 29 // This operand type is used for addis/lis to allow the assembler parser 30 // to accept immediates in the range -65536..65535 for compatibility with 31 // the GNU assembler. The operand is treated as 16-bit otherwise. 32 let PrintMethod = "printS16ImmOperand"; 33 let EncoderMethod = "getImm16Encoding"; 34 let ParserMatchClass = PPCS17ImmAsmOperand; 35 } 36 def tocentry : Operand<iPTR> { 37 let MIOperandInfo = (ops i64imm:$imm); 38 } 39 def PPCTLSRegOperand : AsmOperandClass { 40 let Name = "TLSReg"; let PredicateMethod = "isTLSReg"; 41 let RenderMethod = "addTLSRegOperands"; 42 } 43 def tlsreg : Operand<i64> { 44 let EncoderMethod = "getTLSRegEncoding"; 45 let ParserMatchClass = PPCTLSRegOperand; 46 } 47 def tlsgd : Operand<i64> {} 48 def tlscall : Operand<i64> { 49 let PrintMethod = "printTLSCall"; 50 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 51 let EncoderMethod = "getTLSCallEncoding"; 52 } 53 54 //===----------------------------------------------------------------------===// 55 // 64-bit transformation functions. 56 // 57 58 def SHL64 : SDNodeXForm<imm, [{ 59 // Transformation function: 63 - imm 60 return getI32Imm(63 - N->getZExtValue()); 61 }]>; 62 63 def SRL64 : SDNodeXForm<imm, [{ 64 // Transformation function: 64 - imm 65 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 66 }]>; 67 68 def HI32_48 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 71 }]>; 72 73 def HI48_64 : SDNodeXForm<imm, [{ 74 // Transformation function: shift the immediate value down into the low bits. 75 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 76 }]>; 77 78 79 //===----------------------------------------------------------------------===// 80 // Calls. 81 // 82 83 let Interpretation64Bit = 1 in { 84 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 85 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 86 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 87 Requires<[In64BitMode]>; 88 89 let isCodeGenOnly = 1 in 90 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 91 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>, 92 Requires<[In64BitMode]>; 93 } 94 } 95 96 let Defs = [LR8] in 97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 98 PPC970_Unit_BRU; 99 100 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 101 let Defs = [CTR8], Uses = [CTR8] in { 102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 103 "bdz $dst">; 104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 105 "bdnz $dst">; 106 } 107 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 110 "bdzlr", BrB, []>; 111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 112 "bdnzlr", BrB, []>; 113 } 114 } 115 116 117 118 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 119 // Convenient aliases for call instructions 120 let Uses = [RM] in { 121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 122 "bl $func", BrB, []>; // See Pat patterns below. 123 124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 125 "bl $func", BrB, []>; 126 127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 128 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>; 129 } 130 let Uses = [RM], isCodeGenOnly = 1 in { 131 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 132 (outs), (ins calltarget:$func), 133 "bl $func\n\tnop", BrB, []>; 134 135 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 136 (outs), (ins tlscall:$func), 137 "bl $func\n\tnop", BrB, []>; 138 139 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 140 (outs), (ins abscalltarget:$func), 141 "bla $func\n\tnop", BrB, 142 [(PPCcall_nop (i64 imm:$func))]>; 143 } 144 let Uses = [CTR8, RM] in { 145 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 146 "bctrl", BrB, [(PPCbctrl)]>, 147 Requires<[In64BitMode]>; 148 149 let isCodeGenOnly = 1 in 150 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 151 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>, 152 Requires<[In64BitMode]>; 153 } 154 } 155 } // Interpretation64Bit 156 157 // Calls 158 def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 159 (BL8 tglobaladdr:$dst)>; 160 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 161 (BL8_NOP tglobaladdr:$dst)>; 162 163 def : Pat<(PPCcall (i64 texternalsym:$dst)), 164 (BL8 texternalsym:$dst)>; 165 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 166 (BL8_NOP texternalsym:$dst)>; 167 168 // Atomic operations 169 let usesCustomInserter = 1 in { 170 let Defs = [CR0] in { 171 def ATOMIC_LOAD_ADD_I64 : Pseudo< 172 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 173 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 174 def ATOMIC_LOAD_SUB_I64 : Pseudo< 175 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 176 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 177 def ATOMIC_LOAD_OR_I64 : Pseudo< 178 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 179 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 180 def ATOMIC_LOAD_XOR_I64 : Pseudo< 181 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 182 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 183 def ATOMIC_LOAD_AND_I64 : Pseudo< 184 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 185 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 186 def ATOMIC_LOAD_NAND_I64 : Pseudo< 187 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 188 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 189 190 def ATOMIC_CMP_SWAP_I64 : Pseudo< 191 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 192 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 193 194 def ATOMIC_SWAP_I64 : Pseudo< 195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 196 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 197 } 198 } 199 200 // Instructions to support atomic operations 201 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 202 "ldarx $rD, $ptr", LdStLDARX, 203 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 204 205 let Defs = [CR0] in 206 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 207 "stdcx. $rS, $dst", LdStSTDCX, 208 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 209 isDOT; 210 211 let Interpretation64Bit = 1 in { 212 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 213 def TCRETURNdi8 :Pseudo< (outs), 214 (ins calltarget:$dst, i32imm:$offset), 215 "#TC_RETURNd8 $dst $offset", 216 []>; 217 218 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 219 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 220 "#TC_RETURNa8 $func $offset", 221 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 222 223 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 224 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 225 "#TC_RETURNr8 $dst $offset", 226 []>; 227 228 let isCodeGenOnly = 1 in { 229 230 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 231 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 232 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 233 Requires<[In64BitMode]>; 234 235 236 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 237 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 238 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 239 "b $dst", BrB, 240 []>; 241 242 243 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 244 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 245 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 246 "ba $dst", BrB, 247 []>; 248 249 } 250 } // Interpretation64Bit 251 252 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 253 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 254 255 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 256 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 257 258 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 259 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 260 261 262 // 64-bit CR instructions 263 let Interpretation64Bit = 1 in { 264 let neverHasSideEffects = 1 in { 265 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), 266 "mtocrf $FXM, $ST", BrMCRX>, 267 PPC970_DGroup_First, PPC970_Unit_CRU; 268 269 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), 270 "mtcrf $FXM, $rS", BrMCRX>, 271 PPC970_MicroCode, PPC970_Unit_CRU; 272 273 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 274 "mfocrf $rT, $FXM", SprMFCR>, 275 PPC970_DGroup_First, PPC970_Unit_CRU; 276 277 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 278 "mfcr $rT", SprMFCR>, 279 PPC970_MicroCode, PPC970_Unit_CRU; 280 } // neverHasSideEffects = 1 281 282 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 283 let Defs = [CTR8] in 284 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 285 "#EH_SJLJ_SETJMP64", 286 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 287 Requires<[In64BitMode]>; 288 let isTerminator = 1 in 289 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 290 "#EH_SJLJ_LONGJMP64", 291 [(PPCeh_sjlj_longjmp addr:$buf)]>, 292 Requires<[In64BitMode]>; 293 } 294 295 //===----------------------------------------------------------------------===// 296 // 64-bit SPR manipulation instrs. 297 298 let Uses = [CTR8] in { 299 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 300 "mfctr $rT", SprMFSPR>, 301 PPC970_DGroup_First, PPC970_Unit_FXU; 302 } 303 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 304 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 305 "mtctr $rS", SprMTSPR>, 306 PPC970_DGroup_First, PPC970_Unit_FXU; 307 } 308 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in { 309 let Pattern = [(int_ppc_mtctr i64:$rS)] in 310 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 311 "mtctr $rS", SprMTSPR>, 312 PPC970_DGroup_First, PPC970_Unit_FXU; 313 } 314 315 let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in 316 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 317 "mfspr $rT, 268", SprMFTB>, 318 PPC970_DGroup_First, PPC970_Unit_FXU; 319 // Note that encoding mftb using mfspr is now the preferred form, 320 // and has been since at least ISA v2.03. The mftb instruction has 321 // now been phased out. Using mfspr, however, is known not to work on 322 // the POWER3. 323 324 let Defs = [X1], Uses = [X1] in 325 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 326 [(set i64:$result, 327 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 328 329 let Defs = [LR8] in { 330 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 331 "mtlr $rS", SprMTSPR>, 332 PPC970_DGroup_First, PPC970_Unit_FXU; 333 } 334 let Uses = [LR8] in { 335 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 336 "mflr $rT", SprMFSPR>, 337 PPC970_DGroup_First, PPC970_Unit_FXU; 338 } 339 } // Interpretation64Bit 340 341 //===----------------------------------------------------------------------===// 342 // Fixed point instructions. 343 // 344 345 let PPC970_Unit = 1 in { // FXU Operations. 346 let Interpretation64Bit = 1 in { 347 let neverHasSideEffects = 1 in { 348 349 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 350 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 351 "li $rD, $imm", IntSimple, 352 [(set i64:$rD, imm64SExt16:$imm)]>; 353 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 354 "lis $rD, $imm", IntSimple, 355 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 356 } 357 358 // Logical ops. 359 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 360 "nand", "$rA, $rS, $rB", IntSimple, 361 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 362 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 363 "and", "$rA, $rS, $rB", IntSimple, 364 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 365 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 366 "andc", "$rA, $rS, $rB", IntSimple, 367 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 368 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 369 "or", "$rA, $rS, $rB", IntSimple, 370 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 371 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 372 "nor", "$rA, $rS, $rB", IntSimple, 373 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 374 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 375 "orc", "$rA, $rS, $rB", IntSimple, 376 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 377 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 378 "eqv", "$rA, $rS, $rB", IntSimple, 379 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 380 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 381 "xor", "$rA, $rS, $rB", IntSimple, 382 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 383 384 // Logical ops with immediate. 385 let Defs = [CR0] in { 386 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 387 "andi. $dst, $src1, $src2", IntGeneral, 388 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 389 isDOT; 390 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 391 "andis. $dst, $src1, $src2", IntGeneral, 392 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 393 isDOT; 394 } 395 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 396 "ori $dst, $src1, $src2", IntSimple, 397 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 398 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 399 "oris $dst, $src1, $src2", IntSimple, 400 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 401 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 402 "xori $dst, $src1, $src2", IntSimple, 403 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 404 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 405 "xoris $dst, $src1, $src2", IntSimple, 406 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 407 408 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 409 "add", "$rT, $rA, $rB", IntSimple, 410 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 411 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 412 // initial-exec thread-local storage model. 413 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 414 "add $rT, $rA, $rB", IntSimple, 415 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 416 417 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 418 "addc", "$rT, $rA, $rB", IntGeneral, 419 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 420 PPC970_DGroup_Cracked; 421 let Defs = [CARRY] in 422 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 423 "addic $rD, $rA, $imm", IntGeneral, 424 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 425 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 426 "addi $rD, $rA, $imm", IntSimple, 427 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 428 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 429 "addis $rD, $rA, $imm", IntSimple, 430 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 431 432 let Defs = [CARRY] in { 433 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 434 "subfic $rD, $rA, $imm", IntGeneral, 435 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 436 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 437 "subfc", "$rT, $rA, $rB", IntGeneral, 438 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 439 PPC970_DGroup_Cracked; 440 } 441 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 442 "subf", "$rT, $rA, $rB", IntGeneral, 443 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 444 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 445 "neg", "$rT, $rA", IntSimple, 446 [(set i64:$rT, (ineg i64:$rA))]>; 447 let Uses = [CARRY] in { 448 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 449 "adde", "$rT, $rA, $rB", IntGeneral, 450 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 451 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 452 "addme", "$rT, $rA", IntGeneral, 453 [(set i64:$rT, (adde i64:$rA, -1))]>; 454 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 455 "addze", "$rT, $rA", IntGeneral, 456 [(set i64:$rT, (adde i64:$rA, 0))]>; 457 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 458 "subfe", "$rT, $rA, $rB", IntGeneral, 459 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 460 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 461 "subfme", "$rT, $rA", IntGeneral, 462 [(set i64:$rT, (sube -1, i64:$rA))]>; 463 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 464 "subfze", "$rT, $rA", IntGeneral, 465 [(set i64:$rT, (sube 0, i64:$rA))]>; 466 } 467 468 469 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 470 "mulhd", "$rT, $rA, $rB", IntMulHW, 471 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 472 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 473 "mulhdu", "$rT, $rA, $rB", IntMulHWU, 474 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 475 } 476 } // Interpretation64Bit 477 478 let isCompare = 1, neverHasSideEffects = 1 in { 479 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 480 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 481 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 482 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 483 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm), 484 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 485 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2), 486 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 487 } 488 489 let neverHasSideEffects = 1 in { 490 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 491 "sld", "$rA, $rS, $rB", IntRotateD, 492 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 493 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 494 "srd", "$rA, $rS, $rB", IntRotateD, 495 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 496 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 497 "srad", "$rA, $rS, $rB", IntRotateD, 498 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 499 500 let Interpretation64Bit = 1 in { 501 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 502 "extsb", "$rA, $rS", IntSimple, 503 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 504 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 505 "extsh", "$rA, $rS", IntSimple, 506 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 507 } // Interpretation64Bit 508 509 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 510 "extsw", "$rA, $rS", IntSimple, 511 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 512 let Interpretation64Bit = 1 in 513 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 514 "extsw", "$rA, $rS", IntSimple, 515 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 516 517 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 518 "sradi", "$rA, $rS, $SH", IntRotateDI, 519 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 520 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 521 "cntlzd", "$rA, $rS", IntGeneral, 522 [(set i64:$rA, (ctlz i64:$rS))]>; 523 defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 524 "popcntd", "$rA, $rS", IntGeneral, 525 [(set i64:$rA, (ctpop i64:$rS))]>; 526 527 // popcntw also does a population count on the high 32 bits (storing the 528 // results in the high 32-bits of the output). We'll ignore that here (which is 529 // safe because we never separately use the high part of the 64-bit registers). 530 defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS), 531 "popcntw", "$rA, $rS", IntGeneral, 532 [(set i32:$rA, (ctpop i32:$rS))]>; 533 534 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 535 "divd", "$rT, $rA, $rB", IntDivD, 536 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 537 PPC970_DGroup_First, PPC970_DGroup_Cracked; 538 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 539 "divdu", "$rT, $rA, $rB", IntDivD, 540 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 541 PPC970_DGroup_First, PPC970_DGroup_Cracked; 542 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 543 "mulld", "$rT, $rA, $rB", IntMulHD, 544 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 545 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 546 "mulli $rD, $rA, $imm", IntMulLI, 547 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; 548 } 549 550 let neverHasSideEffects = 1 in { 551 let isCommutable = 1 in { 552 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 553 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 554 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI, 555 []>, isPPC64, RegConstraint<"$rSi = $rA">, 556 NoEncode<"$rSi">; 557 } 558 559 // Rotate instructions. 560 defm RLDCL : MDSForm_1r<30, 8, 561 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 562 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD, 563 []>, isPPC64; 564 defm RLDCR : MDSForm_1r<30, 9, 565 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 566 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD, 567 []>, isPPC64; 568 defm RLDICL : MDForm_1r<30, 0, 569 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 570 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI, 571 []>, isPPC64; 572 defm RLDICR : MDForm_1r<30, 1, 573 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 574 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI, 575 []>, isPPC64; 576 defm RLDIC : MDForm_1r<30, 2, 577 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 578 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI, 579 []>, isPPC64; 580 581 let Interpretation64Bit = 1 in { 582 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 583 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 584 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral, 585 []>; 586 587 let isSelect = 1 in 588 def ISEL8 : AForm_4<31, 15, 589 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 590 "isel $rT, $rA, $rB, $cond", IntGeneral, 591 []>; 592 } // Interpretation64Bit 593 } // neverHasSideEffects = 1 594 } // End FXU Operations. 595 596 597 //===----------------------------------------------------------------------===// 598 // Load/Store instructions. 599 // 600 601 602 // Sign extending loads. 603 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 604 let Interpretation64Bit = 1 in 605 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 606 "lha $rD, $src", LdStLHA, 607 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 608 PPC970_DGroup_Cracked; 609 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 610 "lwa $rD, $src", LdStLWA, 611 [(set i64:$rD, 612 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 613 PPC970_DGroup_Cracked; 614 let Interpretation64Bit = 1 in 615 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 616 "lhax $rD, $src", LdStLHA, 617 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 618 PPC970_DGroup_Cracked; 619 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 620 "lwax $rD, $src", LdStLHA, 621 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 622 PPC970_DGroup_Cracked; 623 624 // Update forms. 625 let mayLoad = 1, neverHasSideEffects = 1 in { 626 let Interpretation64Bit = 1 in 627 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 628 (ins memri:$addr), 629 "lhau $rD, $addr", LdStLHAU, 630 []>, RegConstraint<"$addr.reg = $ea_result">, 631 NoEncode<"$ea_result">; 632 // NO LWAU! 633 634 let Interpretation64Bit = 1 in 635 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 636 (ins memrr:$addr), 637 "lhaux $rD, $addr", LdStLHAU, 638 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 639 NoEncode<"$ea_result">; 640 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 641 (ins memrr:$addr), 642 "lwaux $rD, $addr", LdStLHAU, 643 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 644 NoEncode<"$ea_result">, isPPC64; 645 } 646 } 647 648 let Interpretation64Bit = 1 in { 649 // Zero extending loads. 650 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 651 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 652 "lbz $rD, $src", LdStLoad, 653 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 654 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 655 "lhz $rD, $src", LdStLoad, 656 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 657 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 658 "lwz $rD, $src", LdStLoad, 659 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 660 661 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 662 "lbzx $rD, $src", LdStLoad, 663 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 664 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 665 "lhzx $rD, $src", LdStLoad, 666 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 667 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 668 "lwzx $rD, $src", LdStLoad, 669 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 670 671 672 // Update forms. 673 let mayLoad = 1, neverHasSideEffects = 1 in { 674 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 675 "lbzu $rD, $addr", LdStLoadUpd, 676 []>, RegConstraint<"$addr.reg = $ea_result">, 677 NoEncode<"$ea_result">; 678 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 679 "lhzu $rD, $addr", LdStLoadUpd, 680 []>, RegConstraint<"$addr.reg = $ea_result">, 681 NoEncode<"$ea_result">; 682 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 683 "lwzu $rD, $addr", LdStLoadUpd, 684 []>, RegConstraint<"$addr.reg = $ea_result">, 685 NoEncode<"$ea_result">; 686 687 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 688 (ins memrr:$addr), 689 "lbzux $rD, $addr", LdStLoadUpd, 690 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 691 NoEncode<"$ea_result">; 692 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 693 (ins memrr:$addr), 694 "lhzux $rD, $addr", LdStLoadUpd, 695 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 696 NoEncode<"$ea_result">; 697 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 698 (ins memrr:$addr), 699 "lwzux $rD, $addr", LdStLoadUpd, 700 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 701 NoEncode<"$ea_result">; 702 } 703 } 704 } // Interpretation64Bit 705 706 707 // Full 8-byte loads. 708 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 709 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 710 "ld $rD, $src", LdStLD, 711 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 712 // The following three definitions are selected for small code model only. 713 // Otherwise, we need to create two instructions to form a 32-bit offset, 714 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 715 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 716 "#LDtoc", 717 [(set i64:$rD, 718 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 719 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 720 "#LDtocJTI", 721 [(set i64:$rD, 722 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 723 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 724 "#LDtocCPT", 725 [(set i64:$rD, 726 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 727 728 let hasSideEffects = 1, isCodeGenOnly = 1 in { 729 let RST = 2, DS = 2 in 730 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), 731 "ld 2, 8($reg)", LdStLD, 732 [(PPCload_toc i64:$reg)]>, isPPC64; 733 734 let RST = 2, DS = 10, RA = 1 in 735 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 736 "ld 2, 40(1)", LdStLD, 737 [(PPCtoc_restore)]>, isPPC64; 738 } 739 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 740 "ldx $rD, $src", LdStLD, 741 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 742 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 743 "ldbrx $rD, $src", LdStLoad, 744 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 745 746 let mayLoad = 1, neverHasSideEffects = 1 in { 747 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 748 "ldu $rD, $addr", LdStLDU, 749 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 750 NoEncode<"$ea_result">; 751 752 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 753 (ins memrr:$addr), 754 "ldux $rD, $addr", LdStLDU, 755 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 756 NoEncode<"$ea_result">, isPPC64; 757 } 758 } 759 760 def : Pat<(PPCload ixaddr:$src), 761 (LD ixaddr:$src)>; 762 def : Pat<(PPCload xaddr:$src), 763 (LDX xaddr:$src)>; 764 765 // Support for medium and large code model. 766 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 767 "#ADDIStocHA", 768 [(set i64:$rD, 769 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 770 isPPC64; 771 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 772 "#LDtocL", 773 [(set i64:$rD, 774 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 775 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 776 "#ADDItocL", 777 [(set i64:$rD, 778 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 779 780 // Support for thread-local storage. 781 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 782 "#ADDISgotTprelHA", 783 [(set i64:$rD, 784 (PPCaddisGotTprelHA i64:$reg, 785 tglobaltlsaddr:$disp))]>, 786 isPPC64; 787 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 788 "#LDgotTprelL", 789 [(set i64:$rD, 790 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 791 isPPC64; 792 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 793 (ADD8TLS $in, tglobaltlsaddr:$g)>; 794 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 795 "#ADDIStlsgdHA", 796 [(set i64:$rD, 797 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 798 isPPC64; 799 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 800 "#ADDItlsgdL", 801 [(set i64:$rD, 802 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 803 isPPC64; 804 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 805 "#GETtlsADDR", 806 [(set i64:$rD, 807 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 808 isPPC64; 809 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 810 "#ADDIStlsldHA", 811 [(set i64:$rD, 812 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 813 isPPC64; 814 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 815 "#ADDItlsldL", 816 [(set i64:$rD, 817 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 818 isPPC64; 819 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 820 "#GETtlsldADDR", 821 [(set i64:$rD, 822 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 823 isPPC64; 824 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 825 "#ADDISdtprelHA", 826 [(set i64:$rD, 827 (PPCaddisDtprelHA i64:$reg, 828 tglobaltlsaddr:$disp))]>, 829 isPPC64; 830 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 831 "#ADDIdtprelL", 832 [(set i64:$rD, 833 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 834 isPPC64; 835 836 let PPC970_Unit = 2 in { 837 let Interpretation64Bit = 1 in { 838 // Truncating stores. 839 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 840 "stb $rS, $src", LdStStore, 841 [(truncstorei8 i64:$rS, iaddr:$src)]>; 842 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 843 "sth $rS, $src", LdStStore, 844 [(truncstorei16 i64:$rS, iaddr:$src)]>; 845 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 846 "stw $rS, $src", LdStStore, 847 [(truncstorei32 i64:$rS, iaddr:$src)]>; 848 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 849 "stbx $rS, $dst", LdStStore, 850 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 851 PPC970_DGroup_Cracked; 852 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 853 "sthx $rS, $dst", LdStStore, 854 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 855 PPC970_DGroup_Cracked; 856 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 857 "stwx $rS, $dst", LdStStore, 858 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 859 PPC970_DGroup_Cracked; 860 } // Interpretation64Bit 861 862 // Normal 8-byte stores. 863 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 864 "std $rS, $dst", LdStSTD, 865 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 866 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 867 "stdx $rS, $dst", LdStSTD, 868 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 869 PPC970_DGroup_Cracked; 870 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 871 "stdbrx $rS, $dst", LdStStore, 872 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 873 PPC970_DGroup_Cracked; 874 } 875 876 // Stores with Update (pre-inc). 877 let PPC970_Unit = 2, mayStore = 1 in { 878 let Interpretation64Bit = 1 in { 879 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 880 "stbu $rS, $dst", LdStStoreUpd, []>, 881 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 882 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 883 "sthu $rS, $dst", LdStStoreUpd, []>, 884 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 885 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 886 "stwu $rS, $dst", LdStStoreUpd, []>, 887 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 888 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 889 "stdu $rS, $dst", LdStSTDU, []>, 890 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 891 isPPC64; 892 893 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 894 "stbux $rS, $dst", LdStStoreUpd, []>, 895 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 896 PPC970_DGroup_Cracked; 897 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 898 "sthux $rS, $dst", LdStStoreUpd, []>, 899 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 900 PPC970_DGroup_Cracked; 901 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 902 "stwux $rS, $dst", LdStStoreUpd, []>, 903 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 904 PPC970_DGroup_Cracked; 905 } // Interpretation64Bit 906 907 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 908 "stdux $rS, $dst", LdStSTDU, []>, 909 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 910 PPC970_DGroup_Cracked, isPPC64; 911 } 912 913 // Patterns to match the pre-inc stores. We can't put the patterns on 914 // the instruction definitions directly as ISel wants the address base 915 // and offset to be separate operands, not a single complex operand. 916 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 917 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 918 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 919 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 920 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 921 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 922 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 923 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 924 925 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 926 (STBUX8 $rS, $ptrreg, $ptroff)>; 927 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 928 (STHUX8 $rS, $ptrreg, $ptroff)>; 929 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 930 (STWUX8 $rS, $ptrreg, $ptroff)>; 931 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 932 (STDUX $rS, $ptrreg, $ptroff)>; 933 934 935 //===----------------------------------------------------------------------===// 936 // Floating point instructions. 937 // 938 939 940 let PPC970_Unit = 3, neverHasSideEffects = 1, 941 Uses = [RM] in { // FPU Operations. 942 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 943 "fcfid", "$frD, $frB", FPGeneral, 944 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 945 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 946 "fctidz", "$frD, $frB", FPGeneral, 947 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 948 949 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 950 "fcfidu", "$frD, $frB", FPGeneral, 951 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 952 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 953 "fcfids", "$frD, $frB", FPGeneral, 954 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 955 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 956 "fcfidus", "$frD, $frB", FPGeneral, 957 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 958 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 959 "fctiduz", "$frD, $frB", FPGeneral, 960 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 961 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 962 "fctiwuz", "$frD, $frB", FPGeneral, 963 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 964 } 965 966 967 //===----------------------------------------------------------------------===// 968 // Instruction Patterns 969 // 970 971 // Extensions and truncates to/from 32-bit regs. 972 def : Pat<(i64 (zext i32:$in)), 973 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 974 0, 32)>; 975 def : Pat<(i64 (anyext i32:$in)), 976 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 977 def : Pat<(i32 (trunc i64:$in)), 978 (EXTRACT_SUBREG $in, sub_32)>; 979 980 // Extending loads with i64 targets. 981 def : Pat<(zextloadi1 iaddr:$src), 982 (LBZ8 iaddr:$src)>; 983 def : Pat<(zextloadi1 xaddr:$src), 984 (LBZX8 xaddr:$src)>; 985 def : Pat<(extloadi1 iaddr:$src), 986 (LBZ8 iaddr:$src)>; 987 def : Pat<(extloadi1 xaddr:$src), 988 (LBZX8 xaddr:$src)>; 989 def : Pat<(extloadi8 iaddr:$src), 990 (LBZ8 iaddr:$src)>; 991 def : Pat<(extloadi8 xaddr:$src), 992 (LBZX8 xaddr:$src)>; 993 def : Pat<(extloadi16 iaddr:$src), 994 (LHZ8 iaddr:$src)>; 995 def : Pat<(extloadi16 xaddr:$src), 996 (LHZX8 xaddr:$src)>; 997 def : Pat<(extloadi32 iaddr:$src), 998 (LWZ8 iaddr:$src)>; 999 def : Pat<(extloadi32 xaddr:$src), 1000 (LWZX8 xaddr:$src)>; 1001 1002 // Standard shifts. These are represented separately from the real shifts above 1003 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift 1004 // amounts. 1005 def : Pat<(sra i64:$rS, i32:$rB), 1006 (SRAD $rS, $rB)>; 1007 def : Pat<(srl i64:$rS, i32:$rB), 1008 (SRD $rS, $rB)>; 1009 def : Pat<(shl i64:$rS, i32:$rB), 1010 (SLD $rS, $rB)>; 1011 1012 // SHL/SRL 1013 def : Pat<(shl i64:$in, (i32 imm:$imm)), 1014 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1015 def : Pat<(srl i64:$in, (i32 imm:$imm)), 1016 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1017 1018 // ROTL 1019 def : Pat<(rotl i64:$in, i32:$sh), 1020 (RLDCL $in, $sh, 0)>; 1021 def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1022 (RLDICL $in, imm:$imm, 0)>; 1023 1024 // Hi and Lo for Darwin Global Addresses. 1025 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1026 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1027 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1028 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1029 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1030 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1031 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1032 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1033 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1034 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1035 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1036 (ADDI8 $in, tglobaltlsaddr:$g)>; 1037 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1038 (ADDIS8 $in, tglobaladdr:$g)>; 1039 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1040 (ADDIS8 $in, tconstpool:$g)>; 1041 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1042 (ADDIS8 $in, tjumptable:$g)>; 1043 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1044 (ADDIS8 $in, tblockaddress:$g)>; 1045 1046 // Patterns to match r+r indexed loads and stores for 1047 // addresses without at least 4-byte alignment. 1048 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1049 (LWAX xoaddr:$src)>; 1050 def : Pat<(i64 (unaligned4load xoaddr:$src)), 1051 (LDX xoaddr:$src)>; 1052 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1053 (STDX $rS, xoaddr:$dst)>; 1054 1055
