1 //===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the subset of the 32-bit PowerPC instruction set, as used 11 // by the PowerPC instruction selector. 12 // 13 //===----------------------------------------------------------------------===// 14 15 include "PPCInstrFormats.td" 16 17 //===----------------------------------------------------------------------===// 18 // PowerPC specific type constraints. 19 // 20 def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 21 SDTCisVT<0, f64>, SDTCisPtrTy<1> 22 ]>; 23 def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 24 SDTCisVT<0, f64>, SDTCisPtrTy<1> 25 ]>; 26 27 def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 28 def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 29 SDTCisVT<1, i32> ]>; 30 def SDT_PPCvperm : SDTypeProfile<1, 3, [ 31 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 32 ]>; 33 34 def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 36 ]>; 37 38 def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 39 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 40 ]>; 41 42 def SDT_PPClbrx : SDTypeProfile<1, 2, [ 43 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 44 ]>; 45 def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 47 ]>; 48 49 def SDT_PPClarx : SDTypeProfile<1, 1, [ 50 SDTCisInt<0>, SDTCisPtrTy<1> 51 ]>; 52 def SDT_PPCstcx : SDTypeProfile<0, 2, [ 53 SDTCisInt<0>, SDTCisPtrTy<1> 54 ]>; 55 56 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 57 SDTCisPtrTy<0>, SDTCisVT<1, i32> 58 ]>; 59 60 61 //===----------------------------------------------------------------------===// 62 // PowerPC specific DAG Nodes. 63 // 64 65 def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 66 def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 67 68 def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 69 def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 70 def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 71 def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 72 def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 73 def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 74 def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 75 def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 76 def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 77 [SDNPHasChain, SDNPMayStore]>; 78 def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 79 [SDNPHasChain, SDNPMayLoad]>; 80 def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 81 [SDNPHasChain, SDNPMayLoad]>; 82 83 // Extract FPSCR (not modeled at the DAG level). 84 def PPCmffs : SDNode<"PPCISD::MFFS", 85 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, []>; 86 87 // Perform FADD in round-to-zero mode. 88 def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 89 90 91 def PPCfsel : SDNode<"PPCISD::FSEL", 92 // Type constraint for fsel. 93 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 94 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 95 96 def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 97 def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 98 def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, [SDNPMayLoad]>; 99 def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>; 100 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>; 101 102 def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 103 def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 104 [SDNPMayLoad]>; 105 def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 106 def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 107 def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 108 def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 109 def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 110 def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 111 def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 112 def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp, 113 [SDNPHasChain]>; 114 def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 115 116 def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 117 118 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 119 // amounts. These nodes are generated by the multi-precision shift code. 120 def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 121 def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 122 def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 123 124 // These are target-independent nodes, but have target-specific formats. 125 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 126 [SDNPHasChain, SDNPOutGlue]>; 127 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 128 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 129 130 def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 131 def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 133 SDNPVariadic]>; 134 def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 136 SDNPVariadic]>; 137 def PPCload : SDNode<"PPCISD::LOAD", SDTypeProfile<1, 1, []>, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 139 def PPCload_toc : SDNode<"PPCISD::LOAD_TOC", SDTypeProfile<0, 1, []>, 140 [SDNPHasChain, SDNPSideEffect, 141 SDNPInGlue, SDNPOutGlue]>; 142 def PPCtoc_restore : SDNode<"PPCISD::TOC_RESTORE", SDTypeProfile<0, 0, []>, 143 [SDNPHasChain, SDNPSideEffect, 144 SDNPInGlue, SDNPOutGlue]>; 145 def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 147 def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 148 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 149 SDNPVariadic]>; 150 151 def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone, 152 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 153 154 def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 156 157 def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 158 SDTypeProfile<1, 1, [SDTCisInt<0>, 159 SDTCisPtrTy<1>]>, 160 [SDNPHasChain, SDNPSideEffect]>; 161 def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 162 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 163 [SDNPHasChain, SDNPSideEffect]>; 164 165 def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 166 def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 167 [SDNPHasChain, SDNPSideEffect]>; 168 169 def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 170 def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutGlue]>; 171 172 def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 173 [SDNPHasChain, SDNPOptInGlue]>; 174 175 def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 176 [SDNPHasChain, SDNPMayLoad]>; 177 def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 178 [SDNPHasChain, SDNPMayStore]>; 179 180 // Instructions to set/unset CR bit 6 for SVR4 vararg calls 181 def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 182 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 183 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 184 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 185 186 // Instructions to support atomic operations 187 def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx, 188 [SDNPHasChain, SDNPMayLoad]>; 189 def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx, 190 [SDNPHasChain, SDNPMayStore]>; 191 192 // Instructions to support medium and large code model 193 def PPCaddisTocHA : SDNode<"PPCISD::ADDIS_TOC_HA", SDTIntBinOp, []>; 194 def PPCldTocL : SDNode<"PPCISD::LD_TOC_L", SDTIntBinOp, [SDNPMayLoad]>; 195 def PPCaddiTocL : SDNode<"PPCISD::ADDI_TOC_L", SDTIntBinOp, []>; 196 197 198 // Instructions to support dynamic alloca. 199 def SDTDynOp : SDTypeProfile<1, 2, []>; 200 def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 201 202 //===----------------------------------------------------------------------===// 203 // PowerPC specific transformation functions and pattern fragments. 204 // 205 206 def SHL32 : SDNodeXForm<imm, [{ 207 // Transformation function: 31 - imm 208 return getI32Imm(31 - N->getZExtValue()); 209 }]>; 210 211 def SRL32 : SDNodeXForm<imm, [{ 212 // Transformation function: 32 - imm 213 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue()) : getI32Imm(0); 214 }]>; 215 216 def LO16 : SDNodeXForm<imm, [{ 217 // Transformation function: get the low 16 bits. 218 return getI32Imm((unsigned short)N->getZExtValue()); 219 }]>; 220 221 def HI16 : SDNodeXForm<imm, [{ 222 // Transformation function: shift the immediate value down into the low bits. 223 return getI32Imm((unsigned)N->getZExtValue() >> 16); 224 }]>; 225 226 def HA16 : SDNodeXForm<imm, [{ 227 // Transformation function: shift the immediate value down into the low bits. 228 signed int Val = N->getZExtValue(); 229 return getI32Imm((Val - (signed short)Val) >> 16); 230 }]>; 231 def MB : SDNodeXForm<imm, [{ 232 // Transformation function: get the start bit of a mask 233 unsigned mb = 0, me; 234 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 235 return getI32Imm(mb); 236 }]>; 237 238 def ME : SDNodeXForm<imm, [{ 239 // Transformation function: get the end bit of a mask 240 unsigned mb, me = 0; 241 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 242 return getI32Imm(me); 243 }]>; 244 def maskimm32 : PatLeaf<(imm), [{ 245 // maskImm predicate - True if immediate is a run of ones. 246 unsigned mb, me; 247 if (N->getValueType(0) == MVT::i32) 248 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 249 else 250 return false; 251 }]>; 252 253 def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 254 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 255 // sign extended field. Used by instructions like 'addi'. 256 return (int32_t)Imm == (short)Imm; 257 }]>; 258 def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 259 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 260 // sign extended field. Used by instructions like 'addi'. 261 return (int64_t)Imm == (short)Imm; 262 }]>; 263 def immZExt16 : PatLeaf<(imm), [{ 264 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 265 // field. Used by instructions like 'ori'. 266 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 267 }], LO16>; 268 269 // imm16Shifted* - These match immediates where the low 16-bits are zero. There 270 // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 271 // identical in 32-bit mode, but in 64-bit mode, they return true if the 272 // immediate fits into a sign/zero extended 32-bit immediate (with the low bits 273 // clear). 274 def imm16ShiftedZExt : PatLeaf<(imm), [{ 275 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 276 // immediate are set. Used by instructions like 'xoris'. 277 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 278 }], HI16>; 279 280 def imm16ShiftedSExt : PatLeaf<(imm), [{ 281 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 282 // immediate are set. Used by instructions like 'addis'. Identical to 283 // imm16ShiftedZExt in 32-bit mode. 284 if (N->getZExtValue() & 0xFFFF) return false; 285 if (N->getValueType(0) == MVT::i32) 286 return true; 287 // For 64-bit, make sure it is sext right. 288 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 289 }], HI16>; 290 291 // Some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 292 // restricted memrix (4-aligned) constants are alignment sensitive. If these 293 // offsets are hidden behind TOC entries than the values of the lower-order 294 // bits cannot be checked directly. As a result, we need to also incorporate 295 // an alignment check into the relevant patterns. 296 297 def aligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 298 return cast<LoadSDNode>(N)->getAlignment() >= 4; 299 }]>; 300 def aligned4store : PatFrag<(ops node:$val, node:$ptr), 301 (store node:$val, node:$ptr), [{ 302 return cast<StoreSDNode>(N)->getAlignment() >= 4; 303 }]>; 304 def aligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 305 return cast<LoadSDNode>(N)->getAlignment() >= 4; 306 }]>; 307 def aligned4pre_store : PatFrag< 308 (ops node:$val, node:$base, node:$offset), 309 (pre_store node:$val, node:$base, node:$offset), [{ 310 return cast<StoreSDNode>(N)->getAlignment() >= 4; 311 }]>; 312 313 def unaligned4load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 314 return cast<LoadSDNode>(N)->getAlignment() < 4; 315 }]>; 316 def unaligned4store : PatFrag<(ops node:$val, node:$ptr), 317 (store node:$val, node:$ptr), [{ 318 return cast<StoreSDNode>(N)->getAlignment() < 4; 319 }]>; 320 def unaligned4sextloadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 321 return cast<LoadSDNode>(N)->getAlignment() < 4; 322 }]>; 323 324 //===----------------------------------------------------------------------===// 325 // PowerPC Flag Definitions. 326 327 class isPPC64 { bit PPC64 = 1; } 328 class isDOT { bit RC = 1; } 329 330 class RegConstraint<string C> { 331 string Constraints = C; 332 } 333 class NoEncode<string E> { 334 string DisableEncoding = E; 335 } 336 337 338 //===----------------------------------------------------------------------===// 339 // PowerPC Operand Definitions. 340 341 // In the default PowerPC assembler syntax, registers are specified simply 342 // by number, so they cannot be distinguished from immediate values (without 343 // looking at the opcode). This means that the default operand matching logic 344 // for the asm parser does not work, and we need to specify custom matchers. 345 // Since those can only be specified with RegisterOperand classes and not 346 // directly on the RegisterClass, all instructions patterns used by the asm 347 // parser need to use a RegisterOperand (instead of a RegisterClass) for 348 // all their register operands. 349 // For this purpose, we define one RegisterOperand for each RegisterClass, 350 // using the same name as the class, just in lower case. 351 352 def PPCRegGPRCAsmOperand : AsmOperandClass { 353 let Name = "RegGPRC"; let PredicateMethod = "isRegNumber"; 354 } 355 def gprc : RegisterOperand<GPRC> { 356 let ParserMatchClass = PPCRegGPRCAsmOperand; 357 } 358 def PPCRegG8RCAsmOperand : AsmOperandClass { 359 let Name = "RegG8RC"; let PredicateMethod = "isRegNumber"; 360 } 361 def g8rc : RegisterOperand<G8RC> { 362 let ParserMatchClass = PPCRegG8RCAsmOperand; 363 } 364 def PPCRegGPRCNoR0AsmOperand : AsmOperandClass { 365 let Name = "RegGPRCNoR0"; let PredicateMethod = "isRegNumber"; 366 } 367 def gprc_nor0 : RegisterOperand<GPRC_NOR0> { 368 let ParserMatchClass = PPCRegGPRCNoR0AsmOperand; 369 } 370 def PPCRegG8RCNoX0AsmOperand : AsmOperandClass { 371 let Name = "RegG8RCNoX0"; let PredicateMethod = "isRegNumber"; 372 } 373 def g8rc_nox0 : RegisterOperand<G8RC_NOX0> { 374 let ParserMatchClass = PPCRegG8RCNoX0AsmOperand; 375 } 376 def PPCRegF8RCAsmOperand : AsmOperandClass { 377 let Name = "RegF8RC"; let PredicateMethod = "isRegNumber"; 378 } 379 def f8rc : RegisterOperand<F8RC> { 380 let ParserMatchClass = PPCRegF8RCAsmOperand; 381 } 382 def PPCRegF4RCAsmOperand : AsmOperandClass { 383 let Name = "RegF4RC"; let PredicateMethod = "isRegNumber"; 384 } 385 def f4rc : RegisterOperand<F4RC> { 386 let ParserMatchClass = PPCRegF4RCAsmOperand; 387 } 388 def PPCRegVRRCAsmOperand : AsmOperandClass { 389 let Name = "RegVRRC"; let PredicateMethod = "isRegNumber"; 390 } 391 def vrrc : RegisterOperand<VRRC> { 392 let ParserMatchClass = PPCRegVRRCAsmOperand; 393 } 394 def PPCRegCRBITRCAsmOperand : AsmOperandClass { 395 let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; 396 } 397 def crbitrc : RegisterOperand<CRBITRC> { 398 let ParserMatchClass = PPCRegCRBITRCAsmOperand; 399 } 400 def PPCRegCRRCAsmOperand : AsmOperandClass { 401 let Name = "RegCRRC"; let PredicateMethod = "isCCRegNumber"; 402 } 403 def crrc : RegisterOperand<CRRC> { 404 let ParserMatchClass = PPCRegCRRCAsmOperand; 405 } 406 407 def PPCS5ImmAsmOperand : AsmOperandClass { 408 let Name = "S5Imm"; let PredicateMethod = "isS5Imm"; 409 let RenderMethod = "addImmOperands"; 410 } 411 def s5imm : Operand<i32> { 412 let PrintMethod = "printS5ImmOperand"; 413 let ParserMatchClass = PPCS5ImmAsmOperand; 414 } 415 def PPCU5ImmAsmOperand : AsmOperandClass { 416 let Name = "U5Imm"; let PredicateMethod = "isU5Imm"; 417 let RenderMethod = "addImmOperands"; 418 } 419 def u5imm : Operand<i32> { 420 let PrintMethod = "printU5ImmOperand"; 421 let ParserMatchClass = PPCU5ImmAsmOperand; 422 } 423 def PPCU6ImmAsmOperand : AsmOperandClass { 424 let Name = "U6Imm"; let PredicateMethod = "isU6Imm"; 425 let RenderMethod = "addImmOperands"; 426 } 427 def u6imm : Operand<i32> { 428 let PrintMethod = "printU6ImmOperand"; 429 let ParserMatchClass = PPCU6ImmAsmOperand; 430 } 431 def PPCS16ImmAsmOperand : AsmOperandClass { 432 let Name = "S16Imm"; let PredicateMethod = "isS16Imm"; 433 let RenderMethod = "addImmOperands"; 434 } 435 def s16imm : Operand<i32> { 436 let PrintMethod = "printS16ImmOperand"; 437 let EncoderMethod = "getImm16Encoding"; 438 let ParserMatchClass = PPCS16ImmAsmOperand; 439 } 440 def PPCU16ImmAsmOperand : AsmOperandClass { 441 let Name = "U16Imm"; let PredicateMethod = "isU16Imm"; 442 let RenderMethod = "addImmOperands"; 443 } 444 def u16imm : Operand<i32> { 445 let PrintMethod = "printU16ImmOperand"; 446 let EncoderMethod = "getImm16Encoding"; 447 let ParserMatchClass = PPCU16ImmAsmOperand; 448 } 449 def PPCS17ImmAsmOperand : AsmOperandClass { 450 let Name = "S17Imm"; let PredicateMethod = "isS17Imm"; 451 let RenderMethod = "addImmOperands"; 452 } 453 def s17imm : Operand<i32> { 454 // This operand type is used for addis/lis to allow the assembler parser 455 // to accept immediates in the range -65536..65535 for compatibility with 456 // the GNU assembler. The operand is treated as 16-bit otherwise. 457 let PrintMethod = "printS16ImmOperand"; 458 let EncoderMethod = "getImm16Encoding"; 459 let ParserMatchClass = PPCS17ImmAsmOperand; 460 } 461 def PPCDirectBrAsmOperand : AsmOperandClass { 462 let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; 463 let RenderMethod = "addBranchTargetOperands"; 464 } 465 def directbrtarget : Operand<OtherVT> { 466 let PrintMethod = "printBranchOperand"; 467 let EncoderMethod = "getDirectBrEncoding"; 468 let ParserMatchClass = PPCDirectBrAsmOperand; 469 } 470 def absdirectbrtarget : Operand<OtherVT> { 471 let PrintMethod = "printAbsBranchOperand"; 472 let EncoderMethod = "getAbsDirectBrEncoding"; 473 let ParserMatchClass = PPCDirectBrAsmOperand; 474 } 475 def PPCCondBrAsmOperand : AsmOperandClass { 476 let Name = "CondBr"; let PredicateMethod = "isCondBr"; 477 let RenderMethod = "addBranchTargetOperands"; 478 } 479 def condbrtarget : Operand<OtherVT> { 480 let PrintMethod = "printBranchOperand"; 481 let EncoderMethod = "getCondBrEncoding"; 482 let ParserMatchClass = PPCCondBrAsmOperand; 483 } 484 def abscondbrtarget : Operand<OtherVT> { 485 let PrintMethod = "printAbsBranchOperand"; 486 let EncoderMethod = "getAbsCondBrEncoding"; 487 let ParserMatchClass = PPCCondBrAsmOperand; 488 } 489 def calltarget : Operand<iPTR> { 490 let PrintMethod = "printBranchOperand"; 491 let EncoderMethod = "getDirectBrEncoding"; 492 let ParserMatchClass = PPCDirectBrAsmOperand; 493 } 494 def abscalltarget : Operand<iPTR> { 495 let PrintMethod = "printAbsBranchOperand"; 496 let EncoderMethod = "getAbsDirectBrEncoding"; 497 let ParserMatchClass = PPCDirectBrAsmOperand; 498 } 499 def PPCCRBitMaskOperand : AsmOperandClass { 500 let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask"; 501 } 502 def crbitm: Operand<i8> { 503 let PrintMethod = "printcrbitm"; 504 let EncoderMethod = "get_crbitm_encoding"; 505 let ParserMatchClass = PPCCRBitMaskOperand; 506 } 507 // Address operands 508 // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). 509 def PPCRegGxRCNoR0Operand : AsmOperandClass { 510 let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; 511 } 512 def ptr_rc_nor0 : Operand<iPTR>, PointerLikeRegClass<1> { 513 let ParserMatchClass = PPCRegGxRCNoR0Operand; 514 } 515 // A version of ptr_rc usable with the asm parser. 516 def PPCRegGxRCOperand : AsmOperandClass { 517 let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; 518 } 519 def ptr_rc_idx : Operand<iPTR>, PointerLikeRegClass<0> { 520 let ParserMatchClass = PPCRegGxRCOperand; 521 } 522 523 def PPCDispRIOperand : AsmOperandClass { 524 let Name = "DispRI"; let PredicateMethod = "isS16Imm"; 525 let RenderMethod = "addImmOperands"; 526 } 527 def dispRI : Operand<iPTR> { 528 let ParserMatchClass = PPCDispRIOperand; 529 } 530 def PPCDispRIXOperand : AsmOperandClass { 531 let Name = "DispRIX"; let PredicateMethod = "isS16ImmX4"; 532 let RenderMethod = "addImmOperands"; 533 } 534 def dispRIX : Operand<iPTR> { 535 let ParserMatchClass = PPCDispRIXOperand; 536 } 537 538 def memri : Operand<iPTR> { 539 let PrintMethod = "printMemRegImm"; 540 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 541 let EncoderMethod = "getMemRIEncoding"; 542 } 543 def memrr : Operand<iPTR> { 544 let PrintMethod = "printMemRegReg"; 545 let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); 546 } 547 def memrix : Operand<iPTR> { // memri where the imm is 4-aligned. 548 let PrintMethod = "printMemRegImm"; 549 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 550 let EncoderMethod = "getMemRIXEncoding"; 551 } 552 553 // A single-register address. This is used with the SjLj 554 // pseudo-instructions. 555 def memr : Operand<iPTR> { 556 let MIOperandInfo = (ops ptr_rc:$ptrreg); 557 } 558 559 // PowerPC Predicate operand. 560 def pred : Operand<OtherVT> { 561 let PrintMethod = "printPredicateOperand"; 562 let MIOperandInfo = (ops i32imm:$bibo, crrc:$reg); 563 } 564 565 // Define PowerPC specific addressing mode. 566 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; 567 def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; 568 def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 569 def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 570 571 // The address in a single register. This is used with the SjLj 572 // pseudo-instructions. 573 def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 574 575 /// This is just the offset part of iaddr, used for preinc. 576 def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 577 578 //===----------------------------------------------------------------------===// 579 // PowerPC Instruction Predicate Definitions. 580 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">; 581 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">; 582 def IsBookE : Predicate<"PPCSubTarget.isBookE()">; 583 584 //===----------------------------------------------------------------------===// 585 // PowerPC Multiclass Definitions. 586 587 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 588 string asmbase, string asmstr, InstrItinClass itin, 589 list<dag> pattern> { 590 let BaseName = asmbase in { 591 def NAME : XForm_6<opcode, xo, OOL, IOL, 592 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 593 pattern>, RecFormRel; 594 let Defs = [CR0] in 595 def o : XForm_6<opcode, xo, OOL, IOL, 596 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 597 []>, isDOT, RecFormRel; 598 } 599 } 600 601 multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 602 string asmbase, string asmstr, InstrItinClass itin, 603 list<dag> pattern> { 604 let BaseName = asmbase in { 605 let Defs = [CARRY] in 606 def NAME : XForm_6<opcode, xo, OOL, IOL, 607 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 608 pattern>, RecFormRel; 609 let Defs = [CARRY, CR0] in 610 def o : XForm_6<opcode, xo, OOL, IOL, 611 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 612 []>, isDOT, RecFormRel; 613 } 614 } 615 616 multiclass XForm_10r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 617 string asmbase, string asmstr, InstrItinClass itin, 618 list<dag> pattern> { 619 let BaseName = asmbase in { 620 def NAME : XForm_10<opcode, xo, OOL, IOL, 621 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 622 pattern>, RecFormRel; 623 let Defs = [CR0] in 624 def o : XForm_10<opcode, xo, OOL, IOL, 625 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 626 []>, isDOT, RecFormRel; 627 } 628 } 629 630 multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 631 string asmbase, string asmstr, InstrItinClass itin, 632 list<dag> pattern> { 633 let BaseName = asmbase in { 634 let Defs = [CARRY] in 635 def NAME : XForm_10<opcode, xo, OOL, IOL, 636 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 637 pattern>, RecFormRel; 638 let Defs = [CARRY, CR0] in 639 def o : XForm_10<opcode, xo, OOL, IOL, 640 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 641 []>, isDOT, RecFormRel; 642 } 643 } 644 645 multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 646 string asmbase, string asmstr, InstrItinClass itin, 647 list<dag> pattern> { 648 let BaseName = asmbase in { 649 def NAME : XForm_11<opcode, xo, OOL, IOL, 650 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 651 pattern>, RecFormRel; 652 let Defs = [CR0] in 653 def o : XForm_11<opcode, xo, OOL, IOL, 654 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 655 []>, isDOT, RecFormRel; 656 } 657 } 658 659 multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 660 string asmbase, string asmstr, InstrItinClass itin, 661 list<dag> pattern> { 662 let BaseName = asmbase in { 663 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 664 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 665 pattern>, RecFormRel; 666 let Defs = [CR0] in 667 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 668 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 669 []>, isDOT, RecFormRel; 670 } 671 } 672 673 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 674 string asmbase, string asmstr, InstrItinClass itin, 675 list<dag> pattern> { 676 let BaseName = asmbase in { 677 let Defs = [CARRY] in 678 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 679 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 680 pattern>, RecFormRel; 681 let Defs = [CARRY, CR0] in 682 def o : XOForm_1<opcode, xo, oe, OOL, IOL, 683 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 684 []>, isDOT, RecFormRel; 685 } 686 } 687 688 multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 689 string asmbase, string asmstr, InstrItinClass itin, 690 list<dag> pattern> { 691 let BaseName = asmbase in { 692 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 693 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 694 pattern>, RecFormRel; 695 let Defs = [CR0] in 696 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 697 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 698 []>, isDOT, RecFormRel; 699 } 700 } 701 702 multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 703 string asmbase, string asmstr, InstrItinClass itin, 704 list<dag> pattern> { 705 let BaseName = asmbase in { 706 let Defs = [CARRY] in 707 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 708 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 709 pattern>, RecFormRel; 710 let Defs = [CARRY, CR0] in 711 def o : XOForm_3<opcode, xo, oe, OOL, IOL, 712 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 713 []>, isDOT, RecFormRel; 714 } 715 } 716 717 multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 718 string asmbase, string asmstr, InstrItinClass itin, 719 list<dag> pattern> { 720 let BaseName = asmbase in { 721 def NAME : MForm_2<opcode, OOL, IOL, 722 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 723 pattern>, RecFormRel; 724 let Defs = [CR0] in 725 def o : MForm_2<opcode, OOL, IOL, 726 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 727 []>, isDOT, RecFormRel; 728 } 729 } 730 731 multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 732 string asmbase, string asmstr, InstrItinClass itin, 733 list<dag> pattern> { 734 let BaseName = asmbase in { 735 def NAME : MDForm_1<opcode, xo, OOL, IOL, 736 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 737 pattern>, RecFormRel; 738 let Defs = [CR0] in 739 def o : MDForm_1<opcode, xo, OOL, IOL, 740 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 741 []>, isDOT, RecFormRel; 742 } 743 } 744 745 multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 746 string asmbase, string asmstr, InstrItinClass itin, 747 list<dag> pattern> { 748 let BaseName = asmbase in { 749 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 750 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 751 pattern>, RecFormRel; 752 let Defs = [CR0] in 753 def o : MDSForm_1<opcode, xo, OOL, IOL, 754 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 755 []>, isDOT, RecFormRel; 756 } 757 } 758 759 multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 760 string asmbase, string asmstr, InstrItinClass itin, 761 list<dag> pattern> { 762 let BaseName = asmbase in { 763 let Defs = [CARRY] in 764 def NAME : XSForm_1<opcode, xo, OOL, IOL, 765 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 766 pattern>, RecFormRel; 767 let Defs = [CARRY, CR0] in 768 def o : XSForm_1<opcode, xo, OOL, IOL, 769 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 770 []>, isDOT, RecFormRel; 771 } 772 } 773 774 multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 775 string asmbase, string asmstr, InstrItinClass itin, 776 list<dag> pattern> { 777 let BaseName = asmbase in { 778 def NAME : XForm_26<opcode, xo, OOL, IOL, 779 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 780 pattern>, RecFormRel; 781 let Defs = [CR1] in 782 def o : XForm_26<opcode, xo, OOL, IOL, 783 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 784 []>, isDOT, RecFormRel; 785 } 786 } 787 788 multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 789 string asmbase, string asmstr, InstrItinClass itin, 790 list<dag> pattern> { 791 let BaseName = asmbase in { 792 def NAME : AForm_1<opcode, xo, OOL, IOL, 793 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 794 pattern>, RecFormRel; 795 let Defs = [CR1] in 796 def o : AForm_1<opcode, xo, OOL, IOL, 797 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 798 []>, isDOT, RecFormRel; 799 } 800 } 801 802 multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 803 string asmbase, string asmstr, InstrItinClass itin, 804 list<dag> pattern> { 805 let BaseName = asmbase in { 806 def NAME : AForm_2<opcode, xo, OOL, IOL, 807 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 808 pattern>, RecFormRel; 809 let Defs = [CR1] in 810 def o : AForm_2<opcode, xo, OOL, IOL, 811 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 812 []>, isDOT, RecFormRel; 813 } 814 } 815 816 multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 817 string asmbase, string asmstr, InstrItinClass itin, 818 list<dag> pattern> { 819 let BaseName = asmbase in { 820 def NAME : AForm_3<opcode, xo, OOL, IOL, 821 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 822 pattern>, RecFormRel; 823 let Defs = [CR1] in 824 def o : AForm_3<opcode, xo, OOL, IOL, 825 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 826 []>, isDOT, RecFormRel; 827 } 828 } 829 830 //===----------------------------------------------------------------------===// 831 // PowerPC Instruction Definitions. 832 833 // Pseudo-instructions: 834 835 let hasCtrlDep = 1 in { 836 let Defs = [R1], Uses = [R1] in { 837 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt", 838 [(callseq_start timm:$amt)]>; 839 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2", 840 [(callseq_end timm:$amt1, timm:$amt2)]>; 841 } 842 843 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS), 844 "UPDATE_VRSAVE $rD, $rS", []>; 845 } 846 847 let Defs = [R1], Uses = [R1] in 848 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 849 [(set i32:$result, 850 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 851 852 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 853 // instruction selection into a branch sequence. 854 let usesCustomInserter = 1, // Expanded after instruction selection. 855 PPC970_Single = 1 in { 856 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 857 // because either operand might become the first operand in an isel, and 858 // that operand cannot be r0. 859 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond, 860 gprc_nor0:$T, gprc_nor0:$F, 861 i32imm:$BROPC), "#SELECT_CC_I4", 862 []>; 863 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond, 864 g8rc_nox0:$T, g8rc_nox0:$F, 865 i32imm:$BROPC), "#SELECT_CC_I8", 866 []>; 867 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 868 i32imm:$BROPC), "#SELECT_CC_F4", 869 []>; 870 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 871 i32imm:$BROPC), "#SELECT_CC_F8", 872 []>; 873 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 874 i32imm:$BROPC), "#SELECT_CC_VRRC", 875 []>; 876 } 877 878 // SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 879 // scavenge a register for it. 880 let mayStore = 1 in 881 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F), 882 "#SPILL_CR", []>; 883 884 // RESTORE_CR - Indicate that we're restoring the CR register (previously 885 // spilled), so we'll need to scavenge a register for it. 886 let mayLoad = 1 in 887 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F), 888 "#RESTORE_CR", []>; 889 890 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 891 let isReturn = 1, Uses = [LR, RM] in 892 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", BrB, 893 [(retflag)]>; 894 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 895 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>; 896 897 let isCodeGenOnly = 1 in 898 def BCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 899 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>; 900 } 901 } 902 903 let Defs = [LR] in 904 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, 905 PPC970_Unit_BRU; 906 907 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 908 let isBarrier = 1 in { 909 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), 910 "b $dst", BrB, 911 [(br bb:$dst)]>; 912 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), 913 "ba $dst", BrB, []>; 914 } 915 916 // BCC represents an arbitrary conditional branch on a predicate. 917 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 918 // a two-value operand where a dag node expects two operands. :( 919 let isCodeGenOnly = 1 in { 920 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), 921 "b${cond:cc}${cond:pm} ${cond:reg}, $dst" 922 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; 923 def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), 924 "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; 925 926 let isReturn = 1, Uses = [LR, RM] in 927 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), 928 "b${cond:cc}lr${cond:pm} ${cond:reg}", BrB, []>; 929 } 930 931 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 932 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 933 "bdzlr", BrB, []>; 934 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 935 "bdnzlr", BrB, []>; 936 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 937 "bdzlr+", BrB, []>; 938 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 939 "bdnzlr+", BrB, []>; 940 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 941 "bdzlr-", BrB, []>; 942 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 943 "bdnzlr-", BrB, []>; 944 } 945 946 let Defs = [CTR], Uses = [CTR] in { 947 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 948 "bdz $dst">; 949 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 950 "bdnz $dst">; 951 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), 952 "bdza $dst">; 953 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), 954 "bdnza $dst">; 955 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), 956 "bdz+ $dst">; 957 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), 958 "bdnz+ $dst">; 959 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), 960 "bdza+ $dst">; 961 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), 962 "bdnza+ $dst">; 963 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), 964 "bdz- $dst">; 965 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), 966 "bdnz- $dst">; 967 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), 968 "bdza- $dst">; 969 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), 970 "bdnza- $dst">; 971 } 972 } 973 974 // The unconditional BCL used by the SjLj setjmp code. 975 let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7 in { 976 let Defs = [LR], Uses = [RM] in { 977 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), 978 "bcl 20, 31, $dst">; 979 } 980 } 981 982 let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 983 // Convenient aliases for call instructions 984 let Uses = [RM] in { 985 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), 986 "bl $func", BrB, []>; // See Pat patterns below. 987 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 988 "bla $func", BrB, [(PPCcall (i32 imm:$func))]>; 989 990 let isCodeGenOnly = 1 in { 991 def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), 992 "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; 993 def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), 994 "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; 995 } 996 } 997 let Uses = [CTR, RM] in { 998 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 999 "bctrl", BrB, [(PPCbctrl)]>, 1000 Requires<[In32BitMode]>; 1001 1002 let isCodeGenOnly = 1 in 1003 def BCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 1004 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>; 1005 } 1006 let Uses = [LR, RM] in { 1007 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1008 "blrl", BrB, []>; 1009 1010 let isCodeGenOnly = 1 in 1011 def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), 1012 "b${cond:cc}lrl${cond:pm} ${cond:reg}", BrB, []>; 1013 } 1014 let Defs = [CTR], Uses = [CTR, RM] in { 1015 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), 1016 "bdzl $dst">; 1017 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), 1018 "bdnzl $dst">; 1019 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), 1020 "bdzla $dst">; 1021 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), 1022 "bdnzla $dst">; 1023 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), 1024 "bdzl+ $dst">; 1025 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), 1026 "bdnzl+ $dst">; 1027 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), 1028 "bdzla+ $dst">; 1029 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), 1030 "bdnzla+ $dst">; 1031 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), 1032 "bdzl- $dst">; 1033 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), 1034 "bdnzl- $dst">; 1035 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), 1036 "bdzla- $dst">; 1037 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), 1038 "bdnzla- $dst">; 1039 } 1040 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1041 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1042 "bdzlrl", BrB, []>; 1043 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1044 "bdnzlrl", BrB, []>; 1045 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1046 "bdzlrl+", BrB, []>; 1047 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1048 "bdnzlrl+", BrB, []>; 1049 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1050 "bdzlrl-", BrB, []>; 1051 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1052 "bdnzlrl-", BrB, []>; 1053 } 1054 } 1055 1056 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1057 def TCRETURNdi :Pseudo< (outs), 1058 (ins calltarget:$dst, i32imm:$offset), 1059 "#TC_RETURNd $dst $offset", 1060 []>; 1061 1062 1063 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1064 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1065 "#TC_RETURNa $func $offset", 1066 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1067 1068 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1069 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1070 "#TC_RETURNr $dst $offset", 1071 []>; 1072 1073 1074 let isCodeGenOnly = 1 in { 1075 1076 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1077 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1078 def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 1079 Requires<[In32BitMode]>; 1080 1081 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1082 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1083 def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 1084 "b $dst", BrB, 1085 []>; 1086 1087 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1088 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1089 def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 1090 "ba $dst", BrB, 1091 []>; 1092 1093 } 1094 1095 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 1096 let Defs = [CTR] in 1097 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 1098 "#EH_SJLJ_SETJMP32", 1099 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1100 Requires<[In32BitMode]>; 1101 let isTerminator = 1 in 1102 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf), 1103 "#EH_SJLJ_LONGJMP32", 1104 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1105 Requires<[In32BitMode]>; 1106 } 1107 1108 let isBranch = 1, isTerminator = 1 in { 1109 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst), 1110 "#EH_SjLj_Setup\t$dst", []>; 1111 } 1112 1113 // System call. 1114 let PPC970_Unit = 7 in { 1115 def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), 1116 "sc $lev", BrB, [(PPCsc (i32 imm:$lev))]>; 1117 } 1118 1119 // DCB* instructions. 1120 def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), 1121 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, 1122 PPC970_DGroup_Single; 1123 def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), 1124 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, 1125 PPC970_DGroup_Single; 1126 def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), 1127 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, 1128 PPC970_DGroup_Single; 1129 def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), 1130 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, 1131 PPC970_DGroup_Single; 1132 def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst), 1133 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>, 1134 PPC970_DGroup_Single; 1135 def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst), 1136 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>, 1137 PPC970_DGroup_Single; 1138 def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), 1139 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, 1140 PPC970_DGroup_Single; 1141 def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), 1142 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, 1143 PPC970_DGroup_Single; 1144 1145 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), 1146 (DCBT xoaddr:$dst)>; 1147 1148 // Atomic operations 1149 let usesCustomInserter = 1 in { 1150 let Defs = [CR0] in { 1151 def ATOMIC_LOAD_ADD_I8 : Pseudo< 1152 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1153 [(set i32:$dst, (atomic_load_add_8 xoaddr:$ptr, i32:$incr))]>; 1154 def ATOMIC_LOAD_SUB_I8 : Pseudo< 1155 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1156 [(set i32:$dst, (atomic_load_sub_8 xoaddr:$ptr, i32:$incr))]>; 1157 def ATOMIC_LOAD_AND_I8 : Pseudo< 1158 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1159 [(set i32:$dst, (atomic_load_and_8 xoaddr:$ptr, i32:$incr))]>; 1160 def ATOMIC_LOAD_OR_I8 : Pseudo< 1161 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1162 [(set i32:$dst, (atomic_load_or_8 xoaddr:$ptr, i32:$incr))]>; 1163 def ATOMIC_LOAD_XOR_I8 : Pseudo< 1164 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1165 [(set i32:$dst, (atomic_load_xor_8 xoaddr:$ptr, i32:$incr))]>; 1166 def ATOMIC_LOAD_NAND_I8 : Pseudo< 1167 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1168 [(set i32:$dst, (atomic_load_nand_8 xoaddr:$ptr, i32:$incr))]>; 1169 def ATOMIC_LOAD_ADD_I16 : Pseudo< 1170 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1171 [(set i32:$dst, (atomic_load_add_16 xoaddr:$ptr, i32:$incr))]>; 1172 def ATOMIC_LOAD_SUB_I16 : Pseudo< 1173 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1174 [(set i32:$dst, (atomic_load_sub_16 xoaddr:$ptr, i32:$incr))]>; 1175 def ATOMIC_LOAD_AND_I16 : Pseudo< 1176 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1177 [(set i32:$dst, (atomic_load_and_16 xoaddr:$ptr, i32:$incr))]>; 1178 def ATOMIC_LOAD_OR_I16 : Pseudo< 1179 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1180 [(set i32:$dst, (atomic_load_or_16 xoaddr:$ptr, i32:$incr))]>; 1181 def ATOMIC_LOAD_XOR_I16 : Pseudo< 1182 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1183 [(set i32:$dst, (atomic_load_xor_16 xoaddr:$ptr, i32:$incr))]>; 1184 def ATOMIC_LOAD_NAND_I16 : Pseudo< 1185 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1186 [(set i32:$dst, (atomic_load_nand_16 xoaddr:$ptr, i32:$incr))]>; 1187 def ATOMIC_LOAD_ADD_I32 : Pseudo< 1188 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1189 [(set i32:$dst, (atomic_load_add_32 xoaddr:$ptr, i32:$incr))]>; 1190 def ATOMIC_LOAD_SUB_I32 : Pseudo< 1191 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1192 [(set i32:$dst, (atomic_load_sub_32 xoaddr:$ptr, i32:$incr))]>; 1193 def ATOMIC_LOAD_AND_I32 : Pseudo< 1194 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1195 [(set i32:$dst, (atomic_load_and_32 xoaddr:$ptr, i32:$incr))]>; 1196 def ATOMIC_LOAD_OR_I32 : Pseudo< 1197 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1198 [(set i32:$dst, (atomic_load_or_32 xoaddr:$ptr, i32:$incr))]>; 1199 def ATOMIC_LOAD_XOR_I32 : Pseudo< 1200 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1201 [(set i32:$dst, (atomic_load_xor_32 xoaddr:$ptr, i32:$incr))]>; 1202 def ATOMIC_LOAD_NAND_I32 : Pseudo< 1203 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1204 [(set i32:$dst, (atomic_load_nand_32 xoaddr:$ptr, i32:$incr))]>; 1205 1206 def ATOMIC_CMP_SWAP_I8 : Pseudo< 1207 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1208 [(set i32:$dst, (atomic_cmp_swap_8 xoaddr:$ptr, i32:$old, i32:$new))]>; 1209 def ATOMIC_CMP_SWAP_I16 : Pseudo< 1210 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1211 [(set i32:$dst, (atomic_cmp_swap_16 xoaddr:$ptr, i32:$old, i32:$new))]>; 1212 def ATOMIC_CMP_SWAP_I32 : Pseudo< 1213 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1214 [(set i32:$dst, (atomic_cmp_swap_32 xoaddr:$ptr, i32:$old, i32:$new))]>; 1215 1216 def ATOMIC_SWAP_I8 : Pseudo< 1217 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1218 [(set i32:$dst, (atomic_swap_8 xoaddr:$ptr, i32:$new))]>; 1219 def ATOMIC_SWAP_I16 : Pseudo< 1220 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1221 [(set i32:$dst, (atomic_swap_16 xoaddr:$ptr, i32:$new))]>; 1222 def ATOMIC_SWAP_I32 : Pseudo< 1223 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1224 [(set i32:$dst, (atomic_swap_32 xoaddr:$ptr, i32:$new))]>; 1225 } 1226 } 1227 1228 // Instructions to support atomic operations 1229 def LWARX : XForm_1<31, 20, (outs gprc:$rD), (ins memrr:$src), 1230 "lwarx $rD, $src", LdStLWARX, 1231 [(set i32:$rD, (PPClarx xoaddr:$src))]>; 1232 1233 let Defs = [CR0] in 1234 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst), 1235 "stwcx. $rS, $dst", LdStSTWCX, 1236 [(PPCstcx i32:$rS, xoaddr:$dst)]>, 1237 isDOT; 1238 1239 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 1240 def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStLoad, [(trap)]>; 1241 1242 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm), 1243 "twi $to, $rA, $imm", IntTrapW, []>; 1244 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB), 1245 "tw $to, $rA, $rB", IntTrapW, []>; 1246 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm), 1247 "tdi $to, $rA, $imm", IntTrapD, []>; 1248 def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB), 1249 "td $to, $rA, $rB", IntTrapD, []>; 1250 1251 //===----------------------------------------------------------------------===// 1252 // PPC32 Load Instructions. 1253 // 1254 1255 // Unindexed (r+i) Loads. 1256 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 1257 def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), 1258 "lbz $rD, $src", LdStLoad, 1259 [(set i32:$rD, (zextloadi8 iaddr:$src))]>; 1260 def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), 1261 "lha $rD, $src", LdStLHA, 1262 [(set i32:$rD, (sextloadi16 iaddr:$src))]>, 1263 PPC970_DGroup_Cracked; 1264 def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), 1265 "lhz $rD, $src", LdStLoad, 1266 [(set i32:$rD, (zextloadi16 iaddr:$src))]>; 1267 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), 1268 "lwz $rD, $src", LdStLoad, 1269 [(set i32:$rD, (load iaddr:$src))]>; 1270 1271 def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), 1272 "lfs $rD, $src", LdStLFD, 1273 [(set f32:$rD, (load iaddr:$src))]>; 1274 def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), 1275 "lfd $rD, $src", LdStLFD, 1276 [(set f64:$rD, (load iaddr:$src))]>; 1277 1278 1279 // Unindexed (r+i) Loads with Update (preinc). 1280 let mayLoad = 1, neverHasSideEffects = 1 in { 1281 def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1282 "lbzu $rD, $addr", LdStLoadUpd, 1283 []>, RegConstraint<"$addr.reg = $ea_result">, 1284 NoEncode<"$ea_result">; 1285 1286 def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1287 "lhau $rD, $addr", LdStLHAU, 1288 []>, RegConstraint<"$addr.reg = $ea_result">, 1289 NoEncode<"$ea_result">; 1290 1291 def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1292 "lhzu $rD, $addr", LdStLoadUpd, 1293 []>, RegConstraint<"$addr.reg = $ea_result">, 1294 NoEncode<"$ea_result">; 1295 1296 def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1297 "lwzu $rD, $addr", LdStLoadUpd, 1298 []>, RegConstraint<"$addr.reg = $ea_result">, 1299 NoEncode<"$ea_result">; 1300 1301 def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1302 "lfsu $rD, $addr", LdStLFDU, 1303 []>, RegConstraint<"$addr.reg = $ea_result">, 1304 NoEncode<"$ea_result">; 1305 1306 def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 1307 "lfdu $rD, $addr", LdStLFDU, 1308 []>, RegConstraint<"$addr.reg = $ea_result">, 1309 NoEncode<"$ea_result">; 1310 1311 1312 // Indexed (r+r) Loads with Update (preinc). 1313 def LBZUX : XForm_1<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1314 (ins memrr:$addr), 1315 "lbzux $rD, $addr", LdStLoadUpd, 1316 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1317 NoEncode<"$ea_result">; 1318 1319 def LHAUX : XForm_1<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1320 (ins memrr:$addr), 1321 "lhaux $rD, $addr", LdStLHAU, 1322 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1323 NoEncode<"$ea_result">; 1324 1325 def LHZUX : XForm_1<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1326 (ins memrr:$addr), 1327 "lhzux $rD, $addr", LdStLoadUpd, 1328 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1329 NoEncode<"$ea_result">; 1330 1331 def LWZUX : XForm_1<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), 1332 (ins memrr:$addr), 1333 "lwzux $rD, $addr", LdStLoadUpd, 1334 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1335 NoEncode<"$ea_result">; 1336 1337 def LFSUX : XForm_1<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), 1338 (ins memrr:$addr), 1339 "lfsux $rD, $addr", LdStLFDU, 1340 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1341 NoEncode<"$ea_result">; 1342 1343 def LFDUX : XForm_1<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), 1344 (ins memrr:$addr), 1345 "lfdux $rD, $addr", LdStLFDU, 1346 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 1347 NoEncode<"$ea_result">; 1348 } 1349 } 1350 1351 // Indexed (r+r) Loads. 1352 // 1353 let canFoldAsLoad = 1, PPC970_Unit = 2 in { 1354 def LBZX : XForm_1<31, 87, (outs gprc:$rD), (ins memrr:$src), 1355 "lbzx $rD, $src", LdStLoad, 1356 [(set i32:$rD, (zextloadi8 xaddr:$src))]>; 1357 def LHAX : XForm_1<31, 343, (outs gprc:$rD), (ins memrr:$src), 1358 "lhax $rD, $src", LdStLHA, 1359 [(set i32:$rD, (sextloadi16 xaddr:$src))]>, 1360 PPC970_DGroup_Cracked; 1361 def LHZX : XForm_1<31, 279, (outs gprc:$rD), (ins memrr:$src), 1362 "lhzx $rD, $src", LdStLoad, 1363 [(set i32:$rD, (zextloadi16 xaddr:$src))]>; 1364 def LWZX : XForm_1<31, 23, (outs gprc:$rD), (ins memrr:$src), 1365 "lwzx $rD, $src", LdStLoad, 1366 [(set i32:$rD, (load xaddr:$src))]>; 1367 1368 1369 def LHBRX : XForm_1<31, 790, (outs gprc:$rD), (ins memrr:$src), 1370 "lhbrx $rD, $src", LdStLoad, 1371 [(set i32:$rD, (PPClbrx xoaddr:$src, i16))]>; 1372 def LWBRX : XForm_1<31, 534, (outs gprc:$rD), (ins memrr:$src), 1373 "lwbrx $rD, $src", LdStLoad, 1374 [(set i32:$rD, (PPClbrx xoaddr:$src, i32))]>; 1375 1376 def LFSX : XForm_25<31, 535, (outs f4rc:$frD), (ins memrr:$src), 1377 "lfsx $frD, $src", LdStLFD, 1378 [(set f32:$frD, (load xaddr:$src))]>; 1379 def LFDX : XForm_25<31, 599, (outs f8rc:$frD), (ins memrr:$src), 1380 "lfdx $frD, $src", LdStLFD, 1381 [(set f64:$frD, (load xaddr:$src))]>; 1382 1383 def LFIWAX : XForm_25<31, 855, (outs f8rc:$frD), (ins memrr:$src), 1384 "lfiwax $frD, $src", LdStLFD, 1385 [(set f64:$frD, (PPClfiwax xoaddr:$src))]>; 1386 def LFIWZX : XForm_25<31, 887, (outs f8rc:$frD), (ins memrr:$src), 1387 "lfiwzx $frD, $src", LdStLFD, 1388 [(set f64:$frD, (PPClfiwzx xoaddr:$src))]>; 1389 } 1390 1391 // Load Multiple 1392 def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), 1393 "lmw $rD, $src", LdStLMW, []>; 1394 1395 //===----------------------------------------------------------------------===// 1396 // PPC32 Store Instructions. 1397 // 1398 1399 // Unindexed (r+i) Stores. 1400 let PPC970_Unit = 2 in { 1401 def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$src), 1402 "stb $rS, $src", LdStStore, 1403 [(truncstorei8 i32:$rS, iaddr:$src)]>; 1404 def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$src), 1405 "sth $rS, $src", LdStStore, 1406 [(truncstorei16 i32:$rS, iaddr:$src)]>; 1407 def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$src), 1408 "stw $rS, $src", LdStStore, 1409 [(store i32:$rS, iaddr:$src)]>; 1410 def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), 1411 "stfs $rS, $dst", LdStSTFD, 1412 [(store f32:$rS, iaddr:$dst)]>; 1413 def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), 1414 "stfd $rS, $dst", LdStSTFD, 1415 [(store f64:$rS, iaddr:$dst)]>; 1416 } 1417 1418 // Unindexed (r+i) Stores with Update (preinc). 1419 let PPC970_Unit = 2, mayStore = 1 in { 1420 def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1421 "stbu $rS, $dst", LdStStoreUpd, []>, 1422 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1423 def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1424 "sthu $rS, $dst", LdStStoreUpd, []>, 1425 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1426 def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), 1427 "stwu $rS, $dst", LdStStoreUpd, []>, 1428 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1429 def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), 1430 "stfsu $rS, $dst", LdStSTFDU, []>, 1431 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1432 def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), 1433 "stfdu $rS, $dst", LdStSTFDU, []>, 1434 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 1435 } 1436 1437 // Patterns to match the pre-inc stores. We can't put the patterns on 1438 // the instruction definitions directly as ISel wants the address base 1439 // and offset to be separate operands, not a single complex operand. 1440 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1441 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 1442 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1443 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 1444 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1445 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 1446 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1447 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 1448 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 1449 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 1450 1451 // Indexed (r+r) Stores. 1452 let PPC970_Unit = 2 in { 1453 def STBX : XForm_8<31, 215, (outs), (ins gprc:$rS, memrr:$dst), 1454 "stbx $rS, $dst", LdStStore, 1455 [(truncstorei8 i32:$rS, xaddr:$dst)]>, 1456 PPC970_DGroup_Cracked; 1457 def STHX : XForm_8<31, 407, (outs), (ins gprc:$rS, memrr:$dst), 1458 "sthx $rS, $dst", LdStStore, 1459 [(truncstorei16 i32:$rS, xaddr:$dst)]>, 1460 PPC970_DGroup_Cracked; 1461 def STWX : XForm_8<31, 151, (outs), (ins gprc:$rS, memrr:$dst), 1462 "stwx $rS, $dst", LdStStore, 1463 [(store i32:$rS, xaddr:$dst)]>, 1464 PPC970_DGroup_Cracked; 1465 1466 def STHBRX: XForm_8<31, 918, (outs), (ins gprc:$rS, memrr:$dst), 1467 "sthbrx $rS, $dst", LdStStore, 1468 [(PPCstbrx i32:$rS, xoaddr:$dst, i16)]>, 1469 PPC970_DGroup_Cracked; 1470 def STWBRX: XForm_8<31, 662, (outs), (ins gprc:$rS, memrr:$dst), 1471 "stwbrx $rS, $dst", LdStStore, 1472 [(PPCstbrx i32:$rS, xoaddr:$dst, i32)]>, 1473 PPC970_DGroup_Cracked; 1474 1475 def STFIWX: XForm_28<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), 1476 "stfiwx $frS, $dst", LdStSTFD, 1477 [(PPCstfiwx f64:$frS, xoaddr:$dst)]>; 1478 1479 def STFSX : XForm_28<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), 1480 "stfsx $frS, $dst", LdStSTFD, 1481 [(store f32:$frS, xaddr:$dst)]>; 1482 def STFDX : XForm_28<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), 1483 "stfdx $frS, $dst", LdStSTFD, 1484 [(store f64:$frS, xaddr:$dst)]>; 1485 } 1486 1487 // Indexed (r+r) Stores with Update (preinc). 1488 let PPC970_Unit = 2, mayStore = 1 in { 1489 def STBUX : XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1490 "stbux $rS, $dst", LdStStoreUpd, []>, 1491 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1492 PPC970_DGroup_Cracked; 1493 def STHUX : XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1494 "sthux $rS, $dst", LdStStoreUpd, []>, 1495 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1496 PPC970_DGroup_Cracked; 1497 def STWUX : XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memrr:$dst), 1498 "stwux $rS, $dst", LdStStoreUpd, []>, 1499 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1500 PPC970_DGroup_Cracked; 1501 def STFSUX: XForm_8<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memrr:$dst), 1502 "stfsux $rS, $dst", LdStSTFDU, []>, 1503 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1504 PPC970_DGroup_Cracked; 1505 def STFDUX: XForm_8<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memrr:$dst), 1506 "stfdux $rS, $dst", LdStSTFDU, []>, 1507 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 1508 PPC970_DGroup_Cracked; 1509 } 1510 1511 // Patterns to match the pre-inc stores. We can't put the patterns on 1512 // the instruction definitions directly as ISel wants the address base 1513 // and offset to be separate operands, not a single complex operand. 1514 def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1515 (STBUX $rS, $ptrreg, $ptroff)>; 1516 def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1517 (STHUX $rS, $ptrreg, $ptroff)>; 1518 def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1519 (STWUX $rS, $ptrreg, $ptroff)>; 1520 def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1521 (STFSUX $rS, $ptrreg, $ptroff)>; 1522 def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 1523 (STFDUX $rS, $ptrreg, $ptroff)>; 1524 1525 // Store Multiple 1526 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), 1527 "stmw $rS, $dst", LdStLMW, []>; 1528 1529 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L), 1530 "sync $L", LdStSync, []>; 1531 def : Pat<(int_ppc_sync), (SYNC 0)>; 1532 1533 //===----------------------------------------------------------------------===// 1534 // PPC32 Arithmetic Instructions. 1535 // 1536 1537 let PPC970_Unit = 1 in { // FXU Operations. 1538 def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), 1539 "addi $rD, $rA, $imm", IntSimple, 1540 [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; 1541 let BaseName = "addic" in { 1542 let Defs = [CARRY] in 1543 def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1544 "addic $rD, $rA, $imm", IntGeneral, 1545 [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, 1546 RecFormRel, PPC970_DGroup_Cracked; 1547 let Defs = [CARRY, CR0] in 1548 def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1549 "addic. $rD, $rA, $imm", IntGeneral, 1550 []>, isDOT, RecFormRel; 1551 } 1552 def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), 1553 "addis $rD, $rA, $imm", IntSimple, 1554 [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; 1555 let isCodeGenOnly = 1 in 1556 def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), 1557 "la $rD, $sym($rA)", IntGeneral, 1558 [(set i32:$rD, (add i32:$rA, 1559 (PPClo tglobaladdr:$sym, 0)))]>; 1560 def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1561 "mulli $rD, $rA, $imm", IntMulLI, 1562 [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; 1563 let Defs = [CARRY] in 1564 def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), 1565 "subfic $rD, $rA, $imm", IntGeneral, 1566 [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; 1567 1568 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1569 def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), 1570 "li $rD, $imm", IntSimple, 1571 [(set i32:$rD, imm32SExt16:$imm)]>; 1572 def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), 1573 "lis $rD, $imm", IntSimple, 1574 [(set i32:$rD, imm16ShiftedSExt:$imm)]>; 1575 } 1576 } 1577 1578 let PPC970_Unit = 1 in { // FXU Operations. 1579 let Defs = [CR0] in { 1580 def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1581 "andi. $dst, $src1, $src2", IntGeneral, 1582 [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, 1583 isDOT; 1584 def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1585 "andis. $dst, $src1, $src2", IntGeneral, 1586 [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, 1587 isDOT; 1588 } 1589 def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1590 "ori $dst, $src1, $src2", IntSimple, 1591 [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; 1592 def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1593 "oris $dst, $src1, $src2", IntSimple, 1594 [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; 1595 def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1596 "xori $dst, $src1, $src2", IntSimple, 1597 [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; 1598 def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), 1599 "xoris $dst, $src1, $src2", IntSimple, 1600 [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; 1601 def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntSimple, 1602 []>; 1603 let isCompare = 1, neverHasSideEffects = 1 in { 1604 def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), 1605 "cmpwi $crD, $rA, $imm", IntCompare>; 1606 def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), 1607 "cmplwi $dst, $src1, $src2", IntCompare>; 1608 } 1609 } 1610 1611 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 1612 defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1613 "nand", "$rA, $rS, $rB", IntSimple, 1614 [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; 1615 defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1616 "and", "$rA, $rS, $rB", IntSimple, 1617 [(set i32:$rA, (and i32:$rS, i32:$rB))]>; 1618 defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1619 "andc", "$rA, $rS, $rB", IntSimple, 1620 [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; 1621 defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1622 "or", "$rA, $rS, $rB", IntSimple, 1623 [(set i32:$rA, (or i32:$rS, i32:$rB))]>; 1624 defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1625 "nor", "$rA, $rS, $rB", IntSimple, 1626 [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; 1627 defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1628 "orc", "$rA, $rS, $rB", IntSimple, 1629 [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; 1630 defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1631 "eqv", "$rA, $rS, $rB", IntSimple, 1632 [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; 1633 defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1634 "xor", "$rA, $rS, $rB", IntSimple, 1635 [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; 1636 defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1637 "slw", "$rA, $rS, $rB", IntGeneral, 1638 [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>; 1639 defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1640 "srw", "$rA, $rS, $rB", IntGeneral, 1641 [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>; 1642 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), 1643 "sraw", "$rA, $rS, $rB", IntShift, 1644 [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>; 1645 } 1646 1647 let PPC970_Unit = 1 in { // FXU Operations. 1648 let neverHasSideEffects = 1 in { 1649 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), 1650 "srawi", "$rA, $rS, $SH", IntShift, 1651 [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>; 1652 defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), 1653 "cntlzw", "$rA, $rS", IntGeneral, 1654 [(set i32:$rA, (ctlz i32:$rS))]>; 1655 defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), 1656 "extsb", "$rA, $rS", IntSimple, 1657 [(set i32:$rA, (sext_inreg i32:$rS, i8))]>; 1658 defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), 1659 "extsh", "$rA, $rS", IntSimple, 1660 [(set i32:$rA, (sext_inreg i32:$rS, i16))]>; 1661 } 1662 let isCompare = 1, neverHasSideEffects = 1 in { 1663 def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 1664 "cmpw $crD, $rA, $rB", IntCompare>; 1665 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), 1666 "cmplw $crD, $rA, $rB", IntCompare>; 1667 } 1668 } 1669 let PPC970_Unit = 3 in { // FPU Operations. 1670 //def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB), 1671 // "fcmpo $crD, $fA, $fB", FPCompare>; 1672 let isCompare = 1, neverHasSideEffects = 1 in { 1673 def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), 1674 "fcmpu $crD, $fA, $fB", FPCompare>; 1675 def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), 1676 "fcmpu $crD, $fA, $fB", FPCompare>; 1677 } 1678 1679 let Uses = [RM] in { 1680 let neverHasSideEffects = 1 in { 1681 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), 1682 "fctiwz", "$frD, $frB", FPGeneral, 1683 [(set f64:$frD, (PPCfctiwz f64:$frB))]>; 1684 1685 defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), 1686 "frsp", "$frD, $frB", FPGeneral, 1687 [(set f32:$frD, (fround f64:$frB))]>; 1688 1689 // The frin -> nearbyint mapping is valid only in fast-math mode. 1690 let Interpretation64Bit = 1 in 1691 defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), 1692 "frin", "$frD, $frB", FPGeneral, 1693 [(set f64:$frD, (fnearbyint f64:$frB))]>; 1694 defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), 1695 "frin", "$frD, $frB", FPGeneral, 1696 [(set f32:$frD, (fnearbyint f32:$frB))]>; 1697 } 1698 1699 // These pseudos expand to rint but also set FE_INEXACT when the result does 1700 // not equal the argument. 1701 let usesCustomInserter = 1, Defs = [RM] in { // FIXME: Model FPSCR! 1702 def FRINDrint : Pseudo<(outs f8rc:$frD), (ins f8rc:$frB), 1703 "#FRINDrint", [(set f64:$frD, (frint f64:$frB))]>; 1704 def FRINSrint : Pseudo<(outs f4rc:$frD), (ins f4rc:$frB), 1705 "#FRINSrint", [(set f32:$frD, (frint f32:$frB))]>; 1706 } 1707 1708 let neverHasSideEffects = 1 in { 1709 let Interpretation64Bit = 1 in 1710 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), 1711 "frip", "$frD, $frB", FPGeneral, 1712 [(set f64:$frD, (fceil f64:$frB))]>; 1713 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), 1714 "frip", "$frD, $frB", FPGeneral, 1715 [(set f32:$frD, (fceil f32:$frB))]>; 1716 let Interpretation64Bit = 1 in 1717 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), 1718 "friz", "$frD, $frB", FPGeneral, 1719 [(set f64:$frD, (ftrunc f64:$frB))]>; 1720 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), 1721 "friz", "$frD, $frB", FPGeneral, 1722 [(set f32:$frD, (ftrunc f32:$frB))]>; 1723 let Interpretation64Bit = 1 in 1724 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), 1725 "frim", "$frD, $frB", FPGeneral, 1726 [(set f64:$frD, (ffloor f64:$frB))]>; 1727 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), 1728 "frim", "$frD, $frB", FPGeneral, 1729 [(set f32:$frD, (ffloor f32:$frB))]>; 1730 1731 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), 1732 "fsqrt", "$frD, $frB", FPSqrt, 1733 [(set f64:$frD, (fsqrt f64:$frB))]>; 1734 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), 1735 "fsqrts", "$frD, $frB", FPSqrt, 1736 [(set f32:$frD, (fsqrt f32:$frB))]>; 1737 } 1738 } 1739 } 1740 1741 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are 1742 /// often coalesced away and we don't want the dispatch group builder to think 1743 /// that they will fill slots (which could cause the load of a LSU reject to 1744 /// sneak into a d-group with a store). 1745 let neverHasSideEffects = 1 in 1746 defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), 1747 "fmr", "$frD, $frB", FPGeneral, 1748 []>, // (set f32:$frD, f32:$frB) 1749 PPC970_Unit_Pseudo; 1750 1751 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 1752 // These are artificially split into two different forms, for 4/8 byte FP. 1753 defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), 1754 "fabs", "$frD, $frB", FPGeneral, 1755 [(set f32:$frD, (fabs f32:$frB))]>; 1756 let Interpretation64Bit = 1 in 1757 defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), 1758 "fabs", "$frD, $frB", FPGeneral, 1759 [(set f64:$frD, (fabs f64:$frB))]>; 1760 defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), 1761 "fnabs", "$frD, $frB", FPGeneral, 1762 [(set f32:$frD, (fneg (fabs f32:$frB)))]>; 1763 let Interpretation64Bit = 1 in 1764 defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), 1765 "fnabs", "$frD, $frB", FPGeneral, 1766 [(set f64:$frD, (fneg (fabs f64:$frB)))]>; 1767 defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), 1768 "fneg", "$frD, $frB", FPGeneral, 1769 [(set f32:$frD, (fneg f32:$frB))]>; 1770 let Interpretation64Bit = 1 in 1771 defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), 1772 "fneg", "$frD, $frB", FPGeneral, 1773 [(set f64:$frD, (fneg f64:$frB))]>; 1774 1775 // Reciprocal estimates. 1776 defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), 1777 "fre", "$frD, $frB", FPGeneral, 1778 [(set f64:$frD, (PPCfre f64:$frB))]>; 1779 defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), 1780 "fres", "$frD, $frB", FPGeneral, 1781 [(set f32:$frD, (PPCfre f32:$frB))]>; 1782 defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), 1783 "frsqrte", "$frD, $frB", FPGeneral, 1784 [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; 1785 defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), 1786 "frsqrtes", "$frD, $frB", FPGeneral, 1787 [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; 1788 } 1789 1790 // XL-Form instructions. condition register logical ops. 1791 // 1792 let neverHasSideEffects = 1 in 1793 def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 1794 "mcrf $BF, $BFA", BrMCR>, 1795 PPC970_DGroup_First, PPC970_Unit_CRU; 1796 1797 def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 1798 (ins crbitrc:$CRA, crbitrc:$CRB), 1799 "crand $CRD, $CRA, $CRB", BrCR, []>; 1800 1801 def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 1802 (ins crbitrc:$CRA, crbitrc:$CRB), 1803 "crnand $CRD, $CRA, $CRB", BrCR, []>; 1804 1805 def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 1806 (ins crbitrc:$CRA, crbitrc:$CRB), 1807 "cror $CRD, $CRA, $CRB", BrCR, []>; 1808 1809 def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 1810 (ins crbitrc:$CRA, crbitrc:$CRB), 1811 "crxor $CRD, $CRA, $CRB", BrCR, []>; 1812 1813 def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 1814 (ins crbitrc:$CRA, crbitrc:$CRB), 1815 "crnor $CRD, $CRA, $CRB", BrCR, []>; 1816 1817 def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 1818 (ins crbitrc:$CRA, crbitrc:$CRB), 1819 "creqv $CRD, $CRA, $CRB", BrCR, []>; 1820 1821 def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 1822 (ins crbitrc:$CRA, crbitrc:$CRB), 1823 "crandc $CRD, $CRA, $CRB", BrCR, []>; 1824 1825 def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 1826 (ins crbitrc:$CRA, crbitrc:$CRB), 1827 "crorc $CRD, $CRA, $CRB", BrCR, []>; 1828 1829 let isCodeGenOnly = 1 in { 1830 def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), 1831 "creqv $dst, $dst, $dst", BrCR, 1832 []>; 1833 1834 def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), 1835 "crxor $dst, $dst, $dst", BrCR, 1836 []>; 1837 1838 let Defs = [CR1EQ], CRD = 6 in { 1839 def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 1840 "creqv 6, 6, 6", BrCR, 1841 [(PPCcr6set)]>; 1842 1843 def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 1844 "crxor 6, 6, 6", BrCR, 1845 [(PPCcr6unset)]>; 1846 } 1847 } 1848 1849 // XFX-Form instructions. Instructions that deal with SPRs. 1850 // 1851 1852 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), 1853 "mfspr $RT, $SPR", SprMFSPR>; 1854 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), 1855 "mtspr $SPR, $RT", SprMTSPR>; 1856 1857 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), 1858 "mftb $RT, $SPR", SprMFTB>; 1859 1860 let Uses = [CTR] in { 1861 def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), 1862 "mfctr $rT", SprMFSPR>, 1863 PPC970_DGroup_First, PPC970_Unit_FXU; 1864 } 1865 let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { 1866 def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 1867 "mtctr $rS", SprMTSPR>, 1868 PPC970_DGroup_First, PPC970_Unit_FXU; 1869 } 1870 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { 1871 let Pattern = [(int_ppc_mtctr i32:$rS)] in 1872 def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), 1873 "mtctr $rS", SprMTSPR>, 1874 PPC970_DGroup_First, PPC970_Unit_FXU; 1875 } 1876 1877 let Defs = [LR] in { 1878 def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), 1879 "mtlr $rS", SprMTSPR>, 1880 PPC970_DGroup_First, PPC970_Unit_FXU; 1881 } 1882 let Uses = [LR] in { 1883 def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), 1884 "mflr $rT", SprMFSPR>, 1885 PPC970_DGroup_First, PPC970_Unit_FXU; 1886 } 1887 1888 let isCodeGenOnly = 1 in { 1889 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 1890 // like a GPR on the PPC970. As such, copies in and out have the same 1891 // performance characteristics as an OR instruction. 1892 def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), 1893 "mtspr 256, $rS", IntGeneral>, 1894 PPC970_DGroup_Single, PPC970_Unit_FXU; 1895 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), 1896 "mfspr $rT, 256", IntGeneral>, 1897 PPC970_DGroup_First, PPC970_Unit_FXU; 1898 1899 def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, 1900 (outs VRSAVERC:$reg), (ins gprc:$rS), 1901 "mtspr 256, $rS", IntGeneral>, 1902 PPC970_DGroup_Single, PPC970_Unit_FXU; 1903 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), 1904 (ins VRSAVERC:$reg), 1905 "mfspr $rT, 256", IntGeneral>, 1906 PPC970_DGroup_First, PPC970_Unit_FXU; 1907 } 1908 1909 // SPILL_VRSAVE - Indicate that we're dumping the VRSAVE register, 1910 // so we'll need to scavenge a register for it. 1911 let mayStore = 1 in 1912 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F), 1913 "#SPILL_VRSAVE", []>; 1914 1915 // RESTORE_VRSAVE - Indicate that we're restoring the VRSAVE register (previously 1916 // spilled), so we'll need to scavenge a register for it. 1917 let mayLoad = 1 in 1918 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), 1919 "#RESTORE_VRSAVE", []>; 1920 1921 let neverHasSideEffects = 1 in { 1922 def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), 1923 "mtocrf $FXM, $ST", BrMCRX>, 1924 PPC970_DGroup_First, PPC970_Unit_CRU; 1925 1926 def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), 1927 "mtcrf $FXM, $rS", BrMCRX>, 1928 PPC970_MicroCode, PPC970_Unit_CRU; 1929 1930 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), 1931 "mfocrf $rT, $FXM", SprMFCR>, 1932 PPC970_DGroup_First, PPC970_Unit_CRU; 1933 1934 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), 1935 "mfcr $rT", SprMFCR>, 1936 PPC970_MicroCode, PPC970_Unit_CRU; 1937 } // neverHasSideEffects = 1 1938 1939 // Pseudo instruction to perform FADD in round-to-zero mode. 1940 let usesCustomInserter = 1, Uses = [RM] in { 1941 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 1942 [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>; 1943 } 1944 1945 // The above pseudo gets expanded to make use of the following instructions 1946 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 1947 let Uses = [RM], Defs = [RM] in { 1948 def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 1949 "mtfsb0 $FM", IntMTFSB0, []>, 1950 PPC970_DGroup_Single, PPC970_Unit_FPU; 1951 def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 1952 "mtfsb1 $FM", IntMTFSB0, []>, 1953 PPC970_DGroup_Single, PPC970_Unit_FPU; 1954 def MTFSF : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), 1955 "mtfsf $FM, $rT", IntMTFSB0, []>, 1956 PPC970_DGroup_Single, PPC970_Unit_FPU; 1957 } 1958 let Uses = [RM] in { 1959 def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), 1960 "mffs $rT", IntMFFS, 1961 [(set f64:$rT, (PPCmffs))]>, 1962 PPC970_DGroup_Single, PPC970_Unit_FPU; 1963 } 1964 1965 1966 let PPC970_Unit = 1, neverHasSideEffects = 1 in { // FXU Operations. 1967 // XO-Form instructions. Arithmetic instructions that can set overflow bit 1968 // 1969 defm ADD4 : XOForm_1r<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1970 "add", "$rT, $rA, $rB", IntSimple, 1971 [(set i32:$rT, (add i32:$rA, i32:$rB))]>; 1972 defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1973 "addc", "$rT, $rA, $rB", IntGeneral, 1974 [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, 1975 PPC970_DGroup_Cracked; 1976 defm DIVW : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1977 "divw", "$rT, $rA, $rB", IntDivW, 1978 [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>, 1979 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1980 defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1981 "divwu", "$rT, $rA, $rB", IntDivW, 1982 [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>, 1983 PPC970_DGroup_First, PPC970_DGroup_Cracked; 1984 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1985 "mulhw", "$rT, $rA, $rB", IntMulHW, 1986 [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; 1987 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1988 "mulhwu", "$rT, $rA, $rB", IntMulHWU, 1989 [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; 1990 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1991 "mullw", "$rT, $rA, $rB", IntMulHW, 1992 [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; 1993 defm SUBF : XOForm_1r<31, 40, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1994 "subf", "$rT, $rA, $rB", IntGeneral, 1995 [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; 1996 defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 1997 "subfc", "$rT, $rA, $rB", IntGeneral, 1998 [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, 1999 PPC970_DGroup_Cracked; 2000 defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), 2001 "neg", "$rT, $rA", IntSimple, 2002 [(set i32:$rT, (ineg i32:$rA))]>; 2003 let Uses = [CARRY] in { 2004 defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2005 "adde", "$rT, $rA, $rB", IntGeneral, 2006 [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; 2007 defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), 2008 "addme", "$rT, $rA", IntGeneral, 2009 [(set i32:$rT, (adde i32:$rA, -1))]>; 2010 defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), 2011 "addze", "$rT, $rA", IntGeneral, 2012 [(set i32:$rT, (adde i32:$rA, 0))]>; 2013 defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), 2014 "subfe", "$rT, $rA, $rB", IntGeneral, 2015 [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; 2016 defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), 2017 "subfme", "$rT, $rA", IntGeneral, 2018 [(set i32:$rT, (sube -1, i32:$rA))]>; 2019 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), 2020 "subfze", "$rT, $rA", IntGeneral, 2021 [(set i32:$rT, (sube 0, i32:$rA))]>; 2022 } 2023 } 2024 2025 // A-Form instructions. Most of the instructions executed in the FPU are of 2026 // this type. 2027 // 2028 let PPC970_Unit = 3, neverHasSideEffects = 1 in { // FPU Operations. 2029 let Uses = [RM] in { 2030 defm FMADD : AForm_1r<63, 29, 2031 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2032 "fmadd", "$FRT, $FRA, $FRC, $FRB", FPFused, 2033 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 2034 defm FMADDS : AForm_1r<59, 29, 2035 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2036 "fmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 2037 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 2038 defm FMSUB : AForm_1r<63, 28, 2039 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2040 "fmsub", "$FRT, $FRA, $FRC, $FRB", FPFused, 2041 [(set f64:$FRT, 2042 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 2043 defm FMSUBS : AForm_1r<59, 28, 2044 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2045 "fmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 2046 [(set f32:$FRT, 2047 (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 2048 defm FNMADD : AForm_1r<63, 31, 2049 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2050 "fnmadd", "$FRT, $FRA, $FRC, $FRB", FPFused, 2051 [(set f64:$FRT, 2052 (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 2053 defm FNMADDS : AForm_1r<59, 31, 2054 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2055 "fnmadds", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 2056 [(set f32:$FRT, 2057 (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 2058 defm FNMSUB : AForm_1r<63, 30, 2059 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2060 "fnmsub", "$FRT, $FRA, $FRC, $FRB", FPFused, 2061 [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC, 2062 (fneg f64:$FRB))))]>; 2063 defm FNMSUBS : AForm_1r<59, 30, 2064 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2065 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 2066 [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC, 2067 (fneg f32:$FRB))))]>; 2068 } 2069 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 2070 // having 4 of these, force the comparison to always be an 8-byte double (code 2071 // should use an FMRSD if the input comparison value really wants to be a float) 2072 // and 4/8 byte forms for the result and operand type.. 2073 let Interpretation64Bit = 1 in 2074 defm FSELD : AForm_1r<63, 23, 2075 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 2076 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 2077 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 2078 defm FSELS : AForm_1r<63, 23, 2079 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 2080 "fsel", "$FRT, $FRA, $FRC, $FRB", FPGeneral, 2081 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 2082 let Uses = [RM] in { 2083 defm FADD : AForm_2r<63, 21, 2084 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2085 "fadd", "$FRT, $FRA, $FRB", FPAddSub, 2086 [(set f64:$FRT, (fadd f64:$FRA, f64:$FRB))]>; 2087 defm FADDS : AForm_2r<59, 21, 2088 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2089 "fadds", "$FRT, $FRA, $FRB", FPGeneral, 2090 [(set f32:$FRT, (fadd f32:$FRA, f32:$FRB))]>; 2091 defm FDIV : AForm_2r<63, 18, 2092 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2093 "fdiv", "$FRT, $FRA, $FRB", FPDivD, 2094 [(set f64:$FRT, (fdiv f64:$FRA, f64:$FRB))]>; 2095 defm FDIVS : AForm_2r<59, 18, 2096 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2097 "fdivs", "$FRT, $FRA, $FRB", FPDivS, 2098 [(set f32:$FRT, (fdiv f32:$FRA, f32:$FRB))]>; 2099 defm FMUL : AForm_3r<63, 25, 2100 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 2101 "fmul", "$FRT, $FRA, $FRC", FPFused, 2102 [(set f64:$FRT, (fmul f64:$FRA, f64:$FRC))]>; 2103 defm FMULS : AForm_3r<59, 25, 2104 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 2105 "fmuls", "$FRT, $FRA, $FRC", FPGeneral, 2106 [(set f32:$FRT, (fmul f32:$FRA, f32:$FRC))]>; 2107 defm FSUB : AForm_2r<63, 20, 2108 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 2109 "fsub", "$FRT, $FRA, $FRB", FPAddSub, 2110 [(set f64:$FRT, (fsub f64:$FRA, f64:$FRB))]>; 2111 defm FSUBS : AForm_2r<59, 20, 2112 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 2113 "fsubs", "$FRT, $FRA, $FRB", FPGeneral, 2114 [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; 2115 } 2116 } 2117 2118 let neverHasSideEffects = 1 in { 2119 let PPC970_Unit = 1 in { // FXU Operations. 2120 let isSelect = 1 in 2121 def ISEL : AForm_4<31, 15, 2122 (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), 2123 "isel $rT, $rA, $rB, $cond", IntGeneral, 2124 []>; 2125 } 2126 2127 let PPC970_Unit = 1 in { // FXU Operations. 2128 // M-Form instructions. rotate and mask instructions. 2129 // 2130 let isCommutable = 1 in { 2131 // RLWIMI can be commuted if the rotate amount is zero. 2132 defm RLWIMI : MForm_2r<20, (outs gprc:$rA), 2133 (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, 2134 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", IntRotate, 2135 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">, 2136 NoEncode<"$rSi">; 2137 } 2138 let BaseName = "rlwinm" in { 2139 def RLWINM : MForm_2<21, 2140 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2141 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 2142 []>, RecFormRel; 2143 let Defs = [CR0] in 2144 def RLWINMo : MForm_2<21, 2145 (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 2146 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral, 2147 []>, isDOT, RecFormRel, PPC970_DGroup_Cracked; 2148 } 2149 defm RLWNM : MForm_2r<23, (outs gprc:$rA), 2150 (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), 2151 "rlwnm", "$rA, $rS, $rB, $MB, $ME", IntGeneral, 2152 []>; 2153 } 2154 } // neverHasSideEffects = 1 2155 2156 //===----------------------------------------------------------------------===// 2157 // PowerPC Instruction Patterns 2158 // 2159 2160 // Arbitrary immediate support. Implement in terms of LIS/ORI. 2161 def : Pat<(i32 imm:$imm), 2162 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 2163 2164 // Implement the 'not' operation with the NOR instruction. 2165 def NOT : Pat<(not i32:$in), 2166 (NOR $in, $in)>; 2167 2168 // ADD an arbitrary immediate. 2169 def : Pat<(add i32:$in, imm:$imm), 2170 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 2171 // OR an arbitrary immediate. 2172 def : Pat<(or i32:$in, imm:$imm), 2173 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2174 // XOR an arbitrary immediate. 2175 def : Pat<(xor i32:$in, imm:$imm), 2176 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 2177 // SUBFIC 2178 def : Pat<(sub imm32SExt16:$imm, i32:$in), 2179 (SUBFIC $in, imm:$imm)>; 2180 2181 // SHL/SRL 2182 def : Pat<(shl i32:$in, (i32 imm:$imm)), 2183 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 2184 def : Pat<(srl i32:$in, (i32 imm:$imm)), 2185 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 2186 2187 // ROTL 2188 def : Pat<(rotl i32:$in, i32:$sh), 2189 (RLWNM $in, $sh, 0, 31)>; 2190 def : Pat<(rotl i32:$in, (i32 imm:$imm)), 2191 (RLWINM $in, imm:$imm, 0, 31)>; 2192 2193 // RLWNM 2194 def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 2195 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 2196 2197 // Calls 2198 def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 2199 (BL tglobaladdr:$dst)>; 2200 def : Pat<(PPCcall (i32 texternalsym:$dst)), 2201 (BL texternalsym:$dst)>; 2202 2203 2204 def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 2205 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 2206 2207 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 2208 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 2209 2210 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 2211 (TCRETURNri CTRRC:$dst, imm:$imm)>; 2212 2213 2214 2215 // Hi and Lo for Darwin Global Addresses. 2216 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 2217 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 2218 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 2219 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 2220 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 2221 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 2222 def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 2223 def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 2224 def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 2225 (ADDIS $in, tglobaltlsaddr:$g)>; 2226 def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 2227 (ADDI $in, tglobaltlsaddr:$g)>; 2228 def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 2229 (ADDIS $in, tglobaladdr:$g)>; 2230 def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 2231 (ADDIS $in, tconstpool:$g)>; 2232 def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 2233 (ADDIS $in, tjumptable:$g)>; 2234 def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 2235 (ADDIS $in, tblockaddress:$g)>; 2236 2237 // Standard shifts. These are represented separately from the real shifts above 2238 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift 2239 // amounts. 2240 def : Pat<(sra i32:$rS, i32:$rB), 2241 (SRAW $rS, $rB)>; 2242 def : Pat<(srl i32:$rS, i32:$rB), 2243 (SRW $rS, $rB)>; 2244 def : Pat<(shl i32:$rS, i32:$rB), 2245 (SLW $rS, $rB)>; 2246 2247 def : Pat<(zextloadi1 iaddr:$src), 2248 (LBZ iaddr:$src)>; 2249 def : Pat<(zextloadi1 xaddr:$src), 2250 (LBZX xaddr:$src)>; 2251 def : Pat<(extloadi1 iaddr:$src), 2252 (LBZ iaddr:$src)>; 2253 def : Pat<(extloadi1 xaddr:$src), 2254 (LBZX xaddr:$src)>; 2255 def : Pat<(extloadi8 iaddr:$src), 2256 (LBZ iaddr:$src)>; 2257 def : Pat<(extloadi8 xaddr:$src), 2258 (LBZX xaddr:$src)>; 2259 def : Pat<(extloadi16 iaddr:$src), 2260 (LHZ iaddr:$src)>; 2261 def : Pat<(extloadi16 xaddr:$src), 2262 (LHZX xaddr:$src)>; 2263 def : Pat<(f64 (extloadf32 iaddr:$src)), 2264 (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; 2265 def : Pat<(f64 (extloadf32 xaddr:$src)), 2266 (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; 2267 2268 def : Pat<(f64 (fextend f32:$src)), 2269 (COPY_TO_REGCLASS $src, F8RC)>; 2270 2271 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>; 2272 2273 // Additional FNMSUB patterns: -a*c + b == -(a*c - b) 2274 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B), 2275 (FNMSUB $A, $C, $B)>; 2276 def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B), 2277 (FNMSUB $A, $C, $B)>; 2278 def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B), 2279 (FNMSUBS $A, $C, $B)>; 2280 def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B), 2281 (FNMSUBS $A, $C, $B)>; 2282 2283 include "PPCInstrAltivec.td" 2284 include "PPCInstr64Bit.td" 2285 2286 2287 //===----------------------------------------------------------------------===// 2288 // PowerPC Instructions used for assembler/disassembler only 2289 // 2290 2291 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 2292 "isync", SprISYNC, []>; 2293 2294 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), 2295 "icbi $src", LdStICBI, []>; 2296 2297 def EIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2298 "eieio", LdStLoad, []>; 2299 2300 def WAIT : XForm_24_sync<31, 62, (outs), (ins i32imm:$L), 2301 "wait $L", LdStLoad, []>; 2302 2303 //===----------------------------------------------------------------------===// 2304 // PowerPC Assembler Instruction Aliases 2305 // 2306 2307 // Pseudo-instructions for alternate assembly syntax (never used by codegen). 2308 // These are aliases that require C++ handling to convert to the target 2309 // instruction, while InstAliases can be handled directly by tblgen. 2310 class PPCAsmPseudo<string asm, dag iops> 2311 : Instruction { 2312 let Namespace = "PPC"; 2313 bit PPC64 = 0; // Default value, override with isPPC64 2314 2315 let OutOperandList = (outs); 2316 let InOperandList = iops; 2317 let Pattern = []; 2318 let AsmString = asm; 2319 let isAsmParserOnly = 1; 2320 let isPseudo = 1; 2321 } 2322 2323 def : InstAlias<"sc", (SC 0)>; 2324 2325 def : InstAlias<"sync", (SYNC 0)>; 2326 def : InstAlias<"msync", (SYNC 0)>; 2327 def : InstAlias<"lwsync", (SYNC 1)>; 2328 def : InstAlias<"ptesync", (SYNC 2)>; 2329 2330 def : InstAlias<"wait", (WAIT 0)>; 2331 def : InstAlias<"waitrsv", (WAIT 1)>; 2332 def : InstAlias<"waitimpl", (WAIT 2)>; 2333 2334 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 2335 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 2336 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 2337 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 2338 2339 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 2340 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 2341 2342 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 2343 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 2344 2345 def : InstAlias<"xnop", (XORI R0, R0, 0)>; 2346 2347 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 2348 def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 2349 2350 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 2351 def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; 2352 2353 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; 2354 2355 def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; 2356 2357 def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 2358 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 2359 def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 2360 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 2361 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 2362 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 2363 def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm", 2364 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 2365 2366 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 2367 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 2368 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 2369 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>; 2370 2371 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 2372 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2373 def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 2374 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2375 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 2376 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2377 def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 2378 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2379 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 2380 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2381 def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 2382 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2383 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 2384 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2385 def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 2386 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 2387 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 2388 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2389 def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 2390 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2391 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 2392 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2393 def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n", 2394 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2395 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 2396 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2397 def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n", 2398 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2399 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 2400 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2401 def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 2402 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 2403 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 2404 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 2405 def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 2406 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 2407 2408 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 2409 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 2410 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 2411 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 2412 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 2413 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 2414 2415 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 2416 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 2417 def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 2418 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 2419 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 2420 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 2421 def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 2422 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 2423 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 2424 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 2425 def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 2426 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 2427 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 2428 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2429 def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 2430 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2431 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 2432 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2433 def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n", 2434 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2435 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 2436 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2437 def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n", 2438 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2439 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 2440 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2441 def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 2442 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 2443 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 2444 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 2445 def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 2446 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 2447 2448 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 2449 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 2450 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 2451 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 2452 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 2453 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 2454 2455 // These generic branch instruction forms are used for the assembler parser only. 2456 // Defs and Uses are conservative, since we don't know the BO value. 2457 let PPC970_Unit = 7 in { 2458 let Defs = [CTR], Uses = [CTR, RM] in { 2459 def gBC : BForm_3<16, 0, 0, (outs), 2460 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 2461 "bc $bo, $bi, $dst">; 2462 def gBCA : BForm_3<16, 1, 0, (outs), 2463 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 2464 "bca $bo, $bi, $dst">; 2465 } 2466 let Defs = [LR, CTR], Uses = [CTR, RM] in { 2467 def gBCL : BForm_3<16, 0, 1, (outs), 2468 (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), 2469 "bcl $bo, $bi, $dst">; 2470 def gBCLA : BForm_3<16, 1, 1, (outs), 2471 (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), 2472 "bcla $bo, $bi, $dst">; 2473 } 2474 let Defs = [CTR], Uses = [CTR, LR, RM] in 2475 def gBCLR : XLForm_2<19, 16, 0, (outs), 2476 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 2477 "bclr $bo, $bi, $bh", BrB, []>; 2478 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 2479 def gBCLRL : XLForm_2<19, 16, 1, (outs), 2480 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 2481 "bclrl $bo, $bi, $bh", BrB, []>; 2482 let Defs = [CTR], Uses = [CTR, LR, RM] in 2483 def gBCCTR : XLForm_2<19, 528, 0, (outs), 2484 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 2485 "bcctr $bo, $bi, $bh", BrB, []>; 2486 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 2487 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 2488 (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), 2489 "bcctrl $bo, $bi, $bh", BrB, []>; 2490 } 2491 def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 2492 def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 2493 def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 2494 def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 2495 2496 multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 2497 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 2498 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 2499 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 2500 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 2501 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 2502 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 2503 } 2504 multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 2505 : BranchSimpleMnemonic1<name, pm, bo> { 2506 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 2507 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 2508 } 2509 defm : BranchSimpleMnemonic2<"t", "", 12>; 2510 defm : BranchSimpleMnemonic2<"f", "", 4>; 2511 defm : BranchSimpleMnemonic2<"t", "-", 14>; 2512 defm : BranchSimpleMnemonic2<"f", "-", 6>; 2513 defm : BranchSimpleMnemonic2<"t", "+", 15>; 2514 defm : BranchSimpleMnemonic2<"f", "+", 7>; 2515 defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 2516 defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 2517 defm : BranchSimpleMnemonic1<"dzt", "", 10>; 2518 defm : BranchSimpleMnemonic1<"dzf", "", 2>; 2519 2520 multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 2521 def : InstAlias<"b"#name#pm#" $cc, $dst", 2522 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 2523 def : InstAlias<"b"#name#pm#" $dst", 2524 (BCC bibo, CR0, condbrtarget:$dst)>; 2525 2526 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 2527 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 2528 def : InstAlias<"b"#name#"a"#pm#" $dst", 2529 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 2530 2531 def : InstAlias<"b"#name#"lr"#pm#" $cc", 2532 (BCLR bibo, crrc:$cc)>; 2533 def : InstAlias<"b"#name#"lr"#pm, 2534 (BCLR bibo, CR0)>; 2535 2536 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 2537 (BCCTR bibo, crrc:$cc)>; 2538 def : InstAlias<"b"#name#"ctr"#pm, 2539 (BCCTR bibo, CR0)>; 2540 2541 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 2542 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 2543 def : InstAlias<"b"#name#"l"#pm#" $dst", 2544 (BCCL bibo, CR0, condbrtarget:$dst)>; 2545 2546 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 2547 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 2548 def : InstAlias<"b"#name#"la"#pm#" $dst", 2549 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 2550 2551 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 2552 (BCLRL bibo, crrc:$cc)>; 2553 def : InstAlias<"b"#name#"lrl"#pm, 2554 (BCLRL bibo, CR0)>; 2555 2556 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 2557 (BCCTRL bibo, crrc:$cc)>; 2558 def : InstAlias<"b"#name#"ctrl"#pm, 2559 (BCCTRL bibo, CR0)>; 2560 } 2561 multiclass BranchExtendedMnemonic<string name, int bibo> { 2562 defm : BranchExtendedMnemonicPM<name, "", bibo>; 2563 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 2564 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 2565 } 2566 defm : BranchExtendedMnemonic<"lt", 12>; 2567 defm : BranchExtendedMnemonic<"gt", 44>; 2568 defm : BranchExtendedMnemonic<"eq", 76>; 2569 defm : BranchExtendedMnemonic<"un", 108>; 2570 defm : BranchExtendedMnemonic<"so", 108>; 2571 defm : BranchExtendedMnemonic<"ge", 4>; 2572 defm : BranchExtendedMnemonic<"nl", 4>; 2573 defm : BranchExtendedMnemonic<"le", 36>; 2574 defm : BranchExtendedMnemonic<"ng", 36>; 2575 defm : BranchExtendedMnemonic<"ne", 68>; 2576 defm : BranchExtendedMnemonic<"nu", 100>; 2577 defm : BranchExtendedMnemonic<"ns", 100>; 2578 2579 def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 2580 def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 2581 def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 2582 def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 2583 def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>; 2584 def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 2585 def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>; 2586 def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 2587 2588 def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 2589 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 2590 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 2591 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 2592 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm:$imm)>; 2593 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 2594 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm:$imm)>; 2595 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 2596 2597 multiclass TrapExtendedMnemonic<string name, int to> { 2598 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 2599 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 2600 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 2601 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 2602 } 2603 defm : TrapExtendedMnemonic<"lt", 16>; 2604 defm : TrapExtendedMnemonic<"le", 20>; 2605 defm : TrapExtendedMnemonic<"eq", 4>; 2606 defm : TrapExtendedMnemonic<"ge", 12>; 2607 defm : TrapExtendedMnemonic<"gt", 8>; 2608 defm : TrapExtendedMnemonic<"nl", 12>; 2609 defm : TrapExtendedMnemonic<"ne", 24>; 2610 defm : TrapExtendedMnemonic<"ng", 20>; 2611 defm : TrapExtendedMnemonic<"llt", 2>; 2612 defm : TrapExtendedMnemonic<"lle", 6>; 2613 defm : TrapExtendedMnemonic<"lge", 5>; 2614 defm : TrapExtendedMnemonic<"lgt", 1>; 2615 defm : TrapExtendedMnemonic<"lnl", 5>; 2616 defm : TrapExtendedMnemonic<"lng", 6>; 2617 defm : TrapExtendedMnemonic<"u", 31>; 2618 2619
