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      1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // R600 Instruction format definitions.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
     15                 InstrItinClass itin>
     16     : AMDGPUInst <outs, ins, asm, pattern> {
     17 
     18   field bits<64> Inst;
     19   bit TransOnly = 0;
     20   bit Trig = 0;
     21   bit Op3 = 0;
     22   bit isVector = 0;
     23   bits<2> FlagOperandIdx = 0;
     24   bit Op1 = 0;
     25   bit Op2 = 0;
     26   bit LDS_1A = 0;
     27   bit LDS_1A1D = 0;
     28   bit HasNativeOperands = 0;
     29   bit VTXInst = 0;
     30   bit TEXInst = 0;
     31   bit ALUInst = 0;
     32 
     33   let Namespace = "AMDGPU";
     34   let OutOperandList = outs;
     35   let InOperandList = ins;
     36   let AsmString = asm;
     37   let Pattern = pattern;
     38   let Itinerary = itin;
     39 
     40   let TSFlags{0} = TransOnly;
     41   let TSFlags{4} = Trig;
     42   let TSFlags{5} = Op3;
     43 
     44   // Vector instructions are instructions that must fill all slots in an
     45   // instruction group
     46   let TSFlags{6} = isVector;
     47   let TSFlags{8-7} = FlagOperandIdx;
     48   let TSFlags{9} = HasNativeOperands;
     49   let TSFlags{10} = Op1;
     50   let TSFlags{11} = Op2;
     51   let TSFlags{12} = VTXInst;
     52   let TSFlags{13} = TEXInst;
     53   let TSFlags{14} = ALUInst;
     54   let TSFlags{15} = LDS_1A;
     55   let TSFlags{16} = LDS_1A1D;
     56 }
     57 
     58 //===----------------------------------------------------------------------===//
     59 // ALU instructions
     60 //===----------------------------------------------------------------------===//
     61 
     62 class R600_ALU_LDS_Word0 {
     63   field bits<32> Word0;
     64 
     65   bits<11> src0;
     66   bits<1>  src0_rel;
     67   bits<11> src1;
     68   bits<1>  src1_rel;
     69   bits<3>  index_mode = 0;
     70   bits<2>  pred_sel;
     71   bits<1>  last;
     72 
     73   bits<9>  src0_sel  = src0{8-0};
     74   bits<2>  src0_chan = src0{10-9};
     75   bits<9>  src1_sel  = src1{8-0};
     76   bits<2>  src1_chan = src1{10-9};
     77 
     78   let Word0{8-0}   = src0_sel;
     79   let Word0{9}     = src0_rel;
     80   let Word0{11-10} = src0_chan;
     81   let Word0{21-13} = src1_sel;
     82   let Word0{22}    = src1_rel;
     83   let Word0{24-23} = src1_chan;
     84   let Word0{28-26} = index_mode;
     85   let Word0{30-29} = pred_sel;
     86   let Word0{31}    = last;
     87 }
     88 
     89 class R600ALU_Word0 : R600_ALU_LDS_Word0 {
     90 
     91   bits<1>  src0_neg;
     92   bits<1>  src1_neg;
     93 
     94   let Word0{12}    = src0_neg;
     95   let Word0{25}    = src1_neg;
     96 }
     97 
     98 class R600ALU_Word1 {
     99   field bits<32> Word1;
    100 
    101   bits<11> dst;
    102   bits<3>  bank_swizzle;
    103   bits<1>  dst_rel;
    104   bits<1>  clamp;
    105 
    106   bits<7>  dst_sel  = dst{6-0};
    107   bits<2>  dst_chan = dst{10-9};
    108 
    109   let Word1{20-18} = bank_swizzle;
    110   let Word1{27-21} = dst_sel;
    111   let Word1{28}    = dst_rel;
    112   let Word1{30-29} = dst_chan;
    113   let Word1{31}    = clamp;
    114 }
    115 
    116 class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
    117 
    118   bits<1>  src0_abs;
    119   bits<1>  src1_abs;
    120   bits<1>  update_exec_mask;
    121   bits<1>  update_pred;
    122   bits<1>  write;
    123   bits<2>  omod;
    124 
    125   let Word1{0}     = src0_abs;
    126   let Word1{1}     = src1_abs;
    127   let Word1{2}     = update_exec_mask;
    128   let Word1{3}     = update_pred;
    129   let Word1{4}     = write;
    130   let Word1{6-5}   = omod;
    131   let Word1{17-7}  = alu_inst;
    132 }
    133 
    134 class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
    135 
    136   bits<11> src2;
    137   bits<1>  src2_rel;
    138   bits<1>  src2_neg;
    139 
    140   bits<9>  src2_sel = src2{8-0};
    141   bits<2>  src2_chan = src2{10-9};
    142 
    143   let Word1{8-0}   = src2_sel;
    144   let Word1{9}     = src2_rel;
    145   let Word1{11-10} = src2_chan;
    146   let Word1{12}    = src2_neg;
    147   let Word1{17-13} = alu_inst;
    148 }
    149 
    150 class R600LDS_Word1 {
    151   field bits<32> Word1;
    152 
    153   bits<11> src2;
    154   bits<9>  src2_sel  = src2{8-0};
    155   bits<2>  src2_chan = src2{10-9};
    156   bits<1>  src2_rel;
    157   // offset specifies the stride offset to the second set of data to be read
    158   // from.  This is a dword offset.
    159   bits<5>  alu_inst = 17; // OP3_INST_LDS_IDX_OP
    160   bits<3>  bank_swizzle;
    161   bits<6>  lds_op;
    162   bits<2>  dst_chan = 0;
    163 
    164   let Word1{8-0}   = src2_sel;
    165   let Word1{9}     = src2_rel;
    166   let Word1{11-10} = src2_chan;
    167   let Word1{17-13} = alu_inst;
    168   let Word1{20-18} = bank_swizzle;
    169   let Word1{26-21} = lds_op;
    170   let Word1{30-29} = dst_chan;
    171 }
    172 
    173 
    174 /*
    175 XXX: R600 subtarget uses a slightly different encoding than the other
    176 subtargets.  We currently handle this in R600MCCodeEmitter, but we may
    177 want to use these instruction classes in the future.
    178 
    179 class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
    180 
    181   bits<1>  fog_merge;
    182   bits<10> alu_inst;
    183 
    184   let Inst{37}    = fog_merge;
    185   let Inst{39-38} = omod;
    186   let Inst{49-40} = alu_inst;
    187 }
    188 
    189 class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
    190 
    191   bits<11> alu_inst;
    192 
    193   let Inst{38-37} = omod;
    194   let Inst{49-39} = alu_inst;
    195 }
    196 */
    197 
    198 //===----------------------------------------------------------------------===//
    199 // Vertex Fetch instructions
    200 //===----------------------------------------------------------------------===//
    201 
    202 class VTX_WORD0 {
    203   field bits<32> Word0;
    204   bits<7> src_gpr;
    205   bits<5> VC_INST;
    206   bits<2> FETCH_TYPE;
    207   bits<1> FETCH_WHOLE_QUAD;
    208   bits<8> BUFFER_ID;
    209   bits<1> SRC_REL;
    210   bits<2> SRC_SEL_X;
    211 
    212   let Word0{4-0}   = VC_INST;
    213   let Word0{6-5}   = FETCH_TYPE;
    214   let Word0{7}     = FETCH_WHOLE_QUAD;
    215   let Word0{15-8}  = BUFFER_ID;
    216   let Word0{22-16} = src_gpr;
    217   let Word0{23}    = SRC_REL;
    218   let Word0{25-24} = SRC_SEL_X;
    219 }
    220 
    221 class VTX_WORD0_eg : VTX_WORD0 {
    222 
    223   bits<6> MEGA_FETCH_COUNT;
    224 
    225   let Word0{31-26} = MEGA_FETCH_COUNT;
    226 }
    227 
    228 class VTX_WORD0_cm : VTX_WORD0 {
    229 
    230   bits<2> SRC_SEL_Y;
    231   bits<2> STRUCTURED_READ;
    232   bits<1> LDS_REQ;
    233   bits<1> COALESCED_READ;
    234 
    235   let Word0{27-26} = SRC_SEL_Y;
    236   let Word0{29-28} = STRUCTURED_READ;
    237   let Word0{30}    = LDS_REQ;
    238   let Word0{31}    = COALESCED_READ;
    239 }
    240 
    241 class VTX_WORD1_GPR {
    242   field bits<32> Word1;
    243   bits<7> dst_gpr;
    244   bits<1> DST_REL;
    245   bits<3> DST_SEL_X;
    246   bits<3> DST_SEL_Y;
    247   bits<3> DST_SEL_Z;
    248   bits<3> DST_SEL_W;
    249   bits<1> USE_CONST_FIELDS;
    250   bits<6> DATA_FORMAT;
    251   bits<2> NUM_FORMAT_ALL;
    252   bits<1> FORMAT_COMP_ALL;
    253   bits<1> SRF_MODE_ALL;
    254 
    255   let Word1{6-0} = dst_gpr;
    256   let Word1{7}    = DST_REL;
    257   let Word1{8}    = 0; // Reserved
    258   let Word1{11-9} = DST_SEL_X;
    259   let Word1{14-12} = DST_SEL_Y;
    260   let Word1{17-15} = DST_SEL_Z;
    261   let Word1{20-18} = DST_SEL_W;
    262   let Word1{21}    = USE_CONST_FIELDS;
    263   let Word1{27-22} = DATA_FORMAT;
    264   let Word1{29-28} = NUM_FORMAT_ALL;
    265   let Word1{30}    = FORMAT_COMP_ALL;
    266   let Word1{31}    = SRF_MODE_ALL;
    267 }
    268 
    269 //===----------------------------------------------------------------------===//
    270 // Texture fetch instructions
    271 //===----------------------------------------------------------------------===//
    272 
    273 class TEX_WORD0 {
    274   field bits<32> Word0;
    275 
    276   bits<5> TEX_INST;
    277   bits<2> INST_MOD;
    278   bits<1> FETCH_WHOLE_QUAD;
    279   bits<8> RESOURCE_ID;
    280   bits<7> SRC_GPR;
    281   bits<1> SRC_REL;
    282   bits<1> ALT_CONST;
    283   bits<2> RESOURCE_INDEX_MODE;
    284   bits<2> SAMPLER_INDEX_MODE;
    285 
    286   let Word0{4-0} = TEX_INST;
    287   let Word0{6-5} = INST_MOD;
    288   let Word0{7} = FETCH_WHOLE_QUAD;
    289   let Word0{15-8} = RESOURCE_ID;
    290   let Word0{22-16} = SRC_GPR;
    291   let Word0{23} = SRC_REL;
    292   let Word0{24} = ALT_CONST;
    293   let Word0{26-25} = RESOURCE_INDEX_MODE;
    294   let Word0{28-27} = SAMPLER_INDEX_MODE;
    295 }
    296 
    297 class TEX_WORD1 {
    298   field bits<32> Word1;
    299 
    300   bits<7> DST_GPR;
    301   bits<1> DST_REL;
    302   bits<3> DST_SEL_X;
    303   bits<3> DST_SEL_Y;
    304   bits<3> DST_SEL_Z;
    305   bits<3> DST_SEL_W;
    306   bits<7> LOD_BIAS;
    307   bits<1> COORD_TYPE_X;
    308   bits<1> COORD_TYPE_Y;
    309   bits<1> COORD_TYPE_Z;
    310   bits<1> COORD_TYPE_W;
    311 
    312   let Word1{6-0} = DST_GPR;
    313   let Word1{7} = DST_REL;
    314   let Word1{11-9} = DST_SEL_X;
    315   let Word1{14-12} = DST_SEL_Y;
    316   let Word1{17-15} = DST_SEL_Z;
    317   let Word1{20-18} = DST_SEL_W;
    318   let Word1{27-21} = LOD_BIAS;
    319   let Word1{28} = COORD_TYPE_X;
    320   let Word1{29} = COORD_TYPE_Y;
    321   let Word1{30} = COORD_TYPE_Z;
    322   let Word1{31} = COORD_TYPE_W;
    323 }
    324 
    325 class TEX_WORD2 {
    326   field bits<32> Word2;
    327 
    328   bits<5> OFFSET_X;
    329   bits<5> OFFSET_Y;
    330   bits<5> OFFSET_Z;
    331   bits<5> SAMPLER_ID;
    332   bits<3> SRC_SEL_X;
    333   bits<3> SRC_SEL_Y;
    334   bits<3> SRC_SEL_Z;
    335   bits<3> SRC_SEL_W;
    336 
    337   let Word2{4-0} = OFFSET_X;
    338   let Word2{9-5} = OFFSET_Y;
    339   let Word2{14-10} = OFFSET_Z;
    340   let Word2{19-15} = SAMPLER_ID;
    341   let Word2{22-20} = SRC_SEL_X;
    342   let Word2{25-23} = SRC_SEL_Y;
    343   let Word2{28-26} = SRC_SEL_Z;
    344   let Word2{31-29} = SRC_SEL_W;
    345 }
    346 
    347 //===----------------------------------------------------------------------===//
    348 // Control Flow Instructions
    349 //===----------------------------------------------------------------------===//
    350 
    351 class CF_WORD1_R600 {
    352   field bits<32> Word1;
    353 
    354   bits<3> POP_COUNT;
    355   bits<5> CF_CONST;
    356   bits<2> COND;
    357   bits<3> COUNT;
    358   bits<6> CALL_COUNT;
    359   bits<1> COUNT_3;
    360   bits<1> END_OF_PROGRAM;
    361   bits<1> VALID_PIXEL_MODE;
    362   bits<7> CF_INST;
    363   bits<1> WHOLE_QUAD_MODE;
    364   bits<1> BARRIER;
    365 
    366   let Word1{2-0} = POP_COUNT;
    367   let Word1{7-3} = CF_CONST;
    368   let Word1{9-8} = COND;
    369   let Word1{12-10} = COUNT;
    370   let Word1{18-13} = CALL_COUNT;
    371   let Word1{19} = COUNT_3;
    372   let Word1{21} = END_OF_PROGRAM;
    373   let Word1{22} = VALID_PIXEL_MODE;
    374   let Word1{29-23} = CF_INST;
    375   let Word1{30} = WHOLE_QUAD_MODE;
    376   let Word1{31} = BARRIER;
    377 }
    378 
    379 class CF_WORD0_EG {
    380   field bits<32> Word0;
    381 
    382   bits<24> ADDR;
    383   bits<3> JUMPTABLE_SEL;
    384 
    385   let Word0{23-0} = ADDR;
    386   let Word0{26-24} = JUMPTABLE_SEL;
    387 }
    388 
    389 class CF_WORD1_EG {
    390   field bits<32> Word1;
    391 
    392   bits<3> POP_COUNT;
    393   bits<5> CF_CONST;
    394   bits<2> COND;
    395   bits<6> COUNT;
    396   bits<1> VALID_PIXEL_MODE;
    397   bits<1> END_OF_PROGRAM;
    398   bits<8> CF_INST;
    399   bits<1> BARRIER;
    400 
    401   let Word1{2-0} = POP_COUNT;
    402   let Word1{7-3} = CF_CONST;
    403   let Word1{9-8} = COND;
    404   let Word1{15-10} = COUNT;
    405   let Word1{20} = VALID_PIXEL_MODE;
    406   let Word1{21} = END_OF_PROGRAM;
    407   let Word1{29-22} = CF_INST;
    408   let Word1{31} = BARRIER;
    409 }
    410 
    411 class CF_ALU_WORD0 {
    412   field bits<32> Word0;
    413 
    414   bits<22> ADDR;
    415   bits<4> KCACHE_BANK0;
    416   bits<4> KCACHE_BANK1;
    417   bits<2> KCACHE_MODE0;
    418 
    419   let Word0{21-0} = ADDR;
    420   let Word0{25-22} = KCACHE_BANK0;
    421   let Word0{29-26} = KCACHE_BANK1;
    422   let Word0{31-30} = KCACHE_MODE0;
    423 }
    424 
    425 class CF_ALU_WORD1 {
    426   field bits<32> Word1;
    427 
    428   bits<2> KCACHE_MODE1;
    429   bits<8> KCACHE_ADDR0;
    430   bits<8> KCACHE_ADDR1;
    431   bits<7> COUNT;
    432   bits<1> ALT_CONST;
    433   bits<4> CF_INST;
    434   bits<1> WHOLE_QUAD_MODE;
    435   bits<1> BARRIER;
    436 
    437   let Word1{1-0} = KCACHE_MODE1;
    438   let Word1{9-2} = KCACHE_ADDR0;
    439   let Word1{17-10} = KCACHE_ADDR1;
    440   let Word1{24-18} = COUNT;
    441   let Word1{25} = ALT_CONST;
    442   let Word1{29-26} = CF_INST;
    443   let Word1{30} = WHOLE_QUAD_MODE;
    444   let Word1{31} = BARRIER;
    445 }
    446 
    447 class CF_ALLOC_EXPORT_WORD0_RAT {
    448   field bits<32> Word0;
    449 
    450   bits<4> rat_id;
    451   bits<6> rat_inst;
    452   bits<2> rim;
    453   bits<2> type;
    454   bits<7> rw_gpr;
    455   bits<1> rw_rel;
    456   bits<7> index_gpr;
    457   bits<2> elem_size;
    458 
    459   let Word0{3-0}   = rat_id;
    460   let Word0{9-4}   = rat_inst;
    461   let Word0{10}    = 0; // Reserved
    462   let Word0{12-11} = rim;
    463   let Word0{14-13} = type;
    464   let Word0{21-15} = rw_gpr;
    465   let Word0{22}    = rw_rel;
    466   let Word0{29-23} = index_gpr;
    467   let Word0{31-30} = elem_size;
    468 }
    469 
    470 class CF_ALLOC_EXPORT_WORD1_BUF {
    471   field bits<32> Word1;
    472 
    473   bits<12> array_size;
    474   bits<4>  comp_mask;
    475   bits<4>  burst_count;
    476   bits<1>  vpm;
    477   bits<1>  eop;
    478   bits<8>  cf_inst;
    479   bits<1>  mark;
    480   bits<1>  barrier;
    481 
    482   let Word1{11-0} = array_size;
    483   let Word1{15-12} = comp_mask;
    484   let Word1{19-16} = burst_count;
    485   let Word1{20}    = vpm;
    486   let Word1{21}    = eop;
    487   let Word1{29-22} = cf_inst;
    488   let Word1{30}    = mark;
    489   let Word1{31}    = barrier;
    490 }
    491