1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "SparcTargetMachine.h" 14 #include "Sparc.h" 15 #include "llvm/CodeGen/Passes.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/Support/TargetRegistry.h" 18 using namespace llvm; 19 20 extern "C" void LLVMInitializeSparcTarget() { 21 // Register the target. 22 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 23 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); 24 } 25 26 /// SparcTargetMachine ctor - Create an ILP32 architecture model 27 /// 28 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 29 StringRef CPU, StringRef FS, 30 const TargetOptions &Options, 31 Reloc::Model RM, CodeModel::Model CM, 32 CodeGenOpt::Level OL, 33 bool is64bit) 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS, is64bit), 36 DL(Subtarget.getDataLayout()), 37 InstrInfo(Subtarget), 38 TLInfo(*this), TSInfo(*this), 39 FrameLowering(Subtarget) { 40 initAsmInfo(); 41 } 42 43 namespace { 44 /// Sparc Code Generator Pass Configuration Options. 45 class SparcPassConfig : public TargetPassConfig { 46 public: 47 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) 48 : TargetPassConfig(TM, PM) {} 49 50 SparcTargetMachine &getSparcTargetMachine() const { 51 return getTM<SparcTargetMachine>(); 52 } 53 54 virtual bool addInstSelector(); 55 virtual bool addPreEmitPass(); 56 }; 57 } // namespace 58 59 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 60 return new SparcPassConfig(this, PM); 61 } 62 63 bool SparcPassConfig::addInstSelector() { 64 addPass(createSparcISelDag(getSparcTargetMachine())); 65 return false; 66 } 67 68 /// addPreEmitPass - This pass may be implemented by targets that want to run 69 /// passes immediately before machine code is emitted. This should return 70 /// true if -print-machineinstrs should print out the code after the passes. 71 bool SparcPassConfig::addPreEmitPass(){ 72 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); 73 return true; 74 } 75 76 void SparcV8TargetMachine::anchor() { } 77 78 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 79 StringRef TT, StringRef CPU, 80 StringRef FS, 81 const TargetOptions &Options, 82 Reloc::Model RM, 83 CodeModel::Model CM, 84 CodeGenOpt::Level OL) 85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 86 } 87 88 void SparcV9TargetMachine::anchor() { } 89 90 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 91 StringRef TT, StringRef CPU, 92 StringRef FS, 93 const TargetOptions &Options, 94 Reloc::Model RM, 95 CodeModel::Model CM, 96 CodeGenOpt::Level OL) 97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 98 } 99
