1 //===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Target-independent interfaces which we are implementing 12 //===----------------------------------------------------------------------===// 13 14 include "llvm/Target/Target.td" 15 16 //===----------------------------------------------------------------------===// 17 // SystemZ supported processors and features 18 //===----------------------------------------------------------------------===// 19 20 include "SystemZProcessors.td" 21 22 //===----------------------------------------------------------------------===// 23 // Register file description 24 //===----------------------------------------------------------------------===// 25 26 include "SystemZRegisterInfo.td" 27 28 //===----------------------------------------------------------------------===// 29 // Calling convention description 30 //===----------------------------------------------------------------------===// 31 32 include "SystemZCallingConv.td" 33 34 //===----------------------------------------------------------------------===// 35 // Instruction descriptions 36 //===----------------------------------------------------------------------===// 37 38 include "SystemZOperators.td" 39 include "SystemZOperands.td" 40 include "SystemZPatterns.td" 41 include "SystemZInstrFormats.td" 42 include "SystemZInstrInfo.td" 43 include "SystemZInstrFP.td" 44 45 def SystemZInstrInfo : InstrInfo {} 46 47 //===----------------------------------------------------------------------===// 48 // Assembly parser 49 //===----------------------------------------------------------------------===// 50 51 def SystemZAsmParser : AsmParser { 52 let ShouldEmitMatchRegisterName = 0; 53 } 54 55 //===----------------------------------------------------------------------===// 56 // Assembly writer 57 //===----------------------------------------------------------------------===// 58 59 def SystemZAsmWriter : AsmWriter { 60 string AsmWriterClassName = "InstPrinter"; 61 bit isMCAsmWriter = 1; 62 } 63 64 //===----------------------------------------------------------------------===// 65 // Top-level target declaration 66 //===----------------------------------------------------------------------===// 67 68 def SystemZ : Target { 69 let InstructionSet = SystemZInstrInfo; 70 let AssemblyParsers = [SystemZAsmParser]; 71 let AssemblyWriters = [SystemZAsmWriter]; 72 } 73
